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382 lines
16 KiB
C
382 lines
16 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for GDMA
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file GDMA.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for GDMA
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*
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* CMSIS Peripheral Access Layer for GDMA
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*/
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#if !defined(GDMA_H_)
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#define GDMA_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- GDMA Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup GDMA_Peripheral_Access_Layer GDMA Peripheral Access Layer
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* @{
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*/
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/** GDMA - Size of Registers Arrays */
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#define GDMA_CH_COUNT 4u
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/** GDMA - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[64];
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struct { /* offset: 0x40, array step: 0x40 */
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__IO uint32_t SADR; /**< DMA SOURCE ADDRESS REGISTERS, array offset: 0x40, array step: 0x40 */
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__IO uint32_t DADR; /**< DMA DESTINATION ADDRESS REGISTERS, array offset: 0x44, array step: 0x40 */
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__IO uint32_t LLI; /**< DMA CHANNEL LINKED LIST ITEM REGISTERS, array offset: 0x48, array step: 0x40 */
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__IO uint32_t CTRL; /**< DMA CONTROL REGISTERS, array offset: 0x4C, array step: 0x40 */
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__IO uint32_t CONFIG; /**< DMA CONFIGURE REGISTERS, array offset: 0x50, array step: 0x40 */
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__IO uint32_t CHL_EN; /**< DMA CHANNEL ENABLE REGISTERS, array offset: 0x54, array step: 0x40 */
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__IO uint32_t CHL_STOP; /**< DMA CHANNEL STOP REGISTERS, array offset: 0x58, array step: 0x40 */
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__IO uint32_t CHNL_INT; /**< DMA INT REGISTERS, array offset: 0x5C, array step: 0x40 */
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uint8_t RESERVED_0[16];
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__IO uint32_t NUM_OF_DESCRIPTOR; /**< the number of descriptor, array offset: 0x70, array step: 0x40 */
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uint8_t RESERVED_1[12];
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} CH[GDMA_CH_COUNT];
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} GDMA_Type;
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/* ----------------------------------------------------------------------------
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-- GDMA Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup GDMA_Register_Masks GDMA Register Masks
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* @{
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*/
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/*! @name SADR - DMA SOURCE ADDRESS REGISTERS */
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/*! @{ */
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#define GDMA_SADR_SRCADDR_MASK (0xFFFFFFFFU)
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#define GDMA_SADR_SRCADDR_SHIFT (0U)
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/*! SRCADDR - SOURCE ADDRESS */
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#define GDMA_SADR_SRCADDR(x) (((uint32_t)(((uint32_t)(x)) << GDMA_SADR_SRCADDR_SHIFT)) & GDMA_SADR_SRCADDR_MASK)
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/*! @} */
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/* The count of GDMA_SADR */
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#define GDMA_SADR_COUNT (4U)
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/*! @name DADR - DMA DESTINATION ADDRESS REGISTERS */
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/*! @{ */
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#define GDMA_DADR_DESTADDR_MASK (0xFFFFFFFFU)
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#define GDMA_DADR_DESTADDR_SHIFT (0U)
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/*! DESTADDR - DESTINATION ADDRESS */
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#define GDMA_DADR_DESTADDR(x) (((uint32_t)(((uint32_t)(x)) << GDMA_DADR_DESTADDR_SHIFT)) & GDMA_DADR_DESTADDR_MASK)
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/*! @} */
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/* The count of GDMA_DADR */
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#define GDMA_DADR_COUNT (4U)
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/*! @name LLI - DMA CHANNEL LINKED LIST ITEM REGISTERS */
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/*! @{ */
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#define GDMA_LLI_STOP_MASK (0x1U)
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#define GDMA_LLI_STOP_SHIFT (0U)
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/*! STOP - STOP the channel after transaction is finished */
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#define GDMA_LLI_STOP(x) (((uint32_t)(((uint32_t)(x)) << GDMA_LLI_STOP_SHIFT)) & GDMA_LLI_STOP_MASK)
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#define GDMA_LLI_DESC_INT_EN_MASK (0x2U)
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#define GDMA_LLI_DESC_INT_EN_SHIFT (1U)
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/*! DESC_INT_EN - the interrupt enable for descriptor finish */
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#define GDMA_LLI_DESC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GDMA_LLI_DESC_INT_EN_SHIFT)) & GDMA_LLI_DESC_INT_EN_MASK)
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#define GDMA_LLI_LLI_MASK (0xFFFFFFF0U)
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#define GDMA_LLI_LLI_SHIFT (4U)
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/*! LLI - LINKED LIST ITEM ADDRESS */
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#define GDMA_LLI_LLI(x) (((uint32_t)(((uint32_t)(x)) << GDMA_LLI_LLI_SHIFT)) & GDMA_LLI_LLI_MASK)
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/*! @} */
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/* The count of GDMA_LLI */
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#define GDMA_LLI_COUNT (4U)
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/*! @name CTRL - DMA CONTROL REGISTERS */
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/*! @{ */
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#define GDMA_CTRL_LEN_MASK (0x1FFFU)
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#define GDMA_CTRL_LEN_SHIFT (0U)
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/*! LEN - Length of the transfer in bytes */
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#define GDMA_CTRL_LEN(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_LEN_SHIFT)) & GDMA_CTRL_LEN_MASK)
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#define GDMA_CTRL_DESTBSIZE_MASK (0xE0000U)
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#define GDMA_CTRL_DESTBSIZE_SHIFT (17U)
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/*! DESTBSIZE - Destination peripheral/memory transfer burst size */
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#define GDMA_CTRL_DESTBSIZE(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_DESTBSIZE_SHIFT)) & GDMA_CTRL_DESTBSIZE_MASK)
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#define GDMA_CTRL_SRCBSIZE_MASK (0x700000U)
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#define GDMA_CTRL_SRCBSIZE_SHIFT (20U)
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/*! SRCBSIZE - Source peripheral/memory transfer burst size */
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#define GDMA_CTRL_SRCBSIZE(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_SRCBSIZE_SHIFT)) & GDMA_CTRL_SRCBSIZE_MASK)
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#define GDMA_CTRL_DESTWIDTH_MASK (0x1800000U)
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#define GDMA_CTRL_DESTWIDTH_SHIFT (23U)
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/*! DESTWIDTH - Destination peripheral/memory transfer width */
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#define GDMA_CTRL_DESTWIDTH(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_DESTWIDTH_SHIFT)) & GDMA_CTRL_DESTWIDTH_MASK)
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#define GDMA_CTRL_SRCWIDTH_MASK (0x6000000U)
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#define GDMA_CTRL_SRCWIDTH_SHIFT (25U)
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/*! SRCWIDTH - Source peripheral/memory transfer width */
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#define GDMA_CTRL_SRCWIDTH(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_SRCWIDTH_SHIFT)) & GDMA_CTRL_SRCWIDTH_MASK)
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#define GDMA_CTRL_DESTADDRINC_MASK (0x8000000U)
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#define GDMA_CTRL_DESTADDRINC_SHIFT (27U)
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/*! DESTADDRINC - destination address increment */
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#define GDMA_CTRL_DESTADDRINC(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_DESTADDRINC_SHIFT)) & GDMA_CTRL_DESTADDRINC_MASK)
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#define GDMA_CTRL_SRCADDRINC_MASK (0x10000000U)
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#define GDMA_CTRL_SRCADDRINC_SHIFT (28U)
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/*! SRCADDRINC - Source address increment */
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#define GDMA_CTRL_SRCADDRINC(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_SRCADDRINC_SHIFT)) & GDMA_CTRL_SRCADDRINC_MASK)
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#define GDMA_CTRL_PROT_MASK (0xE0000000U)
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#define GDMA_CTRL_PROT_SHIFT (29U)
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/*! PROT - Protection info for AHB master bus */
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#define GDMA_CTRL_PROT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CTRL_PROT_SHIFT)) & GDMA_CTRL_PROT_MASK)
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/*! @} */
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/* The count of GDMA_CTRL */
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#define GDMA_CTRL_COUNT (4U)
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/*! @name CONFIG - DMA CONFIGURE REGISTERS */
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/*! @{ */
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#define GDMA_CONFIG_LLE_MASK (0x1U)
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#define GDMA_CONFIG_LLE_SHIFT (0U)
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/*! LLE - Link List Enable */
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#define GDMA_CONFIG_LLE(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_LLE_SHIFT)) & GDMA_CONFIG_LLE_MASK)
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#define GDMA_CONFIG_HW_EN_SRC_MASK (0x38000000U)
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#define GDMA_CONFIG_HW_EN_SRC_SHIFT (27U)
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/*! HW_EN_SRC - hardware enable trigger source */
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#define GDMA_CONFIG_HW_EN_SRC(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_HW_EN_SRC_SHIFT)) & GDMA_CONFIG_HW_EN_SRC_MASK)
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#define GDMA_CONFIG_HW_EN_MASK (0x40000000U)
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#define GDMA_CONFIG_HW_EN_SHIFT (30U)
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/*! HW_EN - Hardware enable configuration of current channel */
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#define GDMA_CONFIG_HW_EN(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_HW_EN_SHIFT)) & GDMA_CONFIG_HW_EN_MASK)
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#define GDMA_CONFIG_FIFO_EMPTY_MASK (0x80000000U)
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#define GDMA_CONFIG_FIFO_EMPTY_SHIFT (31U)
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/*! FIFO_EMPTY - FIFO status of current channel */
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#define GDMA_CONFIG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CONFIG_FIFO_EMPTY_SHIFT)) & GDMA_CONFIG_FIFO_EMPTY_MASK)
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/*! @} */
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/* The count of GDMA_CONFIG */
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#define GDMA_CONFIG_COUNT (4U)
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/*! @name CHL_EN - DMA CHANNEL ENABLE REGISTERS */
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/*! @{ */
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#define GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_MASK (0xFU)
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#define GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_SHIFT (0U)
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/*! CHL_PRIORITY_WEIGHT - DMA Channel Priority Weight */
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#define GDMA_CHL_EN_CHL_PRIORITY_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_SHIFT)) & GDMA_CHL_EN_CHL_PRIORITY_WEIGHT_MASK)
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#define GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_MASK (0xF0U)
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#define GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_SHIFT (4U)
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/*! TEST_BUS_SIGNAL_SEL - TEST_BUS_SIGNAL_SEL */
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#define GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_SHIFT)) & GDMA_CHL_EN_TEST_BUS_SIGNAL_SEL_MASK)
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#define GDMA_CHL_EN_CHL_EN_MASK (0x80000000U)
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#define GDMA_CHL_EN_CHL_EN_SHIFT (31U)
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/*! CHL_EN - Enable/Disable the channel */
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#define GDMA_CHL_EN_CHL_EN(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_EN_CHL_EN_SHIFT)) & GDMA_CHL_EN_CHL_EN_MASK)
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/*! @} */
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/* The count of GDMA_CHL_EN */
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#define GDMA_CHL_EN_COUNT (4U)
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/*! @name CHL_STOP - DMA CHANNEL STOP REGISTERS */
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/*! @{ */
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#define GDMA_CHL_STOP_CHL_STOP_MASK (0x80000000U)
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#define GDMA_CHL_STOP_CHL_STOP_SHIFT (31U)
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/*! CHL_STOP - Stop the running channel */
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#define GDMA_CHL_STOP_CHL_STOP(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHL_STOP_CHL_STOP_SHIFT)) & GDMA_CHL_STOP_CHL_STOP_MASK)
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/*! @} */
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/* The count of GDMA_CHL_STOP */
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#define GDMA_CHL_STOP_COUNT (4U)
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/*! @name CHNL_INT - DMA INT REGISTERS */
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/*! @{ */
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#define GDMA_CHNL_INT_MASK_BLOCKINT_MASK (0x1U)
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#define GDMA_CHNL_INT_MASK_BLOCKINT_SHIFT (0U)
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/*! MASK_BLOCKINT - DMA channel block transfer interrupt mask bit */
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#define GDMA_CHNL_INT_MASK_BLOCKINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_BLOCKINT_SHIFT)) & GDMA_CHNL_INT_MASK_BLOCKINT_MASK)
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#define GDMA_CHNL_INT_STATUS_BLOCKINT_MASK (0x2U)
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#define GDMA_CHNL_INT_STATUS_BLOCKINT_SHIFT (1U)
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/*! STATUS_BLOCKINT - DMA channel block transfer interrupt bit */
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#define GDMA_CHNL_INT_STATUS_BLOCKINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_BLOCKINT_SHIFT)) & GDMA_CHNL_INT_STATUS_BLOCKINT_MASK)
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#define GDMA_CHNL_INT_MASK_TFRINT_MASK (0x4U)
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#define GDMA_CHNL_INT_MASK_TFRINT_SHIFT (2U)
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/*! MASK_TFRINT - transfer interrupt mask bit */
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#define GDMA_CHNL_INT_MASK_TFRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_TFRINT_SHIFT)) & GDMA_CHNL_INT_MASK_TFRINT_MASK)
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#define GDMA_CHNL_INT_STATUS_TFRINT_MASK (0x8U)
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#define GDMA_CHNL_INT_STATUS_TFRINT_SHIFT (3U)
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/*! STATUS_TFRINT - transfer interrupt bit */
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#define GDMA_CHNL_INT_STATUS_TFRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_TFRINT_SHIFT)) & GDMA_CHNL_INT_STATUS_TFRINT_MASK)
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#define GDMA_CHNL_INT_MASK_BUSERRINT_MASK (0x10U)
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#define GDMA_CHNL_INT_MASK_BUSERRINT_SHIFT (4U)
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/*! MASK_BUSERRINT - DMA channel bus error interrupt mask bit */
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#define GDMA_CHNL_INT_MASK_BUSERRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_BUSERRINT_SHIFT)) & GDMA_CHNL_INT_MASK_BUSERRINT_MASK)
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#define GDMA_CHNL_INT_STATUS_BUSERRINT_MASK (0x20U)
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#define GDMA_CHNL_INT_STATUS_BUSERRINT_SHIFT (5U)
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/*! STATUS_BUSERRINT - DMA channel bus error interrupt bit */
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#define GDMA_CHNL_INT_STATUS_BUSERRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_BUSERRINT_SHIFT)) & GDMA_CHNL_INT_STATUS_BUSERRINT_MASK)
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#define GDMA_CHNL_INT_MASK_ADDRERRINT_MASK (0x40U)
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#define GDMA_CHNL_INT_MASK_ADDRERRINT_SHIFT (6U)
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/*! MASK_ADDRERRINT - DMA Channel source/destination address alignment error interrupt mask bit */
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#define GDMA_CHNL_INT_MASK_ADDRERRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_ADDRERRINT_SHIFT)) & GDMA_CHNL_INT_MASK_ADDRERRINT_MASK)
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#define GDMA_CHNL_INT_STATUS_ADDRERRINT_MASK (0x80U)
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#define GDMA_CHNL_INT_STATUS_ADDRERRINT_SHIFT (7U)
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/*! STATUS_ADDRERRINT - DMA Channel source/destination address alignment error interrupt bit */
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#define GDMA_CHNL_INT_STATUS_ADDRERRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_ADDRERRINT_SHIFT)) & GDMA_CHNL_INT_STATUS_ADDRERRINT_MASK)
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#define GDMA_CHNL_INT_STATUS_CHLINT_MASK (0x100U)
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#define GDMA_CHNL_INT_STATUS_CHLINT_SHIFT (8U)
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/*! STATUS_CHLINT - DMA channel interrupt */
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#define GDMA_CHNL_INT_STATUS_CHLINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_STATUS_CHLINT_SHIFT)) & GDMA_CHNL_INT_STATUS_CHLINT_MASK)
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#define GDMA_CHNL_INT_MASK_DESC_TFRINT_MASK (0x200U)
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#define GDMA_CHNL_INT_MASK_DESC_TFRINT_SHIFT (9U)
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/*! MASK_DESC_TFRINT - descriptor transfer interrupt mask bit */
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#define GDMA_CHNL_INT_MASK_DESC_TFRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_MASK_DESC_TFRINT_SHIFT)) & GDMA_CHNL_INT_MASK_DESC_TFRINT_MASK)
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#define GDMA_CHNL_INT_DESC_STATUS_TFRINT_MASK (0x400U)
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#define GDMA_CHNL_INT_DESC_STATUS_TFRINT_SHIFT (10U)
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/*! DESC_STATUS_TFRINT - configurable descriptor transfer interrupt bit */
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#define GDMA_CHNL_INT_DESC_STATUS_TFRINT(x) (((uint32_t)(((uint32_t)(x)) << GDMA_CHNL_INT_DESC_STATUS_TFRINT_SHIFT)) & GDMA_CHNL_INT_DESC_STATUS_TFRINT_MASK)
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/*! @} */
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/* The count of GDMA_CHNL_INT */
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#define GDMA_CHNL_INT_COUNT (4U)
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/*! @name NUM_OF_DESCRIPTOR - the number of descriptor */
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/*! @{ */
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#define GDMA_NUM_OF_DESCRIPTOR_DATA_MASK (0xFFFFFFFFU)
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#define GDMA_NUM_OF_DESCRIPTOR_DATA_SHIFT (0U)
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/*! DATA - the number of descriptor */
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#define GDMA_NUM_OF_DESCRIPTOR_DATA(x) (((uint32_t)(((uint32_t)(x)) << GDMA_NUM_OF_DESCRIPTOR_DATA_SHIFT)) & GDMA_NUM_OF_DESCRIPTOR_DATA_MASK)
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/*! @} */
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/* The count of GDMA_NUM_OF_DESCRIPTOR */
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#define GDMA_NUM_OF_DESCRIPTOR_COUNT (4U)
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/*!
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* @}
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*/ /* end of group GDMA_Register_Masks */
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/*!
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* @}
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*/ /* end of group GDMA_Peripheral_Access_Layer */
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/*
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** End of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#else
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#pragma pop
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#endif
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#elif defined(__GNUC__)
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/* leave anonymous unions enabled */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=default
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#else
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#error Not supported compiler type
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#endif
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/*!
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* @}
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*/ /* end of group Peripheral_access_layer */
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#endif /* GDMA_H_ */
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