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916 lines
45 KiB
C
916 lines
45 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for I2C
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file I2C.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for I2C
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*
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* CMSIS Peripheral Access Layer for I2C
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*/
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#if !defined(I2C_H_)
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#define I2C_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- I2C Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
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* @{
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*/
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/** I2C - Size of Registers Arrays */
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#define I2C_SLVADR_COUNT 4u
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/** I2C - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[2048];
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__IO uint32_t CFG; /**< Configuration Register, offset: 0x800 */
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__IO uint32_t STAT; /**< Status Register, offset: 0x804 */
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__IO uint32_t INTENSET; /**< Interrupt Enable Set Register, offset: 0x808 */
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__O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x80C */
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__IO uint32_t TIMEOUT; /**< Time-out Register, offset: 0x810 */
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__IO uint32_t CLKDIV; /**< Clock Divider Register, offset: 0x814 */
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__I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x818 */
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uint8_t RESERVED_1[4];
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__IO uint32_t MSTCTL; /**< Master Control Register, offset: 0x820 */
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__IO uint32_t MSTTIME; /**< Master Timing Register, offset: 0x824 */
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__IO uint32_t MSTDAT; /**< Master Data Register, offset: 0x828 */
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uint8_t RESERVED_2[20];
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__IO uint32_t SLVCTL; /**< Slave Control Register, offset: 0x840 */
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__IO uint32_t SLVDAT; /**< Slave Data Register, offset: 0x844 */
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__IO uint32_t SLVADR[I2C_SLVADR_COUNT]; /**< Slave Address Register, array offset: 0x848, array step: 0x4 */
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__IO uint32_t SLVQUAL0; /**< Slave Qualification for Address 0 Register, offset: 0x858 */
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uint8_t RESERVED_3[36];
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__I uint32_t MONRXDAT; /**< Monitor Receiver Data Register, offset: 0x880 */
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uint8_t RESERVED_4[1912];
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__I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */
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} I2C_Type;
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/* ----------------------------------------------------------------------------
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-- I2C Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup I2C_Register_Masks I2C Register Masks
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* @{
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*/
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/*! @name CFG - Configuration Register */
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/*! @{ */
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#define I2C_CFG_MSTEN_MASK (0x1U)
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#define I2C_CFG_MSTEN_SHIFT (0U)
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/*! MSTEN - Master Enable
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* 0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not
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* changed, but the Master function is internally reset.
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* 0b1..Enabled. The I2C Master function is enabled.
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*/
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#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
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#define I2C_CFG_SLVEN_MASK (0x2U)
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#define I2C_CFG_SLVEN_SHIFT (1U)
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/*! SLVEN - Slave Enable
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* 0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not
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* changed, but the Slave function is internally reset.
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* 0b1..Enabled. The I2C slave function is enabled.
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*/
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#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
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#define I2C_CFG_MONEN_MASK (0x4U)
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#define I2C_CFG_MONEN_SHIFT (2U)
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/*! MONEN - Monitor Enable
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* 0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration
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* settings are not changed, but the Monitor function is internally reset.
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* 0b1..Enabled. The I2C Monitor function is enabled.
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*/
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#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
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#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
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#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
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/*! TIMEOUTEN - I2C bus Time-out Enable
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* 0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset.
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* 0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause
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* interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system.
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*/
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#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
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#define I2C_CFG_MONCLKSTR_MASK (0x10U)
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#define I2C_CFG_MONCLKSTR_SHIFT (4U)
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/*! MONCLKSTR - Monitor function Clock Stretching
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* 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
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* to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used
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* when non-invasive monitoring is critical.
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* 0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read
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* all incoming data supplied by the Monitor function.
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*/
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#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
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#define I2C_CFG_HSCAPABLE_MASK (0x20U)
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#define I2C_CFG_HSCAPABLE_SHIFT (5U)
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/*! HSCAPABLE - High Speed mode Capable enable
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* 0b0..Fast mode Plus enable
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* 0b1..High Speed mode enable
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*/
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#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
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/*! @} */
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/*! @name STAT - Status Register */
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/*! @{ */
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#define I2C_STAT_MSTPENDING_MASK (0x1U)
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#define I2C_STAT_MSTPENDING_SHIFT (0U)
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/*! MSTPENDING - Master Pending
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* 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
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* 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
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* idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit.
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*/
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#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
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#define I2C_STAT_MSTSTATE_MASK (0xEU)
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#define I2C_STAT_MSTSTATE_SHIFT (1U)
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/*! MSTSTATE - Master State code
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* 0b000..Idle. The Master function is available to be used for a new transaction.
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* 0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave.
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* 0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave.
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* 0b011..NACK Address. Slave NACKed address.
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* 0b100..NACK Data. Slave NACKed transmitted data.
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*/
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#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
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#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
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#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
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/*! MSTARBLOSS - Master Arbitration Loss flag
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* 0b0..No Arbitration Loss has occurred
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* 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
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* function has already stopped driving the bus and has gone into an idle state. Software can respond by doing
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* nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle).
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*/
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#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
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#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
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#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
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/*! MSTSTSTPERR - Master Start/Stop Error flag
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* 0b0..No Start/Stop Error has occurred.
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* 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start
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* or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and
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* gone into an idle state; no action is required. A request for a Start could be made, or software could
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* attempt to make sure that the bus has not stalled.
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*/
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#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
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#define I2C_STAT_SLVPENDING_MASK (0x100U)
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#define I2C_STAT_SLVPENDING_SHIFT (8U)
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/*! SLVPENDING - Slave Pending
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* 0b0..In progress. The Slave function does not currently need software service.
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* 0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE).
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*/
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#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
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#define I2C_STAT_SLVSTATE_MASK (0x600U)
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#define I2C_STAT_SLVSTATE_SHIFT (9U)
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/*! SLVSTATE - Slave State
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* 0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware.
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* 0b01..Slave receive. Received data is available (in Slave Receiver mode).
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* 0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode).
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* 0b11..Reserved
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*/
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#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
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#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
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#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
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/*! SLVNOTSTR - Slave Not Stretching
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* 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time.
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* 0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time.
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*/
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#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
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#define I2C_STAT_SLVIDX_MASK (0x3000U)
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#define I2C_STAT_SLVIDX_SHIFT (12U)
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/*! SLVIDX - Slave address match Index T
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* 0b00..Address 0. Slave address 0 was matched.
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* 0b01..Address 1. Slave address 1 was matched.
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* 0b10..Address 2. Slave address 2 was matched.
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* 0b11..Address 3. Slave address 3 was matched.
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*/
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#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
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#define I2C_STAT_SLVSEL_MASK (0x4000U)
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#define I2C_STAT_SLVSEL_SHIFT (14U)
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/*! SLVSEL - Slave selected flag
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* 0b0..Not selected. The Slave function is not currently selected.
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* 0b1..Selected. The Slave function is currently selected.
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*/
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#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
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#define I2C_STAT_SLVDESEL_MASK (0x8000U)
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#define I2C_STAT_SLVDESEL_SHIFT (15U)
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/*! SLVDESEL - Slave Deselected flag
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* 0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is
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* currently selected. That information is in the SLVSEL flag.
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* 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
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* changing from 1 to 0. See SLVSEL for details about when that event occurs.
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*/
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#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
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#define I2C_STAT_MONRDY_MASK (0x10000U)
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#define I2C_STAT_MONRDY_SHIFT (16U)
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/*! MONRDY - Monitor Ready
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* 0b0..No data. The Monitor function does not currently have data available.
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* 0b1..Data waiting. The Monitor function has data waiting to be read.
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*/
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#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
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#define I2C_STAT_MONOV_MASK (0x20000U)
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#define I2C_STAT_MONOV_SHIFT (17U)
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/*! MONOV - Monitor Overflow flag
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* 0b0..No overrun. Monitor data has not overrun.
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* 0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching
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* not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag.
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*/
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#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
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#define I2C_STAT_MONACTIVE_MASK (0x40000U)
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#define I2C_STAT_MONACTIVE_SHIFT (18U)
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/*! MONACTIVE - Monitor Active flag
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* 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
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* 0b1..Active. The Monitor function considers the I2C bus to be active.
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*/
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#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
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#define I2C_STAT_MONIDLE_MASK (0x80000U)
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#define I2C_STAT_MONIDLE_SHIFT (19U)
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/*! MONIDLE - Monitor Idle flag
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* 0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software.
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* 0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software.
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*/
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#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
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#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
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#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
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/*! EVENTTIMEOUT - Event Time-out Interrupt flag
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* 0b0..No time-out. I2C bus events have not caused a time-out.
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* 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
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*/
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#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
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#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
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#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
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/*! SCLTIMEOUT - SCL Time-out Interrupt flag
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* 0b0..No time-out. SCL low time has not caused a time-out.
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* 0b1..Time-out. SCL low time has caused a time-out.
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*/
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#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
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/*! @} */
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/*! @name INTENSET - Interrupt Enable Set Register */
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/*! @{ */
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#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
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#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
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/*! MSTPENDINGEN - Master Pending interrupt Enable
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* 0b0..Disabled. The MstPending interrupt is disabled.
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* 0b1..Enabled. The MstPending interrupt is enabled.
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*/
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#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
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#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
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#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
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/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable
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* 0b0..Disabled. The MstArbLoss interrupt is disabled.
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* 0b1..Enabled. The MstArbLoss interrupt is enabled.
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*/
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#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
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#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
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#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
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/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable
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* 0b0..Disabled. The MstStStpErr interrupt is disabled.
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* 0b1..Enabled. The MstStStpErr interrupt is enabled.
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*/
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#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
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#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
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#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
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/*! SLVPENDINGEN - Slave Pending interrupt Enable
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* 0b0..Disabled. The SlvPending interrupt is disabled.
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* 0b1..Enabled. The SlvPending interrupt is enabled.
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*/
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#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
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#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
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#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
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/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable
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* 0b0..Disabled. The SlvNotStr interrupt is disabled.
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* 0b1..Enabled. The SlvNotStr interrupt is enabled.
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*/
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#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
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#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
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#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
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/*! SLVDESELEN - Slave Deselect interrupt Enable
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* 0b0..Disabled. The SlvDeSel interrupt is disabled.
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* 0b1..Enabled. The SlvDeSel interrupt is enabled.
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*/
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#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
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#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
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#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
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/*! MONRDYEN - Monitor data Ready interrupt Enable
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* 0b0..Disabled. The MonRdy interrupt is disabled.
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* 0b1..Enabled. The MonRdy interrupt is enabled.
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*/
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#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
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#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
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#define I2C_INTENSET_MONOVEN_SHIFT (17U)
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/*! MONOVEN - Monitor Overrun interrupt Enable
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* 0b0..Disabled. The MonOv interrupt is disabled.
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* 0b1..Enabled. The MonOv interrupt is enabled.
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*/
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#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
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#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
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#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
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/*! MONIDLEEN - Monitor Idle interrupt Enable
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* 0b0..Disabled. The MonIdle interrupt is disabled.
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* 0b1..Enabled. The MonIdle interrupt is enabled.
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*/
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#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
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#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
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#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
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/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable
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* 0b0..Disabled. The Event time-out interrupt is disabled.
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* 0b1..Enabled. The Event time-out interrupt is enabled.
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*/
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#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
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#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
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#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
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/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable
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* 0b0..Disabled. The SCL time-out interrupt is disabled.
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* 0b1..Enabled. The SCL time-out interrupt is enabled.
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*/
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#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
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/*! @} */
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/*! @name INTENCLR - Interrupt Enable Clear Register */
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/*! @{ */
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#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
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#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
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/*! MSTPENDINGCLR - Master Pending interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
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#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
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#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
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/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
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#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
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#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
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/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
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#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
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#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
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/*! SLVPENDINGCLR - Slave Pending interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
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#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
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#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
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/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
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#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
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#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
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/*! SLVDESELCLR - Slave Deselect interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
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#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
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#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
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/*! MONRDYCLR - Monitor data Ready interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
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#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
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#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
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/*! MONOVCLR - Monitor Overrun interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
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#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
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#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
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/*! MONIDLECLR - Monitor Idle interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
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#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
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#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
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/*! EVENTTIMEOUTCLR - Event time-out interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
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#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
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#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
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/*! SCLTIMEOUTCLR - SCL time-out interrupt clear
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* 0b0..No effect on interrupt
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* 0b1..Clears the interrupt bit in INTENSET register
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*/
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#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
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/*! @} */
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/*! @name TIMEOUT - Time-out Register */
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/*! @{ */
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#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
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#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
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/*! TOMIN - Time-out time value, the bottom 4 bits */
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#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
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#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
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#define I2C_TIMEOUT_TO_SHIFT (4U)
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/*! TO - Time-out time value
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* 0b000000000000..A time-out will occur after 16 counts of the I2C function clock.
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* 0b000000000001..A time-out will occur after 32 counts of the I2C function clock.
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* 0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock.
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*/
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#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
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/*! @} */
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/*! @name CLKDIV - Clock Divider Register */
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/*! @{ */
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#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
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#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
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/*! DIVVAL - Divider Value
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* 0b0000000000000000..FCLK is used directly by the I2C.
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* 0b0000000000000001..FCLK is divided by 2 before being used by the I2C.
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* 0b0000000000000010..FCLK is divided by 3 before being used by the I2C.
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* 0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C.
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*/
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#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
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/*! @} */
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/*! @name INTSTAT - Interrupt Status Register */
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/*! @{ */
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#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
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#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
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/*! MSTPENDING - Master Pending
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
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#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
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#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
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/*! MSTARBLOSS - Master Arbitration Loss flag
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
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#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
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#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
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/*! MSTSTSTPERR - Master Start/Stop Error flag
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
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#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
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#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
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/*! SLVPENDING - Slave Pending
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
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#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
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#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
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/*! SLVNOTSTR - Slave Not Stretching status
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
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#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
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#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
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/*! SLVDESEL - Slave Deselected flag
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
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#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
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#define I2C_INTSTAT_MONRDY_SHIFT (16U)
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/*! MONRDY - Monitor Ready
|
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
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#define I2C_INTSTAT_MONOV_MASK (0x20000U)
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#define I2C_INTSTAT_MONOV_SHIFT (17U)
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/*! MONOV - Monitor Overflow flag
|
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* 0b0..Not active
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* 0b1..Active
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*/
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#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
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#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
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#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
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/*! MONIDLE - Monitor Idle flag
|
|
* 0b0..Not active
|
|
* 0b1..Active
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*/
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#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
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#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
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#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
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/*! EVENTTIMEOUT - Event Time-out Interrupt flag
|
|
* 0b0..Not active
|
|
* 0b1..Active
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|
*/
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#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
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#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
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#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
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/*! SCLTIMEOUT - SCL Time-out Interrupt flag
|
|
* 0b0..Not active
|
|
* 0b1..Active
|
|
*/
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#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
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/*! @} */
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/*! @name MSTCTL - Master Control Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
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|
#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
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/*! MSTCONTINUE - Master Continue(write-only)
|
|
* 0b0..No effect
|
|
* 0b1..Continue. Informs the Master function to continue to the next operation. This action must done after
|
|
* writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
|
|
*/
|
|
#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
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#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
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|
#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
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/*! MSTSTART - Master Start control(write-only)
|
|
* 0b0..No effect
|
|
* 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
|
|
*/
|
|
#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
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|
|
#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
|
|
#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
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|
/*! MSTSTOP - Master Stop control(write-only)
|
|
* 0b0..No effect
|
|
* 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
|
|
* if the master is receiving data from the slave (in Master Receiver mode).
|
|
*/
|
|
#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
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|
|
#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
|
|
#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
|
|
/*! MSTDMA - Master DMA enable
|
|
* 0b0..Disable. No DMA requests are generated for master operation.
|
|
* 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
|
|
* Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
|
|
*/
|
|
#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MSTTIME - Master Timing Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
|
|
#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
|
|
/*! MSTSCLLOW - Master SCL Low time
|
|
* 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
|
|
* 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
|
|
* 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
|
|
* 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
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* 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
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* 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
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* 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
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* 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
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*/
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#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
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#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
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#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
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/*! MSTSCLHIGH - Master SCL High time
|
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* 0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider.
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* 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
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* 0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider.
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* 0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider.
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* 0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider.
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* 0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider.
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* 0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider.
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* 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
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*/
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#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
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/*! @} */
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/*! @name MSTDAT - Master Data Register */
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/*! @{ */
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#define I2C_MSTDAT_DATA_MASK (0xFFU)
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#define I2C_MSTDAT_DATA_SHIFT (0U)
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/*! DATA - Master function data register */
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#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
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/*! @} */
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/*! @name SLVCTL - Slave Control Register */
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/*! @{ */
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#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
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#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
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/*! SLVCONTINUE - Slave Continue
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* 0b0..No effect
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* 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING]
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|
* flag. This must be done after writing transmit data, reading received data, or any other housekeeping
|
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* related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be
|
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* set unless SLVPENDING = 1.
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|
*/
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#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
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#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
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#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
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/*! SLVNACK - Slave NACK
|
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* 0b0..No effect
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* 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode).
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*/
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#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
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#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
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#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
|
|
/*! SLVDMA - Slave DMA enable
|
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* 0b0..Disabled. No DMA requests are issued for Slave mode operation.
|
|
* 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
|
|
*/
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|
#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
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|
|
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#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
|
|
#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
|
|
/*! AUTOACK - Automatic Acknowledge
|
|
* 0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a
|
|
* matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored).
|
|
* 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
|
|
* allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
|
|
* not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set,
|
|
* then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated.
|
|
*/
|
|
#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
|
|
|
|
#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
|
|
#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
|
|
/*! AUTOMATCHREAD - Automatic Match Read
|
|
* 0b0..In Automatic Mode, the expected next operation is an I2C write.
|
|
* 0b1..In Automatic Mode, the expected next operation is an I2C read.
|
|
*/
|
|
#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SLVDAT - Slave Data Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_SLVDAT_DATA_MASK (0xFFU)
|
|
#define I2C_SLVDAT_DATA_SHIFT (0U)
|
|
/*! DATA - Slave function data register */
|
|
#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SLVADR - Slave Address Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_SLVADR_SADISABLE_MASK (0x1U)
|
|
#define I2C_SLVADR_SADISABLE_SHIFT (0U)
|
|
/*! SADISABLE - Slave Address n Disable
|
|
* 0b0..Enabled. Slave Address n is enabled.
|
|
* 0b1..Ignored. Slave Address n is ignored.
|
|
*/
|
|
#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
|
|
|
|
#define I2C_SLVADR_SLVADR_MASK (0xFEU)
|
|
#define I2C_SLVADR_SLVADR_SHIFT (1U)
|
|
/*! SLVADR - Slave Address. */
|
|
#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
|
|
|
|
#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
|
|
#define I2C_SLVADR_AUTONACK_SHIFT (15U)
|
|
/*! AUTONACK - Automatic NACK operation
|
|
* 0b0..Normal operation, matching I2C addresses are not ignored.
|
|
* 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address
|
|
* matches SLVADRn, and AUTOMATCHREAD matches the direction.
|
|
*/
|
|
#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
|
|
#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
|
|
/*! QUALMODE0 - Qualify mode for slave address 0
|
|
* 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
|
|
* 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
|
|
*/
|
|
#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
|
|
|
|
#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
|
|
#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
|
|
/*! SLVQUAL0 - Slave address Qualifier for address 0 */
|
|
#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MONRXDAT - Monitor Receiver Data Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
|
|
#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
|
|
/*! MONRXDAT - Monitor function Receiver Data */
|
|
#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
|
|
|
|
#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
|
|
#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
|
|
/*! MONSTART - Monitor Received Start
|
|
* 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
|
|
* 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
|
|
*/
|
|
#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
|
|
|
|
#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
|
|
#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
|
|
/*! MONRESTART - Monitor Received Repeated Start
|
|
* 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
|
|
* 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
|
|
*/
|
|
#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
|
|
|
|
#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
|
|
#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
|
|
/*! MONNACK - Monitor Received NACK
|
|
* 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
|
|
* 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
|
|
*/
|
|
#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ID - Peripheral Identification Register */
|
|
/*! @{ */
|
|
|
|
#define I2C_ID_APERTURE_MASK (0xFFU)
|
|
#define I2C_ID_APERTURE_SHIFT (0U)
|
|
/*! APERTURE - Aperture */
|
|
#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
|
|
|
|
#define I2C_ID_MINOR_REV_MASK (0xF00U)
|
|
#define I2C_ID_MINOR_REV_SHIFT (8U)
|
|
/*! MINOR_REV - Minor revision of module implementation */
|
|
#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
|
|
|
|
#define I2C_ID_MAJOR_REV_MASK (0xF000U)
|
|
#define I2C_ID_MAJOR_REV_SHIFT (12U)
|
|
/*! MAJOR_REV - Major revision of module implementation */
|
|
#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
|
|
|
|
#define I2C_ID_ID_MASK (0xFFFF0000U)
|
|
#define I2C_ID_ID_SHIFT (16U)
|
|
/*! ID - Module identifier for the selected function */
|
|
#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I2C_Register_Masks */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I2C_Peripheral_Access_Layer */
|
|
|
|
|
|
/*
|
|
** End of section using anonymous unions
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang diagnostic pop
|
|
#else
|
|
#pragma pop
|
|
#endif
|
|
#elif defined(__GNUC__)
|
|
/* leave anonymous unions enabled */
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma language=default
|
|
#else
|
|
#error Not supported compiler type
|
|
#endif
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Peripheral_access_layer */
|
|
|
|
|
|
#endif /* I2C_H_ */
|
|
|