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https://github.com/cesanta/mongoose.git
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312 lines
12 KiB
C
312 lines
12 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for MRT
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file MRT.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for MRT
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*
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* CMSIS Peripheral Access Layer for MRT
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*/
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#if !defined(MRT_H_)
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#define MRT_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- MRT Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
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* @{
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*/
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/** MRT - Size of Registers Arrays */
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#define MRT_CHANNEL_COUNT 8u
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/** MRT - Register Layout Typedef */
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typedef struct {
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struct { /* offset: 0x0, array step: 0x10 */
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__IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10, irregular array, not all indices are valid */
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__I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10, irregular array, not all indices are valid */
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__IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10, irregular array, not all indices are valid */
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__IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10, irregular array, not all indices are valid */
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} CHANNEL[MRT_CHANNEL_COUNT];
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uint8_t RESERVED_0[112];
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__IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */
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__I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */
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__IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */
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__I uint32_t ID_CODE; /**< Multi-Rate Timer ID code, offset: 0xFC */
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} MRT_Type;
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/* ----------------------------------------------------------------------------
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-- MRT Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup MRT_Register_Masks MRT Register Masks
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* @{
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*/
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/*! @name CHANNEL_INTVAL - Time Interval Value */
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/*! @{ */
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#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
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#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
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/*! IVALUE - Time interval load value. */
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#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
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#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
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#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
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/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register.
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* 0b0..No force load.
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* 0b1..Force load. T
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*/
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#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
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/*! @} */
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/* The count of MRT_CHANNEL_INTVAL */
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#define MRT_CHANNEL_INTVAL_COUNT (8U)
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/*! @name CHANNEL_TIMER - Timer */
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/*! @{ */
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#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
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#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
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/*! VALUE - Holds the current timer value of the down-counter. */
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#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
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/*! @} */
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/* The count of MRT_CHANNEL_TIMER */
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#define MRT_CHANNEL_TIMER_COUNT (8U)
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/*! @name CHANNEL_CTRL - Control */
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/*! @{ */
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#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
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#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
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/*! INTEN - Enable the TIMER n interrupt.
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* 0b0..Disabled. TIMER n interrupt is disabled.
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* 0b1..Enabled. TIMER n interrupt is enabled.
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*/
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#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
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#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
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#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
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/*! MODE - Selects the timer mode
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* 0b00..Repeat interrupt mode
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* 0b01..One-shot interrupt mode
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* 0b10..One-shot stall mode
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* 0b11..Reserved
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*/
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#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
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/*! @} */
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/* The count of MRT_CHANNEL_CTRL */
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#define MRT_CHANNEL_CTRL_COUNT (8U)
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/*! @name CHANNEL_STAT - Status */
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/*! @{ */
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#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
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#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
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/*! INTFLAG - Monitors the interrupt flag
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* 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
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* 0b1..Pending interrupt.
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*/
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#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
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#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
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#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
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/*! RUN - Indicates the state of TIMER n . RUN bit is read-only.
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* 0b0..Idle state. TIMER n has stopped.
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* 0b1..Running. TIMER n is running.
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*/
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#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
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#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
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#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
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/*! INUSE - Channel-In-Use flag. Operating details depend on the operating mode bit
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* (MODCFG.MULTITASK), and affects the use of the Idle Channel register (IDLE_CH).
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* 0b0..This timer channel is not in use.
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* 0b1..This timer channel is in use.
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*/
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#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
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/*! @} */
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/* The count of MRT_CHANNEL_STAT */
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#define MRT_CHANNEL_STAT_COUNT (8U)
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/*! @name MODCFG - Module Configuration */
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/*! @{ */
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#define MRT_MODCFG_NOC_MASK (0xFU)
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#define MRT_MODCFG_NOC_SHIFT (0U)
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/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded) */
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#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
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#define MRT_MODCFG_NOB_MASK (0x1F0U)
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#define MRT_MODCFG_NOB_SHIFT (4U)
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/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device) */
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#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
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#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
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#define MRT_MODCFG_MULTITASK_SHIFT (31U)
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/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
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* 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
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* 0b1..Multi-task mode
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*/
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#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
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/*! @} */
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/*! @name IDLE_CH - Idle Channel */
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/*! @{ */
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#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
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#define MRT_IDLE_CH_CHAN_SHIFT (4U)
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/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
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* positioned so that it can be used as an offset from the MRT base address, to access the
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* registers for the allocated channel. If all timer channels are running, then CHAN = 0xF.
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*/
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#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
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/*! @} */
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/*! @name IRQ_FLAG - Global Interrupt Flag */
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/*! @{ */
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#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
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#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
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/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
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* 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
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* 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
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* the INTEN bit in the CONTROL0 register is also set to 1, then the interrupt for timer channel 0 and the
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* global interrupt are generated. Writing a 1 to GFLAG0 bit clears the interrupt request.
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*/
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#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
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#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
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#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
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/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0. */
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#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
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#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
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#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
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/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0. */
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#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
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#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
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#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
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/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0. */
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#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
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/*! @} */
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/*! @name ID_CODE - Multi-Rate Timer ID code */
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/*! @{ */
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#define MRT_ID_CODE_ID_CODE_MASK (0xFFFFFFFFU)
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#define MRT_ID_CODE_ID_CODE_SHIFT (0U)
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/*! ID_CODE - Multi-Rate Timer ID code */
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#define MRT_ID_CODE_ID_CODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group MRT_Register_Masks */
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/*!
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* @}
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*/ /* end of group MRT_Peripheral_Access_Layer */
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/*
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** End of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#else
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#pragma pop
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#endif
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#elif defined(__GNUC__)
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/* leave anonymous unions enabled */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=default
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#else
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#error Not supported compiler type
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#endif
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/*!
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* @}
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*/ /* end of group Peripheral_access_layer */
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#endif /* MRT_H_ */
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