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653 lines
39 KiB
C
653 lines
39 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for PINT
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file PINT.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for PINT
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*
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* CMSIS Peripheral Access Layer for PINT
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*/
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#if !defined(PINT_H_)
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#define PINT_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- PINT Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
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* @{
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*/
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/** PINT - Register Layout Typedef */
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typedef struct {
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__IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */
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__IO uint32_t IENR; /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */
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__O uint32_t SIENR; /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */
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__IO uint32_t CIENR; /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */
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__IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */
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__O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */
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__O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */
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__IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */
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__IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */
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__IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */
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__IO uint32_t PMCTRL; /**< Pattern Match Interrupt Control, offset: 0x28 */
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__IO uint32_t PMSRC; /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */
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__IO uint32_t PMCFG; /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */
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} PINT_Type;
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/* ----------------------------------------------------------------------------
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-- PINT Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PINT_Register_Masks PINT Register Masks
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* @{
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*/
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/*! @name ISEL - Pin Interrupt Mode */
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/*! @{ */
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#define PINT_ISEL_PMODE_MASK (0xFFU)
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#define PINT_ISEL_PMODE_SHIFT (0U)
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/*! PMODE - Interrupt mode
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* 0b00000000..Edge-sensitive
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* 0b00000001..Level-sensitive
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*/
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#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
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/*! @} */
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/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */
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/*! @{ */
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#define PINT_IENR_ENRL_MASK (0xFFU)
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#define PINT_IENR_ENRL_SHIFT (0U)
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/*! ENRL - Enable Interrupt
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* 0b00000000..Disable rising edge or level interrupt
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* 0b00000001..Enable rising edge or level interrupt
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*/
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#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
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/*! @} */
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/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */
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/*! @{ */
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#define PINT_SIENR_SETENRL_MASK (0xFFU)
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#define PINT_SIENR_SETENRL_SHIFT (0U)
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/*! SETENRL - Set bits in the IENR
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* 0b00000000..No operation
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* 0b00000001..Enable rising edge or level interrupt
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*/
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#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
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/*! @} */
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/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */
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/*! @{ */
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#define PINT_CIENR_CENRL_MASK (0xFFU)
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#define PINT_CIENR_CENRL_SHIFT (0U)
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/*! CENRL - Clear bits in the IENR
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* 0b00000000..No operation
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* 0b00000001..Disable rising edge or level interrupt
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*/
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#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
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/*! @} */
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/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */
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/*! @{ */
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#define PINT_IENF_ENAF_MASK (0xFFU)
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#define PINT_IENF_ENAF_SHIFT (0U)
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/*! ENAF - Enable Interrupt
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* 0b00000000..Disable falling edge interrupt or set active interrupt level LOW
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* 0b00000001..Enable falling edge interrupt enabled or set active interrupt level HIGH
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*/
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#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
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/*! @} */
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/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */
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/*! @{ */
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#define PINT_SIENF_SETENAF_MASK (0xFFU)
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#define PINT_SIENF_SETENAF_SHIFT (0U)
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/*! SETENAF - Set bits in the IENF
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* 0b00000000..No operation
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* 0b00000001..Select HIGH-active interrupt or enable falling edge interrupt
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*/
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#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
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/*! @} */
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/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */
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/*! @{ */
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#define PINT_CIENF_CENAF_MASK (0xFFU)
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#define PINT_CIENF_CENAF_SHIFT (0U)
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/*! CENAF - Clear bits in the IENF
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* 0b00000000..No operation
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* 0b00000001..LOW-active interrupt selected or falling edge interrupt disabled
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*/
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#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
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/*! @} */
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/*! @name RISE - Pin Interrupt Rising Edge */
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/*! @{ */
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#define PINT_RISE_RDET_MASK (0xFFU)
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#define PINT_RISE_RDET_SHIFT (0U)
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/*! RDET - Rising edge detect
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* 0b00000000..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
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* 0b00000001..Read 1- a rising edge has been detected since Reset or the last time a one was written to this
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* bit, Write 1- clear rising edge detection for this pin
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*/
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#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
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/*! @} */
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/*! @name FALL - Pin Interrupt Falling Edge */
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/*! @{ */
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#define PINT_FALL_FDET_MASK (0xFFU)
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#define PINT_FALL_FDET_SHIFT (0U)
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/*! FDET - Falling edge detect
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* 0b00000000..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
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* 0b00000001..Read 1- a falling edge has been detected since Reset or the last time a one was written to this
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* bit, Write 1- clear falling edge detection for this bit
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*/
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#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
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/*! @} */
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/*! @name IST - Pin Interrupt Status */
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/*! @{ */
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#define PINT_IST_PSTAT_MASK (0xFFU)
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#define PINT_IST_PSTAT_SHIFT (0U)
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/*! PSTAT - Pin interrupt status
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* 0b00000000..Read 0- interrupt is not being requested for this pin, Write 0- no operation.
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* 0b00000001..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and
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* falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin
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* (in the IENF register).
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*/
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#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
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/*! @} */
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/*! @name PMCTRL - Pattern Match Interrupt Control */
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/*! @{ */
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#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
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#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
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/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function.
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* 0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function.
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* 0b1..Pattern match- interrupts are driven in response to pattern matches.
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*/
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#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
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#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
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#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
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/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true.
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* 0b0..Disabled- RXEV output to the CPU is disabled.
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* 0b1..Enabled- RXEV output to the CPU is enabled.
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*/
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#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
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#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
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#define PINT_PMCTRL_PMAT_SHIFT (24U)
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/*! PMAT - Pattern Matches
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* 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs.
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*/
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#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
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/*! @} */
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/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */
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/*! @{ */
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#define PINT_PMSRC_SRC0_MASK (0x700U)
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#define PINT_PMSRC_SRC0_SHIFT (8U)
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/*! SRC0 - Selects the input source for bit slice 0
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
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#define PINT_PMSRC_SRC1_MASK (0x3800U)
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#define PINT_PMSRC_SRC1_SHIFT (11U)
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/*! SRC1 - Selects the input source for bit slice 1
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
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#define PINT_PMSRC_SRC2_MASK (0x1C000U)
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#define PINT_PMSRC_SRC2_SHIFT (14U)
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/*! SRC2 - Selects the input source for bit slice 2
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
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#define PINT_PMSRC_SRC3_MASK (0xE0000U)
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#define PINT_PMSRC_SRC3_SHIFT (17U)
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/*! SRC3 - Selects the input source for bit slice 3
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
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#define PINT_PMSRC_SRC4_MASK (0x700000U)
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#define PINT_PMSRC_SRC4_SHIFT (20U)
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/*! SRC4 - Selects the input source for bit slice 4
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
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#define PINT_PMSRC_SRC5_MASK (0x3800000U)
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#define PINT_PMSRC_SRC5_SHIFT (23U)
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/*! SRC5 - Selects the input source for bit slice 5
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
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#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
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#define PINT_PMSRC_SRC6_SHIFT (26U)
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/*! SRC6 - Selects the input source for bit slice 6
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* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
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* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
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* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
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* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
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* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
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* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
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* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
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* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
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*/
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#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
|
|
|
|
#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
|
|
#define PINT_PMSRC_SRC7_SHIFT (29U)
|
|
/*! SRC7 - Selects the input source for bit slice 7
|
|
* 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
|
|
* 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
|
|
* 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
|
|
* 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
|
|
* 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
|
|
* 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
|
|
* 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
|
|
* 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
|
|
*/
|
|
#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */
|
|
/*! @{ */
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
|
|
#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
|
|
/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
|
|
* 0b0..No effect. Slice 0 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
|
|
#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
|
|
/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
|
|
* 0b0..No effect. Slice 1 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
|
|
#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
|
|
/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
|
|
* 0b0..No effect. Slice 2 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
|
|
#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
|
|
/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
|
|
* 0b0..No effect. Slice 3 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
|
|
#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
|
|
/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
|
|
* 0b0..No effect. Slice 4 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
|
|
#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
|
|
/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
|
|
* 0b0..No effect. Slice 5 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
|
|
|
|
#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
|
|
#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
|
|
/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
|
|
* 0b0..No effect. Slice 6 is not an endpoint.
|
|
* 0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
|
|
*/
|
|
#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
|
|
|
|
#define PINT_PMCFG_CFG0_MASK (0x700U)
|
|
#define PINT_PMCFG_CFG0_SHIFT (8U)
|
|
/*! CFG0 - Specifies the match contribution condition for bit slice 0.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
|
|
|
|
#define PINT_PMCFG_CFG1_MASK (0x3800U)
|
|
#define PINT_PMCFG_CFG1_SHIFT (11U)
|
|
/*! CFG1 - Specifies the match contribution condition for bit slice 1.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
|
|
|
|
#define PINT_PMCFG_CFG2_MASK (0x1C000U)
|
|
#define PINT_PMCFG_CFG2_SHIFT (14U)
|
|
/*! CFG2 - Specifies the match contribution condition for bit slice 2.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
|
|
|
|
#define PINT_PMCFG_CFG3_MASK (0xE0000U)
|
|
#define PINT_PMCFG_CFG3_SHIFT (17U)
|
|
/*! CFG3 - Specifies the match contribution condition for bit slice 3.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
|
|
|
|
#define PINT_PMCFG_CFG4_MASK (0x700000U)
|
|
#define PINT_PMCFG_CFG4_SHIFT (20U)
|
|
/*! CFG4 - Specifies the match contribution condition for bit slice 4.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
|
|
|
|
#define PINT_PMCFG_CFG5_MASK (0x3800000U)
|
|
#define PINT_PMCFG_CFG5_SHIFT (23U)
|
|
/*! CFG5 - Specifies the match contribution condition for bit slice 5.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
|
|
|
|
#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
|
|
#define PINT_PMCFG_CFG6_SHIFT (26U)
|
|
/*! CFG6 - Specifies the match contribution condition for bit slice 6.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
|
|
|
|
#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
|
|
#define PINT_PMCFG_CFG7_SHIFT (29U)
|
|
/*! CFG7 - Specifies the match contribution condition for bit slice 7.
|
|
* 0b000..Constant HIGH
|
|
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
|
|
* time the edge detection for this bit slice was cleared. This match condition is only cleared when the
|
|
* PMCFG or the PMSRC registers are written to.
|
|
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
|
|
* has occurred since the last time the edge detection for this bit slice was cleared. This match condition
|
|
* is only cleared when the PMCFG or the PMSRC registers are written to.
|
|
* 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
|
|
* 0b101..Low level. Match occurs when there is a low level on the specified input.
|
|
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
|
|
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
|
|
* is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
|
|
* cleared after 1 clock cycle.
|
|
*/
|
|
#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PINT_Register_Masks */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PINT_Peripheral_Access_Layer */
|
|
|
|
|
|
/*
|
|
** End of section using anonymous unions
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang diagnostic pop
|
|
#else
|
|
#pragma pop
|
|
#endif
|
|
#elif defined(__GNUC__)
|
|
/* leave anonymous unions enabled */
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma language=default
|
|
#else
|
|
#error Not supported compiler type
|
|
#endif
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Peripheral_access_layer */
|
|
|
|
|
|
#endif /* PINT_H_ */
|
|
|