mirror of
https://github.com/cesanta/mongoose.git
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233 lines
9.8 KiB
C
233 lines
9.8 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for RF_SYSCON
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file RF_SYSCON.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for RF_SYSCON
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*
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* CMSIS Peripheral Access Layer for RF_SYSCON
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*/
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#if !defined(RF_SYSCON_H_)
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#define RF_SYSCON_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- RF_SYSCON Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup RF_SYSCON_Peripheral_Access_Layer RF_SYSCON Peripheral Access Layer
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* @{
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*/
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/** RF_SYSCON - Size of Registers Arrays */
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#define RF_SYSCON_WO_SCRATCH_REG_COUNT 8u
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#define RF_SYSCON_RW_SCRATCH_REG_COUNT 8u
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/** RF_SYSCON - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[1024];
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__I uint32_t WO_SCRATCH_REG[RF_SYSCON_WO_SCRATCH_REG_COUNT]; /**< Write once scratch register 0..Write once scratch register 7, array offset: 0x400, array step: 0x4 */
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uint8_t RESERVED_1[96];
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__IO uint32_t RW_SCRATCH_REG[RF_SYSCON_RW_SCRATCH_REG_COUNT]; /**< Scratch register 0..Scratch register 7, array offset: 0x480, array step: 0x4 */
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} RF_SYSCON_Type;
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/* ----------------------------------------------------------------------------
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-- RF_SYSCON Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup RF_SYSCON_Register_Masks RF_SYSCON Register Masks
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* @{
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*/
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/*! @name WO_SCRATCH_REG - Write once scratch register 0..Write once scratch register 7 */
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/*! @{ */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_SHIFT (0U)
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/*! WO_SCRATCH_REG0 - Write once scratch register 0 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG0_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_SHIFT (0U)
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/*! WO_SCRATCH_REG1 - Write once scratch register 1 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG1_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_SHIFT (0U)
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/*! WO_SCRATCH_REG2 - Write once scratch register 2 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG2_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_SHIFT (0U)
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/*! WO_SCRATCH_REG3 - Write once scratch register 3 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG3_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_SHIFT (0U)
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/*! WO_SCRATCH_REG4 - Write once scratch register 4 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG4_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_SHIFT (0U)
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/*! WO_SCRATCH_REG5 - Write once scratch register 5 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG5_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_SHIFT (0U)
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/*! WO_SCRATCH_REG6 - Write once scratch register 6 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG6_MASK)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_SHIFT (0U)
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/*! WO_SCRATCH_REG7 - Write once scratch register 7 */
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#define RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_SHIFT)) & RF_SYSCON_WO_SCRATCH_REG_WO_SCRATCH_REG7_MASK)
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/*! @} */
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/*! @name RW_SCRATCH_REG - Scratch register 0..Scratch register 7 */
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/*! @{ */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_SHIFT (0U)
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/*! RW_SCRATCH_REG0 - Scratch register 0 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG0_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_SHIFT (0U)
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/*! RW_SCRATCH_REG1 - Scratch register 1 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG1_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_SHIFT (0U)
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/*! RW_SCRATCH_REG2 - Scratch register 2 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG2_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_SHIFT (0U)
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/*! RW_SCRATCH_REG3 - Scratch register 3 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG3_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_SHIFT (0U)
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/*! RW_SCRATCH_REG4 - Scratch register 4 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG4_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_SHIFT (0U)
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/*! RW_SCRATCH_REG5 - Scratch register 5 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG5_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_SHIFT (0U)
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/*! RW_SCRATCH_REG6 - Scratch register 6 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG6_MASK)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_MASK (0xFFFFFFFFU)
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_SHIFT (0U)
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/*! RW_SCRATCH_REG7 - Scratch register 7 */
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#define RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7(x) (((uint32_t)(((uint32_t)(x)) << RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_SHIFT)) & RF_SYSCON_RW_SCRATCH_REG_RW_SCRATCH_REG7_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group RF_SYSCON_Register_Masks */
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/*!
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* @}
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*/ /* end of group RF_SYSCON_Peripheral_Access_Layer */
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/*
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** End of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#else
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#pragma pop
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#endif
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#elif defined(__GNUC__)
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/* leave anonymous unions enabled */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=default
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#else
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#error Not supported compiler type
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#endif
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/*!
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* @}
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*/ /* end of group Peripheral_access_layer */
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#endif /* RF_SYSCON_H_ */
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