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2942 lines
183 KiB
C
2942 lines
183 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for SYSCTL2
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file SYSCTL2.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for SYSCTL2
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*
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* CMSIS Peripheral Access Layer for SYSCTL2
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*/
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#if !defined(SYSCTL2_H_)
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#define SYSCTL2_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- SYSCTL2 Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SYSCTL2_Peripheral_Access_Layer SYSCTL2 Peripheral Access Layer
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* @{
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*/
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/** SYSCTL2 - Register Layout Typedef */
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typedef struct {
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__IO uint32_t RAM_CTRL0; /**< RAM Memory Control Register 0, offset: 0x0 */
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__IO uint32_t USB_CTRL; /**< USB Control Register, offset: 0x4 */
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__IO uint32_t ANA_GRP_CTRL; /**< ANA GRP control register, offset: 0x8 */
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__IO uint32_t AVPLL_CTRL0; /**< Audio PLL Control register0, offset: 0xC */
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__IO uint32_t AVPLL_CTRL1; /**< Audio PLL Control register1, offset: 0x10 */
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__IO uint32_t AVPLL_CTRL2; /**< Audio PLL Control register2, offset: 0x14 */
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__IO uint32_t AVPLL_CTRL3; /**< Audio PLL Control register3, offset: 0x18 */
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__IO uint32_t AVPLL_CTRL4; /**< Audio PLL Control register4, offset: 0x1C */
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__IO uint32_t AVPLL_CTRL5; /**< Audio PLL Control register5, offset: 0x20 */
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__IO uint32_t AVPLL_CTRL6; /**< Audio PLL Control register6, offset: 0x24 */
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__I uint32_t AVPLL_CTRL7; /**< Audio PLL Control register7, offset: 0x28 */
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__IO uint32_t AVPLL_CTRL8; /**< Audio PLL Control register8, offset: 0x2C */
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__IO uint32_t AVPLL_CTRL9; /**< Audio PLL Control register9, offset: 0x30 */
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__IO uint32_t AVPLL_CTRL10; /**< Audio PLL Control register10, offset: 0x34 */
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__IO uint32_t AVPLL_CTRL11; /**< Audio PLL Control register11, offset: 0x38 */
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__IO uint32_t AVPLL_CTRL12; /**< Audio PLL Control register12, offset: 0x3C */
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__IO uint32_t GAU_CTRL; /**< GAU Control register, offset: 0x40 */
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__IO uint32_t CTIMER_CTRL; /**< CTIMER Control register, offset: 0x44 */
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__IO uint32_t EXT_H2H_CTRL; /**< AHB async bridge Control register, offset: 0x48 */
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__IO uint32_t RAM_CTRL1; /**< RAM Memory Control Register 1, offset: 0x4C */
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__IO uint32_t ROM_CTRL; /**< ROM Control Register, offset: 0x50 */
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__IO uint32_t MEM_PD_CTRL; /**< MEM PD Control enable register when PM2 mode, offset: 0x54 */
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__IO uint32_t MEM_PD_CFG; /**< MEM PD Configure register when PM2 mode, offset: 0x58 */
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__IO uint32_t ENET_IN_SEL_TIMER; /**< Select input source for enet pad0, offset: 0x5C */
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__IO uint32_t ENET_IPG_STOP; /**< Configure ipg_stop, used by enet wakeup sequence, offset: 0x60 */
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__I uint32_t ENET_IPG_STOP_ACK; /**< Store ipg_stop_ack, used by enet wakeup sequence, offset: 0x64 */
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__IO uint32_t ROM_BRU_ADDR_MASK_DIS; /**< Disable dynamic address masking feature, offset: 0x68 */
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__IO uint32_t ROM_BRU_DYN_CLK_DIS; /**< Disable dynamic clock gating feature, offset: 0x6C */
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uint8_t RESERVED_0[12];
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__I uint32_t OTP_EARLY_FUSE_VALID; /**< Early fuse valid from OTP, offset: 0x7C */
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__I uint32_t OTP_MEDIUM_FUSE_VALID; /**< Medium fuse valid from OTP, offset: 0x80 */
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__I uint32_t OTP_ALL_FUSE_VALID; /**< All fuse valid from OTP, offset: 0x84 */
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__IO uint32_t PLL_CTRL; /**< PLL control register, offset: 0x88 */
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__IO uint32_t ANA_PDWN_PM2; /**< ana_pdwn control signal when PM2 mode, offset: 0x8C */
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__IO uint32_t SOURCE_CLK_GATE; /**< source clock gate control, offset: 0x90 */
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__IO uint32_t TRNG_PWR_MODE; /**< TRNG_PWR_MODE, offset: 0x94 */
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__IO uint32_t TRNG_PIN_CTRL; /**< TRNG_PIN_CTRL, offset: 0x98 */
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__IO uint32_t CAU_CTRL; /**< CAU control register, offset: 0x9C */
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__IO uint32_t SOC_CIU_RDY_MASK; /**< SOC_CIU_RDY_MASK, offset: 0xA0 */
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__IO uint32_t LE_AUDIO_TIMER_ENABLE; /**< Enable bit for le audio timer, offset: 0xA4 */
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__IO uint32_t LE_AUDIO_TIMER_CNT_CLR; /**< Clear bit of internal counter, offset: 0xA8 */
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__I uint32_t LE_AUDIO_TIMER_CNT0; /**< Counter value captured by trigger0, offset: 0xAC */
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__I uint32_t LE_AUDIO_TIMER_CNT1; /**< Counter value captured by trigger1, offset: 0xB0 */
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__I uint32_t LE_AUDIO_TIMER_CNT2; /**< Counter value captured by trigger2, offset: 0xB4 */
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uint8_t RESERVED_1[8];
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__IO uint32_t AVPLL_CTRL13; /**< Audio PLL Control register13, offset: 0xC0 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_STATUS; /**< CPU Code Bus Access Sram Checker Violation Status, offset: 0xC4 */
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__IO uint32_t MEM_ACC_CHK_CODE_VIO_CLR; /**< CPU Code Bus Access Sram Checker Violation Status Clear, offset: 0xC8 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_STATUS; /**< CPU SYS Bus Access Sram Checker Violation Status, offset: 0xCC */
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__IO uint32_t MEM_ACC_CHK_SYS_VIO_CLR; /**< CPU SYS Bus Access Sram Checker Violation Status Clear, offset: 0xD0 */
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uint8_t RESERVED_2[4];
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__I uint32_t SOC_MCI_EXTRA; /**< Reserved register, offset: 0xD8 */
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__IO uint32_t MCI_SOC_EXTRA; /**< Reserved register, offset: 0xDC */
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__IO uint32_t ROM_DYN_CLK_EN; /**< To control dynamic clock gating of the rom clock, offset: 0xE0 */
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__IO uint32_t RESERVED_REG1; /**< Reserved register, offset: 0xE4 */
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__IO uint32_t RESERVED_REG2; /**< Reserved register, offset: 0xE8 */
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__IO uint32_t RESERVED_REG3; /**< Reserved register, offset: 0xEC */
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__IO uint32_t RESERVED_REG4; /**< Reserved register, offset: 0xF0 */
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__IO uint32_t RESERVED_REG5; /**< Reserved register, offset: 0xF4 */
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__IO uint32_t RESERVED_REG6; /**< Reserved register, offset: 0xF8 */
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__IO uint32_t RESERVED_REG7; /**< Reserved register, offset: 0xFC */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR0; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x100 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC0; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x104 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR1; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x108 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC1; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x10C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR2; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x110 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC2; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x114 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR3; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x118 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC3; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x11C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR4; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x120 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC4; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x124 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR5; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x128 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC5; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x12C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR6; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x130 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC6; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x134 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR7; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x138 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC7; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x13C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR8; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x140 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC8; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x144 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR9; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x148 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC9; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x14C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR10; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x150 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC10; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x154 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR11; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x158 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC11; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x15C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR12; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x160 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC12; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x164 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR13; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x168 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC13; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x16C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR14; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x170 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC14; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x174 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR15; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x178 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC15; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x17C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR16; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x180 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC16; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x184 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR17; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x188 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC17; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x18C */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_ADDR18; /**< CPU CODE Bus Access Sram Checker: Address of Violated Transfer, offset: 0x190 */
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__I uint32_t MEM_ACC_CHK_CODE_VIO_MISC18; /**< CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer, offset: 0x194 */
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uint8_t RESERVED_3[104];
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR0; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x200 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC0; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x204 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR1; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x208 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC1; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x20C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR2; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x210 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC2; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x214 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR3; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x218 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC3; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x21C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR4; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x220 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC4; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x224 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR5; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x228 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC5; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x22C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR6; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x230 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC6; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x234 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR7; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x238 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC7; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x23C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR8; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x240 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC8; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x244 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR9; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x248 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC9; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x24C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR10; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x250 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC10; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x254 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR11; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x258 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC11; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x25C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR12; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x260 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC12; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x264 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR13; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x268 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC13; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x26C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR14; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x270 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC14; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x274 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR15; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x278 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC15; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x27C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR16; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x280 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC16; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x284 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR17; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x288 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC17; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x28C */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_ADDR18; /**< CPU SYS Bus Access Sram Checker: Address of Violated Transfer, offset: 0x290 */
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__I uint32_t MEM_ACC_CHK_SYS_VIO_MISC18; /**< CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer, offset: 0x294 */
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} SYSCTL2_Type;
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/* ----------------------------------------------------------------------------
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-- SYSCTL2 Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SYSCTL2_Register_Masks SYSCTL2 Register Masks
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* @{
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*/
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/*! @name RAM_CTRL0 - RAM Memory Control Register 0 */
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/*! @{ */
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#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_MASK (0x3U)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_SHIFT (0U)
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/*! AON_MEM_RTC1 - aon_mem_rtc1 */
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#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_RTC1_MASK)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_MASK (0xCU)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_SHIFT (2U)
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/*! AON_MEM_WTC1 - aon_mem_wtc1 */
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#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_WTC1_MASK)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_MASK (0x30U)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_SHIFT (4U)
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/*! AON_MEM_RTC0 - aon_mem_rtc0 */
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#define SYSCTL2_RAM_CTRL0_AON_MEM_RTC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_RTC0_MASK)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_MASK (0xC0U)
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#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_SHIFT (6U)
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/*! AON_MEM_WTC0 - aon_mem_wtc0 */
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#define SYSCTL2_RAM_CTRL0_AON_MEM_WTC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_SHIFT)) & SYSCTL2_RAM_CTRL0_AON_MEM_WTC0_MASK)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_MASK (0x300U)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_SHIFT (8U)
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/*! FLEXSPI_MEM_RTC - flexspi_mem_rtc */
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_RTC_MASK)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_MASK (0xC00U)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_SHIFT (10U)
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/*! FLEXSPI_MEM_WTC - flexspi_mem_wtc */
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_MEM_WTC_MASK)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_MASK (0x3000U)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_SHIFT (12U)
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/*! FLEXSPI_CACHE_RTC - flexspi_cache_rtc */
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_RTC_MASK)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_MASK (0xC000U)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_SHIFT (14U)
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/*! FLEXSPI_CACHE_WTC - flexspi_cache_wtc */
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_WTC_MASK)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_MASK (0x30000U)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_SHIFT (16U)
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/*! FLEXSPI_CACHE_TAG_RTC - flexspi_cache_tag_rtc */
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_RTC_MASK)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_MASK (0xC0000U)
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_SHIFT (18U)
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/*! FLEXSPI_CACHE_TAG_WTC - flexspi_cache_tag_wtc */
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#define SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_SHIFT)) & SYSCTL2_RAM_CTRL0_FLEXSPI_CACHE_TAG_WTC_MASK)
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/*! @} */
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/*! @name USB_CTRL - USB Control Register */
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/*! @{ */
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#define SYSCTL2_USB_CTRL_USB_PU_PLL_MASK (0x1U)
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#define SYSCTL2_USB_CTRL_USB_PU_PLL_SHIFT (0U)
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/*! USB_PU_PLL - USB PU PLL */
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#define SYSCTL2_USB_CTRL_USB_PU_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_PU_PLL_SHIFT)) & SYSCTL2_USB_CTRL_USB_PU_PLL_MASK)
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#define SYSCTL2_USB_CTRL_USB_PU_OTG_MASK (0x2U)
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#define SYSCTL2_USB_CTRL_USB_PU_OTG_SHIFT (1U)
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/*! USB_PU_OTG - USB PU OTG */
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#define SYSCTL2_USB_CTRL_USB_PU_OTG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_PU_OTG_SHIFT)) & SYSCTL2_USB_CTRL_USB_PU_OTG_MASK)
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#define SYSCTL2_USB_CTRL_USB_PU_MASK (0x4U)
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#define SYSCTL2_USB_CTRL_USB_PU_SHIFT (2U)
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/*! USB_PU - USB PU */
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#define SYSCTL2_USB_CTRL_USB_PU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_PU_SHIFT)) & SYSCTL2_USB_CTRL_USB_PU_MASK)
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#define SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_MASK (0x8U)
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#define SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_SHIFT (3U)
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/*! REG_RX_PDFVSSM - reg_rx_pdfvssm */
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#define SYSCTL2_USB_CTRL_REG_RX_PDFVSSM(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_PDFVSSM_MASK)
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#define SYSCTL2_USB_CTRL_REG_RX_PDLVMC_MASK (0x10U)
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#define SYSCTL2_USB_CTRL_REG_RX_PDLVMC_SHIFT (4U)
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/*! REG_RX_PDLVMC - reg_rx_pdlvmc */
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#define SYSCTL2_USB_CTRL_REG_RX_PDLVMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_PDLVMC_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_PDLVMC_MASK)
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#define SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_MASK (0x20U)
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#define SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_SHIFT (5U)
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/*! REG_TX_PDFVSSM - reg_tx_pdfvssm */
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#define SYSCTL2_USB_CTRL_REG_TX_PDFVSSM(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_PDFVSSM_MASK)
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#define SYSCTL2_USB_CTRL_REG_TX_PDLVMC_MASK (0x40U)
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#define SYSCTL2_USB_CTRL_REG_TX_PDLVMC_SHIFT (6U)
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/*! REG_TX_PDLVMC - reg_tx_pdlvmc */
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#define SYSCTL2_USB_CTRL_REG_TX_PDLVMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_PDLVMC_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_PDLVMC_MASK)
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#define SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_MASK (0x180U)
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#define SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_SHIFT (7U)
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/*! REG_RX_BUF_RTC - reg_rx_buf_rtc */
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#define SYSCTL2_USB_CTRL_REG_RX_BUF_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_BUF_RTC_MASK)
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#define SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_MASK (0x600U)
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#define SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_SHIFT (9U)
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/*! REG_RX_BUF_WTC - reg_rx_buf_wtc */
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#define SYSCTL2_USB_CTRL_REG_RX_BUF_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_RX_BUF_WTC_MASK)
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#define SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_MASK (0x1800U)
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#define SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_SHIFT (11U)
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/*! REG_TX_BUF_RTC - reg_tx_buf_rtc */
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#define SYSCTL2_USB_CTRL_REG_TX_BUF_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_BUF_RTC_MASK)
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#define SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_MASK (0x6000U)
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#define SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_SHIFT (13U)
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/*! REG_TX_BUF_WTC - reg_tx_buf_wtc */
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#define SYSCTL2_USB_CTRL_REG_TX_BUF_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_SHIFT)) & SYSCTL2_USB_CTRL_REG_TX_BUF_WTC_MASK)
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#define SYSCTL2_USB_CTRL_USB_RESUME_MASK (0x8000U)
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#define SYSCTL2_USB_CTRL_USB_RESUME_SHIFT (15U)
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/*! USB_RESUME - USB Resume */
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#define SYSCTL2_USB_CTRL_USB_RESUME(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_RESUME_SHIFT)) & SYSCTL2_USB_CTRL_USB_RESUME_MASK)
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#define SYSCTL2_USB_CTRL_IDDQ_TEST_MASK (0x10000U)
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#define SYSCTL2_USB_CTRL_IDDQ_TEST_SHIFT (16U)
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/*! IDDQ_TEST - iddq Test */
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#define SYSCTL2_USB_CTRL_IDDQ_TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_IDDQ_TEST_SHIFT)) & SYSCTL2_USB_CTRL_IDDQ_TEST_MASK)
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#define SYSCTL2_USB_CTRL_SOFT_PHY_RESET_MASK (0x20000U)
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#define SYSCTL2_USB_CTRL_SOFT_PHY_RESET_SHIFT (17U)
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/*! SOFT_PHY_RESET - Soft PHY Reset */
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#define SYSCTL2_USB_CTRL_SOFT_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_PHY_RESET_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_PHY_RESET_MASK)
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#define SYSCTL2_USB_CTRL_PHY_RESET_SEL_MASK (0x40000U)
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#define SYSCTL2_USB_CTRL_PHY_RESET_SEL_SHIFT (18U)
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/*! PHY_RESET_SEL - PHY Reset Select */
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#define SYSCTL2_USB_CTRL_PHY_RESET_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_PHY_RESET_SEL_SHIFT)) & SYSCTL2_USB_CTRL_PHY_RESET_SEL_MASK)
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_MASK (0x80000U)
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_SHIFT (19U)
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/*! SOFT_UTMI_SESSEND - Soft UTMI sessend */
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_UTMI_SESSEND_MASK)
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_MASK (0x100000U)
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_SHIFT (20U)
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/*! SOFT_UTMI_XVALID - Soft UTMI xvalid */
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_UTMI_XVALID_MASK)
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_MASK (0x200000U)
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_SHIFT (21U)
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/*! SOFT_UTMI_IDDIG - Soft UTMI iddig */
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#define SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_SHIFT)) & SYSCTL2_USB_CTRL_SOFT_UTMI_IDDIG_MASK)
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#define SYSCTL2_USB_CTRL_MAC_CTRL_SEL_MASK (0x400000U)
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#define SYSCTL2_USB_CTRL_MAC_CTRL_SEL_SHIFT (22U)
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/*! MAC_CTRL_SEL - MAC Control Select */
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#define SYSCTL2_USB_CTRL_MAC_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_MAC_CTRL_SEL_SHIFT)) & SYSCTL2_USB_CTRL_MAC_CTRL_SEL_MASK)
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#define SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_MASK (0x800000U)
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#define SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_SHIFT (23U)
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/*! USB_TX_BITSTUFF_EN - USM TX BITSTUFF EN */
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#define SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_SHIFT)) & SYSCTL2_USB_CTRL_USB_TX_BITSTUFF_EN_MASK)
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/*! @} */
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/*! @name ANA_GRP_CTRL - ANA GRP control register */
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/*! @{ */
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#define SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_MASK (0x3U)
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#define SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_SHIFT (0U)
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/*! ICC_ADJ - ICC_ADJ Current Select */
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#define SYSCTL2_ANA_GRP_CTRL_ICC_ADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_ICC_ADJ_MASK)
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#define SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_MASK (0xCU)
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#define SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_SHIFT (2U)
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/*! IPP_ADJ - IPP_ADJ Current Select */
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#define SYSCTL2_ANA_GRP_CTRL_IPP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_IPP_ADJ_MASK)
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#define SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_MASK (0x20U)
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#define SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_SHIFT (5U)
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/*! AVDD1815_SEL - AVDD Select */
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#define SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_AVDD1815_SEL_MASK)
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#define SYSCTL2_ANA_GRP_CTRL_TEST_ANA_MASK (0x3C0U)
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#define SYSCTL2_ANA_GRP_CTRL_TEST_ANA_SHIFT (6U)
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/*! TEST_ANA - TEST ANA */
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#define SYSCTL2_ANA_GRP_CTRL_TEST_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_TEST_ANA_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_TEST_ANA_MASK)
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#define SYSCTL2_ANA_GRP_CTRL_PU_XTL_MASK (0x400U)
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#define SYSCTL2_ANA_GRP_CTRL_PU_XTL_SHIFT (10U)
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/*! PU_XTL - PU_XTL power up . Provide the reference voltage , USB need it */
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#define SYSCTL2_ANA_GRP_CTRL_PU_XTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_PU_XTL_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_PU_XTL_MASK)
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#define SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK (0x1000U)
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#define SYSCTL2_ANA_GRP_CTRL_PU_AG_SHIFT (12U)
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/*! PU_AG - Analog Group Power Up.Provide the reference current , AVPLL and USB need it */
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#define SYSCTL2_ANA_GRP_CTRL_PU_AG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_GRP_CTRL_PU_AG_SHIFT)) & SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL0 - Audio PLL Control register0 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_MASK (0x1U)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_SHIFT (0U)
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/*! EXT_SPEED_EN - EXT_SPEED Enable */
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#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SPEED_EN_MASK)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_MASK (0x1EU)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED_SHIFT (1U)
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/*! EXT_SPEED - External VCO Speed Control for Different VCO Frequencies. */
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#define SYSCTL2_AVPLL_CTRL0_EXT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SPEED_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SPEED_MASK)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_MASK (0x20U)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_SHIFT (5U)
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/*! EXT_SP_FBRES_EN - External Speed Enable Pin. */
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#define SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SP_FBRES_EN_MASK)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_MASK (0x40U)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_SHIFT (6U)
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/*! EXT_SLLP_DAC_EN - EXT_SLLP_DAC Enable */
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#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_EN_MASK)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_MASK (0x3F80U)
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#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_SHIFT (7U)
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/*! EXT_SLLP_DAC - VCON Reference Value Set */
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#define SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EXT_SLLP_DAC_MASK)
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#define SYSCTL2_AVPLL_CTRL0_EN_LP_C1_MASK (0xC000U)
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#define SYSCTL2_AVPLL_CTRL0_EN_LP_C1_SHIFT (14U)
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/*! EN_LP_C1 - Channel CX LP Enable. */
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#define SYSCTL2_AVPLL_CTRL0_EN_LP_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EN_LP_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EN_LP_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_MASK (0x10000U)
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#define SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_SHIFT (16U)
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/*! EN_DPLL_C1 - Enable/ Disable Channel CX¡¯s DPLL */
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#define SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL0_EN_DPLL_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_MASK (0x60000U)
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#define SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_SHIFT (17U)
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/*! DPHER_DLY_SEL - DPHERCK Delay Tune */
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#define SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL0_DPHER_DLY_SEL_MASK)
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#define SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_MASK (0x80000U)
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#define SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_SHIFT (19U)
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/*! CLKOUT_TST_EN - Clock Out Test Output Enable */
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#define SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_CLKOUT_TST_EN_MASK)
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#define SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_MASK (0x100000U)
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#define SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_SHIFT (20U)
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/*! CLK_DET_EN - PI Output Clock Enable for Internal Reset Circuit */
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#define SYSCTL2_AVPLL_CTRL0_CLK_DET_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL0_CLK_DET_EN_MASK)
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#define SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_MASK (0x3FE00000U)
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#define SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_SHIFT (21U)
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/*! CAL_FBDIV - FBDIV Calibration */
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#define SYSCTL2_AVPLL_CTRL0_CAL_FBDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_SHIFT)) & SYSCTL2_AVPLL_CTRL0_CAL_FBDIV_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL1 - Audio PLL Control register1 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_MASK (0x1U)
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#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_SHIFT (0U)
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/*! FREQ_OFFSET_READY_C1 - Indicate Frequency Offset Value Readiness. */
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#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_READY_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_MASK (0xFFFFEU)
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#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_SHIFT (1U)
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/*! FREQ_OFFSET_C1 - FREQ_OFFSET_CX[18:0] Set */
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#define SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL1_FREQ_OFFSET_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL1_FBDIV_MASK (0x1FF00000U)
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#define SYSCTL2_AVPLL_CTRL1_FBDIV_SHIFT (20U)
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/*! FBDIV - Feedback Clock Divider Select */
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#define SYSCTL2_AVPLL_CTRL1_FBDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL1_FBDIV_SHIFT)) & SYSCTL2_AVPLL_CTRL1_FBDIV_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL2 - Audio PLL Control register2 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL2_PW_SLLP_MASK (0x7U)
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#define SYSCTL2_AVPLL_CTRL2_PW_SLLP_SHIFT (0U)
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/*! PW_SLLP - PLL in Slow Loop */
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#define SYSCTL2_AVPLL_CTRL2_PW_SLLP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PW_SLLP_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PW_SLLP_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_MASK (0x8U)
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#define SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_SHIFT (3U)
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/*! PU_OFST_CTRL_C1 - Power Up/Down FREQ_OFFSET Integrator of CX */
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#define SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PU_OFST_CTRL_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PU_C1_MASK (0x10U)
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#define SYSCTL2_AVPLL_CTRL2_PU_C1_SHIFT (4U)
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/*! PU_C1 - Power Up/Down Channel CX */
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#define SYSCTL2_AVPLL_CTRL2_PU_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PU_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PU_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PU_MASK (0x20U)
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#define SYSCTL2_AVPLL_CTRL2_PU_SHIFT (5U)
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/*! PU - PLL Power-up Signal */
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#define SYSCTL2_AVPLL_CTRL2_PU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PU_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PU_MASK)
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#define SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_MASK (0x40U)
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#define SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_SHIFT (6U)
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/*! POSTDIV_0P5_C1 - Audio Clock Divider Program Set */
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#define SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL2_POSTDIV_0P5_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_MASK (0x380U)
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#define SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_SHIFT (7U)
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/*! PLL_VDDRA_SEL - Gate Voltage Select for VDDBUF */
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#define SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_VDDRA_SEL_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_MASK (0x400U)
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#define SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_SHIFT (10U)
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/*! PLL_LPFC2_LESS - LPF C2 Capacitor Value Select */
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#define SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_LPFC2_LESS_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_MASK (0xF800U)
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#define SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_SHIFT (11U)
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/*! PLL_CALCLK_DIV - Divider Settings to Generate Calibration Clock. */
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#define SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_CALCLK_DIV_MASK)
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#define SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_MASK (0x10000U)
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#define SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_SHIFT (16U)
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/*! PLL_CAL_START - PLL Calibration Start. */
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#define SYSCTL2_AVPLL_CTRL2_PLL_CAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_SHIFT)) & SYSCTL2_AVPLL_CTRL2_PLL_CAL_START_MASK)
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#define SYSCTL2_AVPLL_CTRL2_MODE_MASK (0x60000U)
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#define SYSCTL2_AVPLL_CTRL2_MODE_SHIFT (17U)
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/*! MODE - Feedback Clock for PLL Select */
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#define SYSCTL2_AVPLL_CTRL2_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_MODE_SHIFT)) & SYSCTL2_AVPLL_CTRL2_MODE_MASK)
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#define SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_MASK (0x80000U)
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#define SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_SHIFT (19U)
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/*! MASTER_SLAVEB - This signal synchronizes frequencies of the two PLL¡¯s that are being used */
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#define SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_SHIFT)) & SYSCTL2_AVPLL_CTRL2_MASTER_SLAVEB_MASK)
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#define SYSCTL2_AVPLL_CTRL2_INTPR_MASK (0x700000U)
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#define SYSCTL2_AVPLL_CTRL2_INTPR_SHIFT (20U)
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/*! INTPR - PI Rload Resistor Select */
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#define SYSCTL2_AVPLL_CTRL2_INTPR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_INTPR_SHIFT)) & SYSCTL2_AVPLL_CTRL2_INTPR_MASK)
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#define SYSCTL2_AVPLL_CTRL2_INTPI_MASK (0x7800000U)
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#define SYSCTL2_AVPLL_CTRL2_INTPI_SHIFT (23U)
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/*! INTPI - PI Bias Current Select */
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#define SYSCTL2_AVPLL_CTRL2_INTPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_INTPI_SHIFT)) & SYSCTL2_AVPLL_CTRL2_INTPI_MASK)
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#define SYSCTL2_AVPLL_CTRL2_ICP_MASK (0x78000000U)
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#define SYSCTL2_AVPLL_CTRL2_ICP_SHIFT (27U)
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/*! ICP - Charge Pump Current Control Bits */
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#define SYSCTL2_AVPLL_CTRL2_ICP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL2_ICP_SHIFT)) & SYSCTL2_AVPLL_CTRL2_ICP_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL3 - Audio PLL Control register3 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_MASK (0xFU)
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#define SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_SHIFT (0U)
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/*! REG_SETTLE_LIMIT - Waiting Time Select Before Calibration Start.. */
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#define SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_SHIFT)) & SYSCTL2_AVPLL_CTRL3_REG_SETTLE_LIMIT_MASK)
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#define SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_MASK (0x10U)
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#define SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_SHIFT (4U)
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/*! REG_RING_EXTRA_I_EN - Extra Current Turn On Select. */
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#define SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_SHIFT)) & SYSCTL2_AVPLL_CTRL3_REG_RING_EXTRA_I_EN_MASK)
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#define SYSCTL2_AVPLL_CTRL3_REFDIV_MASK (0xFE0U)
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#define SYSCTL2_AVPLL_CTRL3_REFDIV_SHIFT (5U)
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/*! REFDIV - Reference Clock Divider Select */
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#define SYSCTL2_AVPLL_CTRL3_REFDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_REFDIV_SHIFT)) & SYSCTL2_AVPLL_CTRL3_REFDIV_MASK)
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#define SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_MASK (0xFFFFF000U)
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#define SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_SHIFT (12U)
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/*! P_SYNC1_C1 - Set DPLL¡¯s Reference Divider */
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#define SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL3_P_SYNC1_C1_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL4 - Audio PLL Control register4 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_MASK (0x1U)
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#define SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_SHIFT (0U)
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/*! SLLP_EN_DIS - Slow Loop Select. */
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#define SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_SHIFT)) & SYSCTL2_AVPLL_CTRL4_SLLP_EN_DIS_MASK)
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#define SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_MASK (0x2U)
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#define SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_SHIFT (1U)
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/*! SLLP_CLK_DIV5EN - Slow Loop Clock Enable */
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#define SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_SHIFT)) & SYSCTL2_AVPLL_CTRL4_SLLP_CLK_DIV5EN_MASK)
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#define SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_MASK (0x4U)
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#define SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_SHIFT (2U)
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/*! SEL_VTHVCOCONT - Select Threshold Source for Calibrated VDDVCO Voltage */
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#define SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_SHIFT)) & SYSCTL2_AVPLL_CTRL4_SEL_VTHVCOCONT_MASK)
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#define SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_MASK (0x1F8U)
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#define SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_SHIFT (3U)
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/*! RESERVE_PLL_IN - Reserved pins */
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#define SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_SHIFT)) & SYSCTL2_AVPLL_CTRL4_RESERVE_PLL_IN_MASK)
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#define SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_MASK (0x600U)
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#define SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_SHIFT (9U)
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/*! RESERVE_IN_C1 - Reserved pins */
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#define SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL4_RESERVE_IN_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_MASK (0x7FFFF800U)
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#define SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_SHIFT (11U)
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/*! P_SYNC2_C1 - Set DPLL¡¯s Feedback Divider */
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#define SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL4_P_SYNC2_C1_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL5 - Audio PLL Control register5 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL5_TEST_MON_MASK (0x3FU)
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#define SYSCTL2_AVPLL_CTRL5_TEST_MON_SHIFT (0U)
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/*! TEST_MON - DC Test Point Register. For Internal Use Only. */
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#define SYSCTL2_AVPLL_CTRL5_TEST_MON(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_TEST_MON_SHIFT)) & SYSCTL2_AVPLL_CTRL5_TEST_MON_MASK)
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#define SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_MASK (0xFC0U)
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#define SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_SHIFT (6U)
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/*! SPEED_THRESH - Threshold for VCO Speed Setting Calibration. */
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#define SYSCTL2_AVPLL_CTRL5_SPEED_THRESH(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_SHIFT)) & SYSCTL2_AVPLL_CTRL5_SPEED_THRESH_MASK)
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#define SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_MASK (0xF000U)
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#define SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_SHIFT (12U)
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/*! SPEED_FBRES - External feedback resistor (VCO ring) set up bits */
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#define SYSCTL2_AVPLL_CTRL5_SPEED_FBRES(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_SHIFT)) & SYSCTL2_AVPLL_CTRL5_SPEED_FBRES_MASK)
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#define SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_MASK (0x70000U)
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#define SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_SHIFT (16U)
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/*! SLLP_PSF_LEVEL - Slow Loop Current Generate. */
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#define SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_SHIFT)) & SYSCTL2_AVPLL_CTRL5_SLLP_PSF_LEVEL_MASK)
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#define SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_MASK (0xFFF80000U)
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#define SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_SHIFT (19U)
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/*! POSTDIV_C1 - Audio Clock Divider Program Set */
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#define SYSCTL2_AVPLL_CTRL5_POSTDIV_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL5_POSTDIV_C1_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL6 - Audio PLL Control register6 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_MASK (0x3U)
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#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_SHIFT (0U)
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/*! VTH_VCO_PTAT - IPTAT Current to Generate VDDVCO Voltage Select */
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#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VTH_VCO_PTAT_MASK)
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#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_MASK (0xCU)
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#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_SHIFT (2U)
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/*! VTH_VCO_CAL - VDDVCO Voltage Threshold Select */
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#define SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VTH_VCO_CAL_MASK)
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#define SYSCTL2_AVPLL_CTRL6_VDDL_MASK (0xF0U)
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#define SYSCTL2_AVPLL_CTRL6_VDDL_SHIFT (4U)
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/*! VDDL - Internal Regulated VDD Supply Voltage Control */
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#define SYSCTL2_AVPLL_CTRL6_VDDL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VDDL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VDDL_MASK)
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#define SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_MASK (0x700U)
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#define SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_SHIFT (8U)
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/*! VDDBUF_ADJ - VDDVDOFBUF Voltage Level Adjust */
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#define SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VDDBUF_ADJ_MASK)
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#define SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_MASK (0x1800U)
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#define SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_SHIFT (11U)
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/*! VDDA23_PUMP_SEL - VREF0P96_VDDA23 PUMP Select */
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#define SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VDDA23_PUMP_SEL_MASK)
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#define SYSCTL2_AVPLL_CTRL6_VCON_SEL_MASK (0x6000U)
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#define SYSCTL2_AVPLL_CTRL6_VCON_SEL_SHIFT (13U)
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/*! VCON_SEL - VCON Value Set. */
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#define SYSCTL2_AVPLL_CTRL6_VCON_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VCON_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VCON_SEL_MASK)
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#define SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_MASK (0x18000U)
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#define SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_SHIFT (15U)
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/*! VCO_REF1P45_SEL - VREF1P0V_VCO1P45 Value Select. */
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#define SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_VCO_REF1P45_SEL_MASK)
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#define SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_MASK (0x20000U)
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#define SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_SHIFT (17U)
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/*! UPDATE_SEL - PLL Update Rate Select */
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#define SYSCTL2_AVPLL_CTRL6_UPDATE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_SHIFT)) & SYSCTL2_AVPLL_CTRL6_UPDATE_SEL_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL7 - Audio PLL Control register7 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL7_PLL_LOCK_MASK (0x1000000U)
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#define SYSCTL2_AVPLL_CTRL7_PLL_LOCK_SHIFT (24U)
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/*! PLL_LOCK - Lock Detect Output */
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#define SYSCTL2_AVPLL_CTRL7_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL7_PLL_LOCK_SHIFT)) & SYSCTL2_AVPLL_CTRL7_PLL_LOCK_MASK)
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#define SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_MASK (0x2000000U)
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#define SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_SHIFT (25U)
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/*! PLL_CAL_DONE - Rising edge to indicate the end of PLL calibration */
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#define SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_SHIFT)) & SYSCTL2_AVPLL_CTRL7_PLL_CAL_DONE_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL8 - Audio PLL Control register8 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_MASK (0x1U)
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_SHIFT (0U)
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/*! AVPLL_RESET_C8 - C8 SW Reset . Active high */
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C8_MASK)
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_MASK (0x2U)
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_SHIFT (1U)
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/*! AVPLL_RESET_C1 - C1 SW Reset . Active high */
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_SHIFT)) & SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_C1_MASK)
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_MASK (0x4U)
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_SHIFT (2U)
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/*! AVPLL_RESET - SW Reset . Active high */
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#define SYSCTL2_AVPLL_CTRL8_AVPLL_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_SHIFT)) & SYSCTL2_AVPLL_CTRL8_AVPLL_RESET_MASK)
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#define SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_MASK (0x18U)
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#define SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_SHIFT (3U)
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/*! RESERVE_IN_C8 - Reserved pins */
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#define SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_RESERVE_IN_C8_MASK)
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#define SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_MASK (0x20U)
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#define SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_SHIFT (5U)
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/*! PU_OFST_CTRL_C8 - Power Up/Down FREQ_OFFSET Integrator of CX */
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#define SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_PU_OFST_CTRL_C8_MASK)
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#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_MASK (0x40U)
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#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_SHIFT (6U)
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/*! FREQ_OFFSET_READY_C8 - Indicate Frequency Offset Value Readiness. */
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#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_READY_C8_MASK)
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#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_MASK (0x3FFFF80U)
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#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_SHIFT (7U)
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/*! FREQ_OFFSET_C8 - FREQ_OFFSET_CX[18:0] Set */
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#define SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_FREQ_OFFSET_C8_MASK)
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#define SYSCTL2_AVPLL_CTRL8_EN_LP_C8_MASK (0xC000000U)
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#define SYSCTL2_AVPLL_CTRL8_EN_LP_C8_SHIFT (26U)
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/*! EN_LP_C8 - Channel CX LP Enable. */
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#define SYSCTL2_AVPLL_CTRL8_EN_LP_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_EN_LP_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_EN_LP_C8_MASK)
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#define SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_MASK (0x10000000U)
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#define SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_SHIFT (28U)
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/*! EN_DPLL_C8 - Enable/ Disable Channel CX¡¯s DPLL */
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#define SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL8_EN_DPLL_C8_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL9 - Audio PLL Control register9 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_MASK (0xFFFFFU)
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#define SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_SHIFT (0U)
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/*! P_SYNC1_C8 - Set DPLL¡¯s Reference Divider */
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#define SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL9_P_SYNC1_C8_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL10 - Audio PLL Control register10 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_MASK (0xFFFFFU)
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#define SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_SHIFT (0U)
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/*! P_SYNC2_C8 - Set DPLL¡¯s Feedback Divider */
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#define SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_SHIFT)) & SYSCTL2_AVPLL_CTRL10_P_SYNC2_C8_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL11 - Audio PLL Control register11 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_MASK (0x7FFFFU)
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#define SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_SHIFT (0U)
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/*! FREQ_OFFSET_C2 - FREQ_OFFSET_CX[18:0] Set */
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#define SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL11_FREQ_OFFSET_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_MASK (0xFFF80000U)
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#define SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_SHIFT (19U)
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/*! POSTDIV_C2 - Audio Clock Divider Program Set */
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#define SYSCTL2_AVPLL_CTRL11_POSTDIV_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL11_POSTDIV_C2_MASK)
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/*! @} */
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/*! @name AVPLL_CTRL12 - Audio PLL Control register12 */
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/*! @{ */
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#define SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_MASK (0xFFFFFU)
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#define SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_SHIFT (0U)
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/*! P_SYNC1_C2 - Set DPLL¡¯s Reference Divider */
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#define SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_P_SYNC1_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL12_EN_LP_C2_MASK (0x300000U)
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#define SYSCTL2_AVPLL_CTRL12_EN_LP_C2_SHIFT (20U)
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/*! EN_LP_C2 - Channel CX LP Enable. */
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#define SYSCTL2_AVPLL_CTRL12_EN_LP_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_EN_LP_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_EN_LP_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_MASK (0x400000U)
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#define SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_SHIFT (22U)
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/*! EN_DPLL_C2 - Enable/ Disable Channel CX¡¯s DPLL */
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#define SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_EN_DPLL_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_MASK (0x800000U)
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#define SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_SHIFT (23U)
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/*! PU_OFST_CTRL_C2 - Power Up/Down FREQ_OFFSET Integrator of CX */
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#define SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_PU_OFST_CTRL_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL12_PU_C2_MASK (0x1000000U)
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#define SYSCTL2_AVPLL_CTRL12_PU_C2_SHIFT (24U)
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/*! PU_C2 - Power Up/Down Channel CX */
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#define SYSCTL2_AVPLL_CTRL12_PU_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_PU_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_PU_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_MASK (0x2000000U)
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#define SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_SHIFT (25U)
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/*! POSTDIV_0P5_C2 - Audio Clock Divider Program Set */
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#define SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_POSTDIV_0P5_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_MASK (0x4000000U)
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#define SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_SHIFT (26U)
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/*! FREQ_OFFSET_READY_C2 - Indicate Frequency Offset Value Readiness. */
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#define SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL12_FREQ_OFFSET_READY_C2_MASK)
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/*! @} */
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/*! @name GAU_CTRL - GAU Control register */
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/*! @{ */
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#define SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_MASK (0x1U)
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#define SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_SHIFT (0U)
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/*! GAU_GPDAC_MCLK_EN - gau gpdac mclk enable */
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#define SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_GPDAC_MCLK_EN_MASK)
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#define SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_MASK (0x2U)
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#define SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_SHIFT (1U)
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/*! GAU_BG_MCLK_EN - gau bg mclk enable */
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#define SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_BG_MCLK_EN_MASK)
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#define SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_MASK (0x4U)
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#define SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_SHIFT (2U)
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/*! GAU_GPADC1_MCLK_EN - gau gpadc1 mclk enable */
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#define SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_GPADC1_MCLK_EN_MASK)
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#define SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_MASK (0x8U)
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#define SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_SHIFT (3U)
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/*! GAU_GPADC0_MCLK_EN - gau gpadc0 mclk enable */
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#define SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_GPADC0_MCLK_EN_MASK)
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#define SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_MASK (0x10U)
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#define SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_SHIFT (4U)
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/*! GAU_ACOMP_MCLK_EN - gau acomp mclk enable */
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#define SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_SHIFT)) & SYSCTL2_GAU_CTRL_GAU_ACOMP_MCLK_EN_MASK)
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/*! @} */
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/*! @name CTIMER_CTRL - CTIMER Control register */
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/*! @{ */
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#define SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_MASK (0x1U)
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#define SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_SHIFT (0U)
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/*! CT0_GLOBAL_ENABLE - ctimer0 global_enable */
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#define SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT0_GLOBAL_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_MASK (0x2U)
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#define SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_SHIFT (1U)
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/*! CT0_TRIGGER_ENABLE - ctimer0 trigger_enable */
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#define SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT0_TRIGGER_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_MASK (0x4U)
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#define SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_SHIFT (2U)
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/*! CT1_GLOBAL_ENABLE - ctimer1 global_enable */
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#define SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT1_GLOBAL_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_MASK (0x8U)
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#define SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_SHIFT (3U)
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/*! CT1_TRIGGER_ENABLE - ctimer1 trigger_enable */
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#define SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT1_TRIGGER_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_MASK (0x10U)
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#define SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_SHIFT (4U)
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/*! CT2_GLOBAL_ENABLE - ctimer2 global_enable */
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#define SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT2_GLOBAL_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_MASK (0x20U)
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#define SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_SHIFT (5U)
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/*! CT2_TRIGGER_ENABLE - ctimer2 trigger_enable */
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#define SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT2_TRIGGER_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_MASK (0x40U)
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#define SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_SHIFT (6U)
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/*! CT3_GLOBAL_ENABLE - ctimer3 global_enable */
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#define SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT3_GLOBAL_ENABLE_MASK)
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#define SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_MASK (0x80U)
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#define SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_SHIFT (7U)
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/*! CT3_TRIGGER_ENABLE - ctimer3 trigger_enable */
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#define SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_SHIFT)) & SYSCTL2_CTIMER_CTRL_CT3_TRIGGER_ENABLE_MASK)
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/*! @} */
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/*! @name EXT_H2H_CTRL - AHB async bridge Control register */
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/*! @{ */
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#define SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_MASK (0x1U)
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#define SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_SHIFT (0U)
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/*! WLAN_H2H_PREFETCH_EN - wlan_h2h_prefetch_en */
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#define SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_SHIFT)) & SYSCTL2_EXT_H2H_CTRL_WLAN_H2H_PREFETCH_EN_MASK)
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#define SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_MASK (0x2U)
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#define SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_SHIFT (1U)
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/*! BLE_H2H_PREFETCH_EN - ble_h2h_prefetch_en */
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#define SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_SHIFT)) & SYSCTL2_EXT_H2H_CTRL_BLE_H2H_PREFETCH_EN_MASK)
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/*! @} */
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/*! @name RAM_CTRL1 - RAM Memory Control Register 1 */
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/*! @{ */
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#define SYSCTL2_RAM_CTRL1_PKC_RTC_MASK (0x3U)
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#define SYSCTL2_RAM_CTRL1_PKC_RTC_SHIFT (0U)
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/*! PKC_RTC - pkc_rtc */
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#define SYSCTL2_RAM_CTRL1_PKC_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PKC_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PKC_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_PKC_WTC_MASK (0xCU)
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#define SYSCTL2_RAM_CTRL1_PKC_WTC_SHIFT (2U)
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/*! PKC_WTC - pkc_wtc */
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#define SYSCTL2_RAM_CTRL1_PKC_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PKC_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PKC_WTC_MASK)
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#define SYSCTL2_RAM_CTRL1_PQ_RTC_MASK (0x30U)
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#define SYSCTL2_RAM_CTRL1_PQ_RTC_SHIFT (4U)
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/*! PQ_RTC - pq_rtc */
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#define SYSCTL2_RAM_CTRL1_PQ_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PQ_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PQ_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_PQ_WTC_MASK (0xC0U)
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#define SYSCTL2_RAM_CTRL1_PQ_WTC_SHIFT (6U)
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/*! PQ_WTC - pq_wtc */
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#define SYSCTL2_RAM_CTRL1_PQ_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_PQ_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_PQ_WTC_MASK)
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#define SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_MASK (0x300U)
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#define SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_SHIFT (8U)
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/*! S0_SRAM_RTC - s0_sram_rtc */
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#define SYSCTL2_RAM_CTRL1_S0_SRAM_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_S0_SRAM_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_MASK (0xC00U)
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#define SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_SHIFT (10U)
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/*! S0_SRAM_WTC - s0_sram_wtc */
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#define SYSCTL2_RAM_CTRL1_S0_SRAM_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_S0_SRAM_WTC_MASK)
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#define SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_MASK (0x3000U)
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#define SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_SHIFT (12U)
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/*! SDU_CIS_RTC - sdu_cis_rtc */
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#define SYSCTL2_RAM_CTRL1_SDU_CIS_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_CIS_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_MASK (0xC000U)
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#define SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_SHIFT (14U)
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/*! SDU_CIS_WTC - sdu_cis_wtc */
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#define SYSCTL2_RAM_CTRL1_SDU_CIS_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_CIS_WTC_MASK)
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#define SYSCTL2_RAM_CTRL1_SDU_RX_RTC_MASK (0x30000U)
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#define SYSCTL2_RAM_CTRL1_SDU_RX_RTC_SHIFT (16U)
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/*! SDU_RX_RTC - sdu_rx_rtc */
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#define SYSCTL2_RAM_CTRL1_SDU_RX_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_RX_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_RX_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_SDU_RX_WTC_MASK (0xC0000U)
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#define SYSCTL2_RAM_CTRL1_SDU_RX_WTC_SHIFT (18U)
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/*! SDU_RX_WTC - sdu_rx_wtc */
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#define SYSCTL2_RAM_CTRL1_SDU_RX_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_RX_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_RX_WTC_MASK)
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#define SYSCTL2_RAM_CTRL1_SDU_TX_RTC_MASK (0x300000U)
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#define SYSCTL2_RAM_CTRL1_SDU_TX_RTC_SHIFT (20U)
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/*! SDU_TX_RTC - sdu_tx_rtc */
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#define SYSCTL2_RAM_CTRL1_SDU_TX_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_TX_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_TX_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_SDU_TX_WTC_MASK (0xC00000U)
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#define SYSCTL2_RAM_CTRL1_SDU_TX_WTC_SHIFT (22U)
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/*! SDU_TX_WTC - sdu_tx_wtc */
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#define SYSCTL2_RAM_CTRL1_SDU_TX_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_SDU_TX_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_SDU_TX_WTC_MASK)
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#define SYSCTL2_RAM_CTRL1_ENET_RTC_MASK (0x3000000U)
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#define SYSCTL2_RAM_CTRL1_ENET_RTC_SHIFT (24U)
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/*! ENET_RTC - enet_rtc */
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#define SYSCTL2_RAM_CTRL1_ENET_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_ENET_RTC_SHIFT)) & SYSCTL2_RAM_CTRL1_ENET_RTC_MASK)
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#define SYSCTL2_RAM_CTRL1_ENET_WTC_MASK (0xC000000U)
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#define SYSCTL2_RAM_CTRL1_ENET_WTC_SHIFT (26U)
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/*! ENET_WTC - enet_wtc */
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#define SYSCTL2_RAM_CTRL1_ENET_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RAM_CTRL1_ENET_WTC_SHIFT)) & SYSCTL2_RAM_CTRL1_ENET_WTC_MASK)
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/*! @} */
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/*! @name ROM_CTRL - ROM Control Register */
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/*! @{ */
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#define SYSCTL2_ROM_CTRL_ELS_RTC_MASK (0x7U)
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#define SYSCTL2_ROM_CTRL_ELS_RTC_SHIFT (0U)
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/*! ELS_RTC - els_rtc */
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#define SYSCTL2_ROM_CTRL_ELS_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_ELS_RTC_SHIFT)) & SYSCTL2_ROM_CTRL_ELS_RTC_MASK)
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#define SYSCTL2_ROM_CTRL_ELS_RTC_REF_MASK (0x18U)
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#define SYSCTL2_ROM_CTRL_ELS_RTC_REF_SHIFT (3U)
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/*! ELS_RTC_REF - els_rtc_ref */
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#define SYSCTL2_ROM_CTRL_ELS_RTC_REF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_ELS_RTC_REF_SHIFT)) & SYSCTL2_ROM_CTRL_ELS_RTC_REF_MASK)
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#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_MASK (0xE0U)
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#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_SHIFT (5U)
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/*! S0_ROM_RTC - s0_rom_rtc */
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#define SYSCTL2_ROM_CTRL_S0_ROM_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_S0_ROM_RTC_SHIFT)) & SYSCTL2_ROM_CTRL_S0_ROM_RTC_MASK)
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#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_MASK (0x300U)
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#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_SHIFT (8U)
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/*! S0_ROM_RTC_REF - s0_rom_rtc_ref */
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#define SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_SHIFT)) & SYSCTL2_ROM_CTRL_S0_ROM_RTC_REF_MASK)
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/*! @} */
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/*! @name MEM_PD_CTRL - MEM PD Control enable register when PM2 mode */
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/*! @{ */
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#define SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_MASK (0x1U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_SHIFT (0U)
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/*! SRAM0_SW_CTRL_EN - SW control sram0 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM0_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_MASK (0x2U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_SHIFT (1U)
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/*! SRAM1_SW_CTRL_EN - SW control sram1 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM1_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_MASK (0x4U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_SHIFT (2U)
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/*! SRAM2_SW_CTRL_EN - SW control sram2 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM2_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_MASK (0x8U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_SHIFT (3U)
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/*! SRAM3_SW_CTRL_EN - SW control sram3 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM3_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_MASK (0x10U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_SHIFT (4U)
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/*! SRAM4_SW_CTRL_EN - SW control sram4 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM4_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_MASK (0x20U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_SHIFT (5U)
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/*! SRAM5_SW_CTRL_EN - SW control sram5 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM5_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_MASK (0x40U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_SHIFT (6U)
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/*! SRAM6_SW_CTRL_EN - SW control sram6 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM6_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_MASK (0x80U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_SHIFT (7U)
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/*! SRAM7_SW_CTRL_EN - SW control sram7 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM7_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_MASK (0x100U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_SHIFT (8U)
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/*! SRAM8_SW_CTRL_EN - SW control sram8 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM8_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_MASK (0x200U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_SHIFT (9U)
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/*! SRAM9_SW_CTRL_EN - SW control sram9 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM9_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_MASK (0x400U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_SHIFT (10U)
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/*! SRAM10_SW_CTRL_EN - SW control sram10 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM10_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_MASK (0x800U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_SHIFT (11U)
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/*! SRAM11_SW_CTRL_EN - SW control sram11 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM11_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_MASK (0x1000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_SHIFT (12U)
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/*! SRAM12_SW_CTRL_EN - SW control sram12 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM12_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_MASK (0x2000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_SHIFT (13U)
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/*! SRAM13_SW_CTRL_EN - SW control sram13 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM13_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_MASK (0x4000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_SHIFT (14U)
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/*! SRAM14_SW_CTRL_EN - SW control sram14 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM14_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_MASK (0x8000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_SHIFT (15U)
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/*! SRAM15_SW_CTRL_EN - SW control sram15 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM15_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_MASK (0x10000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_SHIFT (16U)
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/*! SRAM16_SW_CTRL_EN - SW control sram16 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM16_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_MASK (0x20000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_SHIFT (17U)
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/*! SRAM17_SW_CTRL_EN - SW control sram17 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM17_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_MASK (0x40000U)
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#define SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_SHIFT (18U)
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/*! SRAM18_SW_CTRL_EN - SW control sram18 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SRAM18_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_MASK (0x80000U)
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#define SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_SHIFT (19U)
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/*! AON0_SW_CTRL_EN - SW control aon0 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_AON0_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_MASK (0x100000U)
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#define SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_SHIFT (20U)
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/*! AON1_SW_CTRL_EN - SW control aon1 mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_AON1_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_MASK (0x200000U)
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#define SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_SHIFT (21U)
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/*! ELS_SW_CTRL_EN - SW control els mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_ELS_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_MASK (0x400000U)
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#define SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_SHIFT (22U)
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/*! PKC_SW_CTRL_EN - SW control pkc mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_PKC_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_MASK (0x800000U)
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#define SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_SHIFT (23U)
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/*! PQ_SW_CTRL_EN - SW control pq mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_PQ_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_MASK (0x1000000U)
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#define SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_SHIFT (24U)
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/*! FLEXSPI_SW_CTRL_EN - SW control flexspi mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_FLEXSPI_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_MASK (0x2000000U)
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#define SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_SHIFT (25U)
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/*! ROM_SW_CTRL_EN - SW control rom mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_ROM_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_MASK (0x4000000U)
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#define SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_SHIFT (26U)
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/*! OTP_SW_CTRL_EN - SW control otp mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_OTP_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_MASK (0x8000000U)
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#define SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_SHIFT (27U)
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/*! SDIO_SW_CTRL_EN - SW control sdio mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_SDIO_SW_CTRL_EN_MASK)
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#define SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_MASK (0x10000000U)
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#define SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_SHIFT (28U)
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/*! ENET_SW_CTRL_EN - SW control enet mem_pd signal enable when PM2 mode */
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#define SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_SHIFT)) & SYSCTL2_MEM_PD_CTRL_ENET_SW_CTRL_EN_MASK)
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/*! @} */
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/*! @name MEM_PD_CFG - MEM PD Configure register when PM2 mode */
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/*! @{ */
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#define SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_MASK (0x1U)
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#define SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_SHIFT (0U)
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/*! SRAM0_SW_CFG - sw cfg sram0 mem_pdwn signal when PM2 mode; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM0_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_MASK (0x2U)
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#define SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_SHIFT (1U)
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/*! SRAM1_SW_CFG - sw cfg sram1 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM1_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_MASK (0x4U)
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#define SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_SHIFT (2U)
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/*! SRAM2_SW_CFG - sw cfg sram2 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM2_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_MASK (0x8U)
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#define SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_SHIFT (3U)
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/*! SRAM3_SW_CFG - sw cfg sram3 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM3_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_MASK (0x10U)
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#define SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_SHIFT (4U)
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/*! SRAM4_SW_CFG - sw cfg sram4 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM4_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_MASK (0x20U)
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#define SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_SHIFT (5U)
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/*! SRAM5_SW_CFG - sw cfg sram5 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM5_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_MASK (0x40U)
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#define SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_SHIFT (6U)
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/*! SRAM6_SW_CFG - sw cfg sram6 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM6_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_MASK (0x80U)
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#define SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_SHIFT (7U)
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/*! SRAM7_SW_CFG - sw cfg sram7 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM7_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_MASK (0x100U)
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#define SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_SHIFT (8U)
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/*! SRAM8_SW_CFG - sw cfg sram8 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM8_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_MASK (0x200U)
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#define SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_SHIFT (9U)
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/*! SRAM9_SW_CFG - sw cfg sram9 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM9_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_MASK (0x400U)
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#define SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_SHIFT (10U)
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/*! SRAM10_SW_CFG - sw cfg sram mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM10_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_MASK (0x800U)
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#define SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_SHIFT (11U)
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/*! SRAM11_SW_CFG - sw cfg sram11 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM11_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_MASK (0x1000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_SHIFT (12U)
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/*! SRAM12_SW_CFG - sw cfg sram12 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM12_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_MASK (0x2000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_SHIFT (13U)
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/*! SRAM13_SW_CFG - sw cfg sram13 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM13_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_MASK (0x4000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_SHIFT (14U)
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/*! SRAM14_SW_CFG - sw cfg sram14 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM14_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_MASK (0x8000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_SHIFT (15U)
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/*! SRAM15_SW_CFG - sw cfg sram15 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM15_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_MASK (0x10000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_SHIFT (16U)
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/*! SRAM16_SW_CFG - sw cfg sram16 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM16_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_MASK (0x20000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_SHIFT (17U)
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/*! SRAM17_SW_CFG - sw cfg sram17 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM17_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_MASK (0x40000U)
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#define SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_SHIFT (18U)
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/*! SRAM18_SW_CFG - sw cfg sram18 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SRAM18_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_MASK (0x80000U)
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#define SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_SHIFT (19U)
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/*! AON0_SW_CFG - sw cfg aon0 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_AON0_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_AON0_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_MASK (0x100000U)
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#define SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_SHIFT (20U)
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/*! AON1_SW_CFG - sw cfg aon1 mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_AON1_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_AON1_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_MASK (0x200000U)
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#define SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_SHIFT (21U)
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/*! ELS_SW_CFG - sw cfg els mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_ELS_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_ELS_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_MASK (0x400000U)
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#define SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_SHIFT (22U)
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/*! PKC_SW_CFG - sw cfg pkc mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_PKC_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_PKC_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_MASK (0x800000U)
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#define SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_SHIFT (23U)
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/*! PQ_SW_CFG - sw cfg pq mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_PQ_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_PQ_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_MASK (0x1000000U)
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#define SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_SHIFT (24U)
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/*! FLEXSPI_SW_CFG - sw cfg flexspi mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_FLEXSPI_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_MASK (0x2000000U)
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#define SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_SHIFT (25U)
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/*! ROM_SW_CFG - sw cfg rom mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_ROM_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_ROM_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_MASK (0x4000000U)
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#define SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_SHIFT (26U)
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/*! OTP_SW_CFG - sw cfg otp mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_OTP_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_OTP_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_MASK (0x8000000U)
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#define SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_SHIFT (27U)
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/*! SDIO_SW_CFG - sw cfg sdio mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_SDIO_SW_CFG_MASK)
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#define SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_MASK (0x10000000U)
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#define SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_SHIFT (28U)
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/*! ENET_SW_CFG - sw cfg enet mem_pdwn signal when PM2 mode ; 0: active; 1: power down */
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#define SYSCTL2_MEM_PD_CFG_ENET_SW_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_SHIFT)) & SYSCTL2_MEM_PD_CFG_ENET_SW_CFG_MASK)
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/*! @} */
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/*! @name ENET_IN_SEL_TIMER - Select input source for enet pad0 */
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/*! @{ */
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#define SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_MASK (0x1U)
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#define SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_SHIFT (0U)
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/*! ENET_IN_SEL_TIMER - select input source as enet input */
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#define SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_SHIFT)) & SYSCTL2_ENET_IN_SEL_TIMER_ENET_IN_SEL_TIMER_MASK)
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/*! @} */
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/*! @name ENET_IPG_STOP - Configure ipg_stop, used by enet wakeup sequence */
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/*! @{ */
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#define SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_MASK (0x1U)
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#define SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_SHIFT (0U)
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/*! ENET_IPG_STOP - Configure ipg_stop, used by enet wakeup sequence; 0: Drive enet input IPG_STOP low; 1: Drive enet input IPG_STOP high. */
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#define SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_SHIFT)) & SYSCTL2_ENET_IPG_STOP_ENET_IPG_STOP_MASK)
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/*! @} */
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/*! @name ENET_IPG_STOP_ACK - Store ipg_stop_ack, used by enet wakeup sequence */
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/*! @{ */
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#define SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_MASK (0x1U)
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#define SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_SHIFT (0U)
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/*! ENET_IPG_STOP_ACK - Store ipg_stop_ack, used by enet wakeup sequence */
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#define SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_SHIFT)) & SYSCTL2_ENET_IPG_STOP_ACK_ENET_IPG_STOP_ACK_MASK)
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/*! @} */
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/*! @name ROM_BRU_ADDR_MASK_DIS - Disable dynamic address masking feature */
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/*! @{ */
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#define SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_MASK (0x1U)
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#define SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_SHIFT (0U)
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/*! ROM_BRU_ADDR_MASK_DIS - Disable dynamic address masking feature */
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#define SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_SHIFT)) & SYSCTL2_ROM_BRU_ADDR_MASK_DIS_ROM_BRU_ADDR_MASK_DIS_MASK)
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/*! @} */
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/*! @name ROM_BRU_DYN_CLK_DIS - Disable dynamic clock gating feature */
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/*! @{ */
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#define SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_MASK (0x1U)
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#define SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_SHIFT (0U)
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/*! ROM_BRU_DYN_CLK_DIS - Disable dynamic clock gating feature */
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#define SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_SHIFT)) & SYSCTL2_ROM_BRU_DYN_CLK_DIS_ROM_BRU_DYN_CLK_DIS_MASK)
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/*! @} */
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/*! @name OTP_EARLY_FUSE_VALID - Early fuse valid from OTP */
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/*! @{ */
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#define SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_MASK (0x1U)
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#define SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_SHIFT (0U)
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/*! OTP_EARLY_FUSE_VALID - Early fuse valid from OTP */
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#define SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_SHIFT)) & SYSCTL2_OTP_EARLY_FUSE_VALID_OTP_EARLY_FUSE_VALID_MASK)
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/*! @} */
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/*! @name OTP_MEDIUM_FUSE_VALID - Medium fuse valid from OTP */
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/*! @{ */
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#define SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_MASK (0x1U)
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#define SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_SHIFT (0U)
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/*! OTP_MEDIUM_FUSE_VALID - Medium fuse valid from OTP */
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#define SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_SHIFT)) & SYSCTL2_OTP_MEDIUM_FUSE_VALID_OTP_MEDIUM_FUSE_VALID_MASK)
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/*! @} */
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/*! @name OTP_ALL_FUSE_VALID - All fuse valid from OTP */
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/*! @{ */
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#define SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_MASK (0x1U)
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#define SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_SHIFT (0U)
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/*! OTP_ALL_FUSE_VALID - All fuse valid from OTP */
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#define SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_SHIFT)) & SYSCTL2_OTP_ALL_FUSE_VALID_OTP_ALL_FUSE_VALID_MASK)
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/*! @} */
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/*! @name PLL_CTRL - PLL control register */
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/*! @{ */
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#define SYSCTL2_PLL_CTRL_T3_PDB_MASK (0x1U)
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#define SYSCTL2_PLL_CTRL_T3_PDB_SHIFT (0U)
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/*! T3_PDB - T3 PLL enable signal from SOC */
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#define SYSCTL2_PLL_CTRL_T3_PDB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_T3_PDB_SHIFT)) & SYSCTL2_PLL_CTRL_T3_PDB_MASK)
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#define SYSCTL2_PLL_CTRL_T3_LOCK_MASK (0x2U)
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#define SYSCTL2_PLL_CTRL_T3_LOCK_SHIFT (1U)
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/*! T3_LOCK - T3 output clock lock signal */
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#define SYSCTL2_PLL_CTRL_T3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_T3_LOCK_SHIFT)) & SYSCTL2_PLL_CTRL_T3_LOCK_MASK)
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#define SYSCTL2_PLL_CTRL_TDDR_PDB_MASK (0x8U)
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#define SYSCTL2_PLL_CTRL_TDDR_PDB_SHIFT (3U)
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/*! TDDR_PDB - TDDR PLL enable signal from SOC */
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#define SYSCTL2_PLL_CTRL_TDDR_PDB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TDDR_PDB_SHIFT)) & SYSCTL2_PLL_CTRL_TDDR_PDB_MASK)
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#define SYSCTL2_PLL_CTRL_TDDR_LOCK_MASK (0x10U)
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#define SYSCTL2_PLL_CTRL_TDDR_LOCK_SHIFT (4U)
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/*! TDDR_LOCK - TDDR output clock lock signal */
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#define SYSCTL2_PLL_CTRL_TDDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TDDR_LOCK_SHIFT)) & SYSCTL2_PLL_CTRL_TDDR_LOCK_MASK)
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#define SYSCTL2_PLL_CTRL_TCPU_PDB_MASK (0x20U)
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#define SYSCTL2_PLL_CTRL_TCPU_PDB_SHIFT (5U)
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/*! TCPU_PDB - TCPU PLL enable signal from SOC */
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#define SYSCTL2_PLL_CTRL_TCPU_PDB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_PDB_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_PDB_MASK)
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#define SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK (0x40U)
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#define SYSCTL2_PLL_CTRL_TCPU_LOCK_SHIFT (6U)
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/*! TCPU_LOCK - TCPU output clock lock signal */
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#define SYSCTL2_PLL_CTRL_TCPU_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_LOCK_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK)
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#define SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK (0x180U)
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#define SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_SHIFT (7U)
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/*! TCPU_FLEXSPI_CLK_SEL - TCPU_PLL DIV selection(00:3120/12; 01:3120/11; 10: 3120/10; 11:3120/9) */
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#define SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK)
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#define SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK (0x1FE00U)
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#define SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIFT (9U)
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/*! TCPU_FBDIV - TCPU_PLL Feedback Divider Value ( Fxtal 40MHZ: 75 to 96 (decimal); 38.4MHz 78 to 100 (decimal)) */
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#define SYSCTL2_PLL_CTRL_TCPU_FBDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK)
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#define SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK (0x60000U)
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#define SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_SHIFT (17U)
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/*! TDDR_FLEXSPI_CLK_SEL - TDDR_PLL Clock selection from SOC for DDR CLOCK (00:3.2GHZ/11; 01: 3.2GHZ/10; 10: 3.2GHz/9;11: 3.2GHz/8) */
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#define SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_SHIFT)) & SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK)
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#define SYSCTL2_PLL_CTRL_T3_ITRC_EN_MASK (0x80000U)
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#define SYSCTL2_PLL_CTRL_T3_ITRC_EN_SHIFT (19U)
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/*! T3_ITRC_EN - 0-disable the unlock event to ITRC; 1-enable the unlock event to ITRC */
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#define SYSCTL2_PLL_CTRL_T3_ITRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_T3_ITRC_EN_SHIFT)) & SYSCTL2_PLL_CTRL_T3_ITRC_EN_MASK)
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#define SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_MASK (0x100000U)
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#define SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_SHIFT (20U)
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/*! TCPU_ITRC_EN - 0-disable the unlock event to ITRC; 1-enable the unlock event to ITRC */
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#define SYSCTL2_PLL_CTRL_TCPU_ITRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_SHIFT)) & SYSCTL2_PLL_CTRL_TCPU_ITRC_EN_MASK)
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/*! @} */
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/*! @name ANA_PDWN_PM2 - ana_pdwn control signal when PM2 mode */
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/*! @{ */
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#define SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_MASK (0x1U)
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#define SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_SHIFT (0U)
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/*! AVPLL_ANA_PDWN_PM2 - AVPLL ana_pdwn control signal when PM2 mode, 1: AVPLL is low power mode when PM2 0: AVPLL is normal mode when PM2 */
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#define SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_AVPLL_ANA_PDWN_PM2_MASK)
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#define SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_MASK (0x2U)
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#define SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_SHIFT (1U)
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/*! USB_ANA_PDWN_PM2 - USB ana_pdwn control signal when PM2 mode, 1: USB is low power mode when PM2 0: USB is normal mode when PM2 */
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#define SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_USB_ANA_PDWN_PM2_MASK)
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#define SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_MASK (0x4U)
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#define SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_SHIFT (2U)
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/*! GAU_ANA_PDWN_PM2 - GAU ana_pdwn control signal when PM2 mode, 1: GAU is low power mode when PM2 0: GAU is normal mode when PM2 */
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#define SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_GAU_ANA_PDWN_PM2_MASK)
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#define SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_MASK (0x8U)
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#define SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_SHIFT (3U)
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/*! ANA_TOP_ANA_PDWN_PM2 - ANA_TOP ana_pdwn control signal when PM2 mode, 1: ANA_TOP is low power mode when PM2 0: ANA_TOP is normal mode when PM2 */
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#define SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_ANA_TOP_ANA_PDWN_PM2_MASK)
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#define SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_MASK (0x10U)
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#define SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_SHIFT (4U)
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/*! TDDR_TOP_ANA_PDWN_PM2 - TDDR_TOP ana_pdwn control signal when PM2 mode, 1: TDDR_TOP is low power
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* mode when PM2 0: TDDR_TOP is normal mode when PM2
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*/
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#define SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_TDDR_TOP_ANA_PDWN_PM2_MASK)
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#define SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_MASK (0x20U)
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#define SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_SHIFT (5U)
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/*! TCPU_TOP_ANA_PDWN_PM2 - TCPU_TOP ana_pdwn control signal when PM2 mode, 1: TCPU_TOP is low power
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* mode when PM2 0: TCPU_TOP is normal mode when PM2
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*/
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#define SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_TCPU_TOP_ANA_PDWN_PM2_MASK)
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#define SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_MASK (0x40U)
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#define SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_SHIFT (6U)
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/*! T3_ANA_PDWN_PM2 - T3 ana_pdwn control signal when PM2 mode, 1: T3 is low power mode when PM2 0: T3 is normal mode when PM2 */
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#define SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_SHIFT)) & SYSCTL2_ANA_PDWN_PM2_T3_ANA_PDWN_PM2_MASK)
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/*! @} */
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/*! @name SOURCE_CLK_GATE - source clock gate control */
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/*! @{ */
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#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_MASK (0x1U)
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#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_SHIFT (0U)
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/*! TCPU_MCI_CLK_CG - gate tcpu_mci_clk */
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#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_CLK_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_MASK (0x2U)
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#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_SHIFT (1U)
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/*! TCPU_MCI_FLEXSPI_CLK_CG - gate tcpu_mci_flexspi_clk */
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#define SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TCPU_MCI_FLEXSPI_CLK_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_MASK (0x4U)
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#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_SHIFT (2U)
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/*! TDDR_MCI_ENET_CLK_CG - gate tddr_mci_enet_clk */
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#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_ENET_CLK_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_MASK (0x8U)
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#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_SHIFT (3U)
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/*! TDDR_MCI_FLEXSPI_CLK_CG - gate tddr_mci_flexspi_clk */
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#define SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_TDDR_MCI_FLEXSPI_CLK_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_MASK (0x10U)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_SHIFT (4U)
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/*! T3PLL_MCI_48_60M_IRC_CG - gate t3pll_mci_48_60m_irc */
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_48_60M_IRC_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK (0x20U)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_SHIFT (5U)
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/*! T3PLL_MCI_256M_CG - gate t3pll_mci_256m */
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_MASK (0x40U)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_SHIFT (6U)
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/*! T3PLL_MCI_213P3M_CG - gate t3pll_mci_213p3m */
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_213P3M_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_MASK (0x80U)
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_SHIFT (7U)
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/*! T3PLL_MCI_FLEXSPI_CLK_CG - gate t3pll_mci_flexspi_clk */
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#define SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_FLEXSPI_CLK_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK (0x200U)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_SHIFT (9U)
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/*! REFCLK_SYS_CG - gate refclk_sys */
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_MASK (0x10000U)
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#define SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_SHIFT (16U)
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/*! CPU_CLK_EN - enable cpu clk(c0_fr_hclk) bypass PMU gate_cpu_clk control */
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#define SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_CPU_CLK_EN_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_MASK (0x10000000U)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_SHIFT (28U)
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/*! REFCLK_TCPU_CG - gate CAU_PHY_RECLK_CPR_TCPU request when PM0; 1:request;0:no request */
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_TCPU_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_MASK (0x20000000U)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_SHIFT (29U)
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/*! REFCLK_TDDR_CG - gate CAU_PHY_RECLK_CPR_TDDR request when PM0; MCI request CAU gate reference
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* clock for PHY in PM2 mode (when USB/AUD/TCPU/TDDR PLL are all power down); 1:request;0:no request
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*/
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_TDDR_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_MASK (0x40000000U)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_SHIFT (30U)
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/*! REFCLK_AUD_CG - gate CAU_PHY_RECLK_CPR_AUD request when PM0; 1:request;0:no request */
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_AUD_CG_MASK)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_MASK (0x80000000U)
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_SHIFT (31U)
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/*! REFCLK_USB_CG - gate CAU_PHY_RECLK_CPR_USB request when PM0;1:request;0:no request */
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#define SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_SHIFT)) & SYSCTL2_SOURCE_CLK_GATE_REFCLK_USB_CG_MASK)
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/*! @} */
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/*! @name TRNG_PWR_MODE - TRNG_PWR_MODE */
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/*! @{ */
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#define SYSCTL2_TRNG_PWR_MODE_STOP_REQ_MASK (0x1U)
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#define SYSCTL2_TRNG_PWR_MODE_STOP_REQ_SHIFT (0U)
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/*! STOP_REQ - The bit is used as the SoC low-power request. It is generated to tell TRNG that the
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* clock to TRNG is going to stop running. This signal will be asserted no less than two clocks
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* before TRNG clock is stopped, to allow TRNG to prepare for stop mode.0: No request; 1:Request
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*/
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#define SYSCTL2_TRNG_PWR_MODE_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PWR_MODE_STOP_REQ_SHIFT)) & SYSCTL2_TRNG_PWR_MODE_STOP_REQ_MASK)
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#define SYSCTL2_TRNG_PWR_MODE_STOP_ACK_MASK (0x2U)
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#define SYSCTL2_TRNG_PWR_MODE_STOP_ACK_SHIFT (1U)
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/*! STOP_ACK - The bit is used as the SoC low-power acknowledge. TRNG will generate this single
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* clock cycle pulse one clock cycle after STOP_REQ has been asserted.0:No Acknowledge; 1:Acknowledge
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*/
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#define SYSCTL2_TRNG_PWR_MODE_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PWR_MODE_STOP_ACK_SHIFT)) & SYSCTL2_TRNG_PWR_MODE_STOP_ACK_MASK)
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/*! @} */
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/*! @name TRNG_PIN_CTRL - TRNG_PIN_CTRL */
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/*! @{ */
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#define SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK (0x1U)
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#define SYSCTL2_TRNG_PIN_CTRL_ENABLE_SHIFT (0U)
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/*! ENABLE - The bit is used to control the interface of TRNG. 0:Disable; 1: Enable */
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#define SYSCTL2_TRNG_PIN_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PIN_CTRL_ENABLE_SHIFT)) & SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK)
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#define SYSCTL2_TRNG_PIN_CTRL_BUSY_MASK (0x2U)
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#define SYSCTL2_TRNG_PIN_CTRL_BUSY_SHIFT (1U)
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/*! BUSY - The bit indicate that the TRNG is busy. This happens when the TRNG is busy sampling the
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|
* entropy bits and has not issued an entropy valid signal.0: Free; 1: Busy; this bit should be
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* zero after ENABLE(bit0 in this register) is set
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*/
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#define SYSCTL2_TRNG_PIN_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PIN_CTRL_BUSY_SHIFT)) & SYSCTL2_TRNG_PIN_CTRL_BUSY_MASK)
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#define SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_MASK (0x4U)
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#define SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_SHIFT (2U)
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/*! HW_ERROR - The bit indicate that the TRNG has generated a hardware error. This could be due to a
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|
* Frequency Count Fail, a run time or power on reset parameter misconfiguration, and /or a
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|
* failure of one or more of the built in internal entropy quality tests. The cause of the error can
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|
* be decoded by checking the bits of the STATUS register of TRNG.0:No Error; 1: Error
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|
*/
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#define SYSCTL2_TRNG_PIN_CTRL_HW_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_SHIFT)) & SYSCTL2_TRNG_PIN_CTRL_HW_ERROR_MASK)
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/*! @} */
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/*! @name CAU_CTRL - CAU control register */
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/*! @{ */
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#define SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_MASK (0x1U)
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#define SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_SHIFT (0U)
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/*! SOC_REFCLK_RDY - REFCLK ready signal, if 1, can turn on PLL */
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#define SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_SHIFT)) & SYSCTL2_CAU_CTRL_SOC_REFCLK_RDY_MASK)
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#define SYSCTL2_CAU_CTRL_MCI_XOSC_EN_MASK (0x80000000U)
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#define SYSCTL2_CAU_CTRL_MCI_XOSC_EN_SHIFT (31U)
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/*! MCI_XOSC_EN - mci request control different modes for CAU XTAL (1 for normal mode, 0 for sleep/full PD) */
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#define SYSCTL2_CAU_CTRL_MCI_XOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_CAU_CTRL_MCI_XOSC_EN_SHIFT)) & SYSCTL2_CAU_CTRL_MCI_XOSC_EN_MASK)
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/*! @} */
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/*! @name SOC_CIU_RDY_MASK - SOC_CIU_RDY_MASK */
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|
/*! @{ */
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#define SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_MASK (0x1U)
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#define SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_SHIFT (0U)
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/*! SOC_CIU_RDY_MASK - 1'b1:mask SOC_CIU_RDY, think its value is 1; 1'b0:unmask SOC_CIU_RDY, see its real value */
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#define SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_SHIFT)) & SYSCTL2_SOC_CIU_RDY_MASK_SOC_CIU_RDY_MASK_MASK)
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/*! @} */
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/*! @name LE_AUDIO_TIMER_ENABLE - Enable bit for le audio timer */
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/*! @{ */
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#define SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_MASK (0x1U)
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#define SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_SHIFT (0U)
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/*! ENABLE - 1'b1:Timer is enabled; 1'b0:Timer is disabled */
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#define SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_ENABLE_ENABLE_MASK)
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/*! @} */
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/*! @name LE_AUDIO_TIMER_CNT_CLR - Clear bit of internal counter */
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/*! @{ */
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|
#define SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_MASK (0x1U)
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|
#define SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_SHIFT (0U)
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|
/*! CLR - When timer is enabled, write 1 to clear internal counter, write 0 has no effect */
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#define SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT_CLR_CLR_MASK)
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|
/*! @} */
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/*! @name LE_AUDIO_TIMER_CNT0 - Counter value captured by trigger0 */
|
|
/*! @{ */
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|
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|
#define SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_SHIFT (0U)
|
|
/*! CNT0 - Counter value captured by trigger0 */
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT0_CNT0_MASK)
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|
/*! @} */
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/*! @name LE_AUDIO_TIMER_CNT1 - Counter value captured by trigger1 */
|
|
/*! @{ */
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|
#define SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_SHIFT (0U)
|
|
/*! CNT1 - Counter value captured by trigger1 */
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT1_CNT1_MASK)
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|
/*! @} */
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|
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/*! @name LE_AUDIO_TIMER_CNT2 - Counter value captured by trigger2 */
|
|
/*! @{ */
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|
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_SHIFT (0U)
|
|
/*! CNT2 - Counter value captured by trigger2 */
|
|
#define SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_SHIFT)) & SYSCTL2_LE_AUDIO_TIMER_CNT2_CNT2_MASK)
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|
/*! @} */
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|
|
|
/*! @name AVPLL_CTRL13 - Audio PLL Control register13 */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_MASK (0x1U)
|
|
#define SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_SHIFT (0U)
|
|
/*! AVPLL_RESET_C2 - C2 SW Reset . Active high */
|
|
#define SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL13_AVPLL_RESET_C2_MASK)
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|
|
#define SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_MASK (0x600U)
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|
#define SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_SHIFT (9U)
|
|
/*! RESERVE_IN_C2 - Reserved pins */
|
|
#define SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL13_RESERVE_IN_C2_MASK)
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#define SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_MASK (0x7FFFF800U)
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|
#define SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_SHIFT (11U)
|
|
/*! P_SYNC2_C2 - Set DPLL¡¯s Feedback Divider */
|
|
#define SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_SHIFT)) & SYSCTL2_AVPLL_CTRL13_P_SYNC2_C2_MASK)
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|
/*! @} */
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|
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/*! @name MEM_ACC_CHK_CODE_VIO_STATUS - CPU Code Bus Access Sram Checker Violation Status */
|
|
/*! @{ */
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|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_MASK (0x7FFFFU)
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|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_SHIFT (0U)
|
|
/*! STATUS - for each of these 19 bits: 0- No violation; 1-violation happened */
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|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_STATUS_STATUS_MASK)
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|
/*! @} */
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|
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|
/*! @name MEM_ACC_CHK_CODE_VIO_CLR - CPU Code Bus Access Sram Checker Violation Status Clear */
|
|
/*! @{ */
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|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_MASK (0x7FFFFU)
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|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_SHIFT (0U)
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|
/*! STATUS_CLR - Write '1' to clear Violation Status bit; These bits are self-clear */
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_CLR_STATUS_CLR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_STATUS - CPU SYS Bus Access Sram Checker Violation Status */
|
|
/*! @{ */
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|
|
|
#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_MASK (0x7FFFFU)
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|
#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_SHIFT (0U)
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|
/*! STATUS - for each of these 19 bits: 0- No violation; 1-violation happened */
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|
#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_STATUS_STATUS_MASK)
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|
/*! @} */
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|
|
|
/*! @name MEM_ACC_CHK_SYS_VIO_CLR - CPU SYS Bus Access Sram Checker Violation Status Clear */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_MASK (0x7FFFFU)
|
|
#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_SHIFT (0U)
|
|
/*! STATUS_CLR - Write '1' to clear Violation Status bit; These bits are self-clear */
|
|
#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_CLR_STATUS_CLR_MASK)
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|
/*! @} */
|
|
|
|
/*! @name SOC_MCI_EXTRA - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_SHIFT (0U)
|
|
/*! SOC_MCI_EXTRA - Reserved register */
|
|
#define SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_SHIFT)) & SYSCTL2_SOC_MCI_EXTRA_SOC_MCI_EXTRA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCI_SOC_EXTRA - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_SHIFT (0U)
|
|
/*! MCI_SOC_EXTRA - Reserved register */
|
|
#define SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_SHIFT)) & SYSCTL2_MCI_SOC_EXTRA_MCI_SOC_EXTRA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ROM_DYN_CLK_EN - To control dynamic clock gating of the rom clock */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_MASK (0x2U)
|
|
#define SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_SHIFT (1U)
|
|
/*! ROM_DYN_CLK_EN - To control dynamic clock gating of the rom clock
|
|
* 0b0..Disable the clock gating
|
|
* 0b1..Enable the clock gating
|
|
*/
|
|
#define SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_SHIFT)) & SYSCTL2_ROM_DYN_CLK_EN_ROM_DYN_CLK_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG1 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG1_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG1_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG1_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG1_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG1_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG2 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG2_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG2_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG2_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG2_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG2_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG3 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG3_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG3_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG3_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG3_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG3_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG4 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG4_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG4_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG4_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG4_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG4_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG5 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG5_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG5_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG5_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG5_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG5_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG6 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG6_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG6_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG6_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG6_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG6_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RESERVED_REG7 - Reserved register */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_RESERVED_REG7_RESERVED_REG_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_RESERVED_REG7_RESERVED_REG_SHIFT (0U)
|
|
/*! RESERVED_REG - Reserved register */
|
|
#define SYSCTL2_RESERVED_REG7_RESERVED_REG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_RESERVED_REG7_RESERVED_REG_SHIFT)) & SYSCTL2_RESERVED_REG7_RESERVED_REG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM_ACC_CHK_CODE_VIO_ADDR0 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_MASK (0xFFFFFFFFU)
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_SHIFT (0U)
|
|
/*! ADDR - Address of Violated Transfer */
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR0_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM_ACC_CHK_CODE_VIO_MISC0 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_MASK (0x1U)
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_SHIFT (0U)
|
|
/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_WRITE_MASK)
|
|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_MASK (0x2U)
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_SHIFT (1U)
|
|
/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HPROT0_MASK)
|
|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_MASK (0xF0U)
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_SHIFT (4U)
|
|
/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC0_HSEC_LEVEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM_ACC_CHK_CODE_VIO_ADDR1 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
|
|
/*! @{ */
|
|
|
|
#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR1_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC1 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC1_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR2 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR2_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC2 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC2_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR3 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR3_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC3 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC3_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR4 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR4_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC4 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC4_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR5 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR5_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC5 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC5_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR6 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR6_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC6 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC6_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR7 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR7_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC7 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC7_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR8 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR8_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC8 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC8_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR9 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR9_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC9 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC9_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR10 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR10_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC10 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC10_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR11 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR11_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC11 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC11_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR12 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR12_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC12 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC12_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR13 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR13_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC13 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC13_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR14 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR14_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC14 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC14_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR15 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR15_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC15 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC15_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR16 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR16_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC16 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC16_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR17 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR17_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC17 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC17_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_ADDR18 - CPU CODE Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_ADDR18_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_CODE_VIO_MISC18 - CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_CODE_VIO_MISC18_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR0 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR0_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC0 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC0_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR1 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR1_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC1 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC1_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR2 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR2_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC2 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC2_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR3 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR3_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC3 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC3_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR4 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR4_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC4 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC4_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR5 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR5_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC5 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC5_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR6 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR6_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC6 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC6_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR7 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR7_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC7 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC7_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR8 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR8_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC8 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC8_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR9 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR9_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC9 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC9_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR10 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR10_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC10 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC10_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR11 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR11_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC11 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC11_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR12 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR12_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC12 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC12_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR13 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR13_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC13 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC13_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR14 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR14_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC14 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC14_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR15 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR15_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC15 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC15_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR16 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR16_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC16 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC16_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR17 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR17_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC17 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC17_HSEC_LEVEL_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_ADDR18 - CPU SYS Bus Access Sram Checker: Address of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_MASK (0xFFFFFFFFU)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_SHIFT (0U)
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/*! ADDR - Address of Violated Transfer */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_ADDR18_ADDR_MASK)
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/*! @} */
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/*! @name MEM_ACC_CHK_SYS_VIO_MISC18 - CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer */
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/*! @{ */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_MASK (0x1U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_SHIFT (0U)
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/*! WRITE - HWRITE of Violated Transfer. 1-Write; 0-Read */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_WRITE_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_MASK (0x2U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_SHIFT (1U)
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/*! HPROT0 - HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HPROT0_MASK)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_MASK (0xF0U)
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_SHIFT (4U)
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/*! HSEC_LEVEL - HSEC_LEVEL of Violated Transfer. */
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#define SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_SHIFT)) & SYSCTL2_MEM_ACC_CHK_SYS_VIO_MISC18_HSEC_LEVEL_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group SYSCTL2_Register_Masks */
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/*!
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* @}
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*/ /* end of group SYSCTL2_Peripheral_Access_Layer */
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/*
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** End of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#else
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#pragma pop
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#endif
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#elif defined(__GNUC__)
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/* leave anonymous unions enabled */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=default
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#else
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#error Not supported compiler type
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#endif
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/*!
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* @}
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*/ /* end of group Peripheral_access_layer */
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#endif /* SYSCTL2_H_ */
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