mirror of
https://github.com/cesanta/mongoose.git
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338 lines
14 KiB
C
338 lines
14 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for SYSPLL_TCPU
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file SYSPLL_TCPU.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for SYSPLL_TCPU
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*
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* CMSIS Peripheral Access Layer for SYSPLL_TCPU
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*/
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#if !defined(SYSPLL_TCPU_H_)
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#define SYSPLL_TCPU_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- SYSPLL_TCPU Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SYSPLL_TCPU_Peripheral_Access_Layer SYSPLL_TCPU Peripheral Access Layer
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* @{
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*/
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/** SYSPLL_TCPU - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[224];
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__I uint8_t SYSBYPASS_SOC_CTRL_ONE_RO_REG; /**< offset: 0xE0 */
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__I uint8_t SYSBYPASS_SOC_CTRL_TWO_RO_REG; /**< offset: 0xE1 */
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__I uint8_t SYSBYPASS_SOC_CTRL_THREE_RO_REG; /**< offset: 0xE2 */
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__I uint8_t REG_RO_REG; /**< offset: 0xE3 */
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__IO uint8_t SYS_CTRL_REG; /**< offset: 0xE4 */
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__IO uint8_t SYSBYPASS_SOC_CTRL_ONE_RW_REG; /**< offset: 0xE5 */
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__IO uint8_t SYSBYPASS_SOC_CTRL_TWO_RW_REG; /**< offset: 0xE6 */
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__IO uint8_t SYSBYPASS_SOC_CTRL_THREE_RW_REG; /**< offset: 0xE7 */
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__IO uint8_t TCPU_CTRL_ONE_REG; /**< offset: 0xE8 */
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__IO uint8_t TCPU_CTRL_TWO_REG; /**< offset: 0xE9 */
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__IO uint8_t TCPU_CTRL_THREE_REG; /**< offset: 0xEA */
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__IO uint8_t TCPU_CTRL_FOUR_REG; /**< offset: 0xEB */
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__IO uint8_t TCPU_CTRL_FIVE_REG; /**< offset: 0xEC */
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__IO uint8_t TCPU_CTRL_SIX_REG; /**< offset: 0xED */
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__IO uint8_t CLKTREE_CTRL_ONE_REG; /**< offset: 0xEE */
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__IO uint8_t CLKTREE_CTRL_TWO_REG; /**< offset: 0xEF */
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__IO uint8_t GPIO_CTRL_REG; /**< offset: 0xF0 */
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__IO uint8_t ATEST_CTRL_REG; /**< offset: 0xF1 */
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__IO uint8_t RESERVED_LO_REG; /**< offset: 0xF2 */
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__IO uint8_t RESERVED_HI_REG; /**< offset: 0xF3 */
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} SYSPLL_TCPU_Type;
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/* ----------------------------------------------------------------------------
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-- SYSPLL_TCPU Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SYSPLL_TCPU_Register_Masks SYSPLL_TCPU Register Masks
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* @{
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*/
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/*! @name SYSBYPASS_SOC_CTRL_ONE_RO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK (0xFFU)
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT (0U)
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/*! SYSBYPASS_SOC_CTRL_ONE_RO - SYSBYPASS_SOC_CTRL_ONE_RO */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RO_REG_SYSBYPASS_SOC_CTRL_ONE_RO_MASK)
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/*! @} */
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/*! @name SYSBYPASS_SOC_CTRL_TWO_RO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK (0xFFU)
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT (0U)
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/*! SYSBYPASS_SOC_CTRL_TWO_RO - SYSBYPASS_SOC_CTRL_TWO_RO */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RO_REG_SYSBYPASS_SOC_CTRL_TWO_RO_MASK)
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/*! @} */
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/*! @name SYSBYPASS_SOC_CTRL_THREE_RO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK (0xFFU)
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT (0U)
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/*! SYSBYPASS_SOC_CTRL_THREE_RO - SYSBYPASS_SOC_CTRL_THREE_RO */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RO_REG_SYSBYPASS_SOC_CTRL_THREE_RO_MASK)
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/*! @} */
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/*! @name REG_RO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_REG_RO_REG_REG_RO_MASK (0xFFU)
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#define SYSPLL_TCPU_REG_RO_REG_REG_RO_SHIFT (0U)
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/*! REG_RO - REG_RO */
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#define SYSPLL_TCPU_REG_RO_REG_REG_RO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_REG_RO_REG_REG_RO_SHIFT)) & SYSPLL_TCPU_REG_RO_REG_REG_RO_MASK)
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/*! @} */
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/*! @name SYS_CTRL_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_MASK (0xFFU)
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#define SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_SHIFT (0U)
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/*! SYS_CTRL - SYS_CTRL */
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#define SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_SHIFT)) & SYSPLL_TCPU_SYS_CTRL_REG_SYS_CTRL_MASK)
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/*! @} */
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/*! @name SYSBYPASS_SOC_CTRL_ONE_RW_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK (0xFFU)
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT (0U)
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/*! SYSBYPASS_SOC_CTRL_ONE_RW - SYSBYPASS_SOC_CTRL_ONE_RW */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_ONE_RW_REG_SYSBYPASS_SOC_CTRL_ONE_RW_MASK)
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/*! @} */
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/*! @name SYSBYPASS_SOC_CTRL_TWO_RW_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK (0xFFU)
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT (0U)
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/*! SYSBYPASS_SOC_CTRL_TWO_RW - SYSBYPASS_SOC_CTRL_TWO_RW */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_TWO_RW_REG_SYSBYPASS_SOC_CTRL_TWO_RW_MASK)
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/*! @} */
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/*! @name SYSBYPASS_SOC_CTRL_THREE_RW_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK (0xFFU)
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT (0U)
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/*! SYSBYPASS_SOC_CTRL_THREE_RW - SYSBYPASS_SOC_CTRL_THREE_RW */
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#define SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_SHIFT)) & SYSPLL_TCPU_SYSBYPASS_SOC_CTRL_THREE_RW_REG_SYSBYPASS_SOC_CTRL_THREE_RW_MASK)
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/*! @} */
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/*! @name TCPU_CTRL_ONE_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_MASK (0xFFU)
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#define SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_SHIFT (0U)
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/*! TCPU_CTRL_ONE - TCPU_CTRL_ONE */
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#define SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_ONE_REG_TCPU_CTRL_ONE_MASK)
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/*! @} */
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/*! @name TCPU_CTRL_TWO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_MASK (0xFFU)
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#define SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_SHIFT (0U)
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/*! TCPU_CTRL_TWO - TCPU_CTRL_TWO */
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#define SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_TWO_REG_TCPU_CTRL_TWO_MASK)
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/*! @} */
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/*! @name TCPU_CTRL_THREE_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_MASK (0xFFU)
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#define SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_SHIFT (0U)
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/*! TCPU_CTRL_THREE - TCPU_CTRL_THREE */
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#define SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_THREE_REG_TCPU_CTRL_THREE_MASK)
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/*! @} */
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/*! @name TCPU_CTRL_FOUR_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_MASK (0xFFU)
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#define SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_SHIFT (0U)
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/*! TCPU_CTRL_FOUR - TCPU_CTRL_FOUR */
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#define SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_FOUR_REG_TCPU_CTRL_FOUR_MASK)
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/*! @} */
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/*! @name TCPU_CTRL_FIVE_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_MASK (0xFFU)
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#define SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_SHIFT (0U)
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/*! TCPU_CTRL_FIVE - TCPU_CTRL_FIVE */
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#define SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_FIVE_REG_TCPU_CTRL_FIVE_MASK)
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/*! @} */
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/*! @name TCPU_CTRL_SIX_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_MASK (0xFFU)
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#define SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_SHIFT (0U)
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/*! TCPU_CTRL_SIX - TCPU_CTRL_SIX */
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#define SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_SHIFT)) & SYSPLL_TCPU_TCPU_CTRL_SIX_REG_TCPU_CTRL_SIX_MASK)
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/*! @} */
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/*! @name CLKTREE_CTRL_ONE_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_MASK (0xFFU)
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#define SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_SHIFT (0U)
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/*! CLKTREE_CTRL_ONE - CLKTREE_CTRL_ONE */
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#define SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_SHIFT)) & SYSPLL_TCPU_CLKTREE_CTRL_ONE_REG_CLKTREE_CTRL_ONE_MASK)
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/*! @} */
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/*! @name CLKTREE_CTRL_TWO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_MASK (0xFFU)
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#define SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_SHIFT (0U)
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/*! CLKTREE_CTRL_TWO - CLKTREE_CTRL_TWO */
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#define SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_SHIFT)) & SYSPLL_TCPU_CLKTREE_CTRL_TWO_REG_CLKTREE_CTRL_TWO_MASK)
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/*! @} */
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/*! @name GPIO_CTRL_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_MASK (0xFFU)
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#define SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_SHIFT (0U)
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/*! GPIO_CTRL - GPIO_CTRL */
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#define SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_SHIFT)) & SYSPLL_TCPU_GPIO_CTRL_REG_GPIO_CTRL_MASK)
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/*! @} */
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/*! @name ATEST_CTRL_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_MASK (0xFFU)
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#define SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_SHIFT (0U)
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/*! ATEST_CTRL - ATEST_CTRL */
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#define SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_SHIFT)) & SYSPLL_TCPU_ATEST_CTRL_REG_ATEST_CTRL_MASK)
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/*! @} */
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/*! @name RESERVED_LO_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_MASK (0xFFU)
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#define SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_SHIFT (0U)
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/*! RESERVED_LO - RESERVED_LO */
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#define SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_SHIFT)) & SYSPLL_TCPU_RESERVED_LO_REG_RESERVED_LO_MASK)
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/*! @} */
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/*! @name RESERVED_HI_REG - */
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/*! @{ */
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#define SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_MASK (0xFFU)
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#define SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_SHIFT (0U)
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/*! RESERVED_HI - RESERVED_HI */
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#define SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI(x) (((uint8_t)(((uint8_t)(x)) << SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_SHIFT)) & SYSPLL_TCPU_RESERVED_HI_REG_RESERVED_HI_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group SYSPLL_TCPU_Register_Masks */
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/*!
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* @}
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*/ /* end of group SYSPLL_TCPU_Peripheral_Access_Layer */
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/*
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** End of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#else
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#pragma pop
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#endif
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#elif defined(__GNUC__)
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/* leave anonymous unions enabled */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=default
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#else
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#error Not supported compiler type
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#endif
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/*!
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* @}
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*/ /* end of group Peripheral_access_layer */
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#endif /* SYSPLL_TCPU_H_ */
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