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mongoose/tutorials/nxp/frdm-rw612-xpresso-freertos-lwip/device/periph/PERI_TRNG.h
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/*
** ###################################################################
** Processors: RW610ETA2I
** RW610HNA2I
** RW610UKA2I
** RW612ETA2I
** RW612HNA2I
** RW612UKA2I
**
** Version: rev. 1.0, 2021-03-16
** Build: b240715
**
** Abstract:
** CMSIS Peripheral Access Layer for TRNG
**
** Copyright 1997-2016 Freescale Semiconductor, Inc.
** Copyright 2016-2024 NXP
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2021-03-16)
** Initial version.
**
** ###################################################################
*/
/*!
* @file TRNG.h
* @version 1.0
* @date 2021-03-16
* @brief CMSIS Peripheral Access Layer for TRNG
*
* CMSIS Peripheral Access Layer for TRNG
*/
#if !defined(TRNG_H_)
#define TRNG_H_ /**< Symbol preventing repeated inclusion */
#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
#include "RW610_COMMON.h"
#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
#include "RW612_COMMON.h"
#else
#error "No valid CPU defined!"
#endif
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#else
#pragma push
#pragma anon_unions
#endif
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- TRNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
* @{
*/
/** TRNG - Size of Registers Arrays */
#define TRNG_ENTA_COUNT 8u
/** TRNG - Register Layout Typedef */
typedef struct {
__IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */
__IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */
__I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */
union { /* offset: 0x18 */
__IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */
__I uint32_t OSC2_FRQCNT; /**< Oscillator-2 Frequency Count Register, offset: 0x18 */
};
union { /* offset: 0x1C */
__I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */
__IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */
};
union { /* offset: 0x20 */
__I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */
__IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */
};
union { /* offset: 0x24 */
__I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
__IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
};
union { /* offset: 0x28 */
__I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
__IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
};
union { /* offset: 0x2C */
__I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
__IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
};
uint8_t RESERVED_1[12];
__I uint32_t STATUS; /**< Status Register, offset: 0x3C */
__I uint32_t ENT[TRNG_ENTA_COUNT]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_2[64];
__IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */
__IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */
__IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */
__I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */
uint8_t RESERVED_3[60];
__IO uint32_t OSC2_CTL; /**< RNG Oscillator 2 Control Register, offset: 0xEC */
__I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */
__I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */
} TRNG_Type;
/* ----------------------------------------------------------------------------
-- TRNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Register_Masks TRNG Register Masks
* @{
*/
/*! @name MCTL - Miscellaneous Control Register */
/*! @{ */
#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
/*! OSC_DIV
* 0b00..use ring oscillator with no divide
* 0b01..use ring oscillator divided-by-2
* 0b10..use ring oscillator divided-by-4
* 0b11..use ring oscillator divided-by-8
*/
#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
#define TRNG_MCTL_UNUSED4_MASK (0x10U)
#define TRNG_MCTL_UNUSED4_SHIFT (4U)
#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
#define TRNG_MCTL_UNUSED5_MASK (0x20U)
#define TRNG_MCTL_UNUSED5_SHIFT (5U)
#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
#define TRNG_MCTL_RST_DEF_MASK (0x40U)
#define TRNG_MCTL_RST_DEF_SHIFT (6U)
#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
#define TRNG_MCTL_TST_OUT_MASK (0x800U)
#define TRNG_MCTL_TST_OUT_SHIFT (11U)
#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
#define TRNG_MCTL_ERR_MASK (0x1000U)
#define TRNG_MCTL_ERR_SHIFT (12U)
#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
#define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
#define TRNG_MCTL_OSC2_FAIL_MASK (0x8000U)
#define TRNG_MCTL_OSC2_FAIL_SHIFT (15U)
/*! OSC2_FAIL - Oscillator 2 Failure */
#define TRNG_MCTL_OSC2_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC2_FAIL_SHIFT)) & TRNG_MCTL_OSC2_FAIL_MASK)
#define TRNG_MCTL_PRGM_MASK (0x10000U)
#define TRNG_MCTL_PRGM_SHIFT (16U)
#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
/*! @} */
/*! @name SCMISC - Statistical Check Miscellaneous Register */
/*! @{ */
#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
/*! @} */
/*! @name SDCTL - Seed Control Register */
/*! @{ */
#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
/*! @} */
/*! @name TOTSAM - Total Samples Register */
/*! @{ */
#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
/*! @} */
/*! @name FRQMIN - Frequency Count Minimum Limit Register */
/*! @{ */
#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
/*! @} */
/*! @name OSC2_FRQCNT - Oscillator-2 Frequency Count Register */
/*! @{ */
#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK (0x3FFFFFU)
#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT (0U)
#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT)) & TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK)
/*! @} */
/*! @name FRQCNT - Frequency Count Register */
/*! @{ */
#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
/*! @} */
/*! @name FRQMAX - Frequency Count Maximum Limit Register */
/*! @{ */
#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
/*! @} */
/*! @name SCMC - Statistical Check Monobit Count Register */
/*! @{ */
#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
#define TRNG_SCMC_MONO_CT_SHIFT (0U)
#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
/*! @} */
/*! @name SCML - Statistical Check Monobit Limit Register */
/*! @{ */
#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
#define TRNG_SCML_MONO_MAX_SHIFT (0U)
#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
#define TRNG_SCML_MONO_RNG_SHIFT (16U)
#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
/*! @} */
/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
/*! @{ */
#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
/*! @} */
/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
/*! @{ */
#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
/*! @} */
/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
/*! @{ */
#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
/*! @} */
/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
/*! @{ */
#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
/*! @} */
/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
/*! @{ */
#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
/*! @} */
/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
/*! @{ */
#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
/*! @} */
/*! @name STATUS - Status Register */
/*! @{ */
#define TRNG_STATUS_TF1BR0_MASK (0x1U)
#define TRNG_STATUS_TF1BR0_SHIFT (0U)
#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
#define TRNG_STATUS_TF1BR1_MASK (0x2U)
#define TRNG_STATUS_TF1BR1_SHIFT (1U)
#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
#define TRNG_STATUS_TF2BR0_MASK (0x4U)
#define TRNG_STATUS_TF2BR0_SHIFT (2U)
#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
#define TRNG_STATUS_TF2BR1_MASK (0x8U)
#define TRNG_STATUS_TF2BR1_SHIFT (3U)
#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
#define TRNG_STATUS_TF3BR0_MASK (0x10U)
#define TRNG_STATUS_TF3BR0_SHIFT (4U)
#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
#define TRNG_STATUS_TF3BR1_MASK (0x20U)
#define TRNG_STATUS_TF3BR1_SHIFT (5U)
#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
#define TRNG_STATUS_TFLR_MASK (0x2000U)
#define TRNG_STATUS_TFLR_SHIFT (13U)
#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
#define TRNG_STATUS_TFMB_MASK (0x8000U)
#define TRNG_STATUS_TFMB_SHIFT (15U)
#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
/*! @} */
/*! @name ENT - Entropy Read Register */
/*! @{ */
#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
#define TRNG_ENT_ENT_SHIFT (0U)
#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
/*! @} */
/* The count of TRNG_ENT */
#define TRNG_ENT_COUNT (8U)
/*! @name SEC_CFG - Security Configuration Register */
/*! @{ */
#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
/*! NO_PRGM
* 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
* 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
*/
#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
/*! @} */
/*! @name INT_CTRL - Interrupt Control Register */
/*! @{ */
#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
/*! HW_ERR
* 0b0..Corresponding bit of INT_STATUS register cleared.
* 0b1..Corresponding bit of INT_STATUS register active.
*/
#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
/*! ENT_VAL
* 0b0..Same behavior as bit 0 of this register.
* 0b1..Same behavior as bit 0 of this register.
*/
#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
/*! FRQ_CT_FAIL
* 0b0..Same behavior as bit 0 of this register.
* 0b1..Same behavior as bit 0 of this register.
*/
#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
/*! @} */
/*! @name INT_MASK - Mask Register */
/*! @{ */
#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
/*! HW_ERR
* 0b0..Corresponding interrupt of INT_STATUS is masked.
* 0b1..Corresponding bit of INT_STATUS is active.
*/
#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
/*! ENT_VAL
* 0b0..Same behavior as bit 0 of this register.
* 0b1..Same behavior as bit 0 of this register.
*/
#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
/*! FRQ_CT_FAIL
* 0b0..Same behavior as bit 0 of this register.
* 0b1..Same behavior as bit 0 of this register.
*/
#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */
#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
/*! HW_ERR
* 0b0..no error
* 0b1..error detected.
*/
#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
/*! ENT_VAL
* 0b0..Busy generation entropy. Any value read is invalid.
* 0b1..TRNG can be stopped and entropy is valid if read.
*/
#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
/*! FRQ_CT_FAIL
* 0b0..No hardware nor self test frequency errors.
* 0b1..The frequency counter has detected a failure.
*/
#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
/*! @} */
/*! @name OSC2_CTL - RNG Oscillator 2 Control Register */
/*! @{ */
#define TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK (0x3U)
#define TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT (0U)
/*! TRNG_ENT_CTL - TRNG entropy generation control. */
#define TRNG_OSC2_CTL_TRNG_ENT_CTL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT)) & TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK)
#define TRNG_OSC2_CTL_OSC2_DIV_MASK (0xCU)
#define TRNG_OSC2_CTL_OSC2_DIV_SHIFT (2U)
/*! OSC2_DIV - Oscillator 2 divide control */
#define TRNG_OSC2_CTL_OSC2_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_DIV_SHIFT)) & TRNG_OSC2_CTL_OSC2_DIV_MASK)
#define TRNG_OSC2_CTL_OSC2_OUT_EN_MASK (0x10U)
#define TRNG_OSC2_CTL_OSC2_OUT_EN_SHIFT (4U)
/*! OSC2_OUT_EN - Oscillator 2 Output Enable. */
#define TRNG_OSC2_CTL_OSC2_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_OUT_EN_SHIFT)) & TRNG_OSC2_CTL_OSC2_OUT_EN_MASK)
#define TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK (0x200U)
#define TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT (9U)
/*! OSC2_FCT_VAL - TRNG Oscillator 2 Frequency Count Valid */
#define TRNG_OSC2_CTL_OSC2_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT)) & TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK)
#define TRNG_OSC2_CTL_OSC2_TST_OUT_MASK (0x800U)
#define TRNG_OSC2_CTL_OSC2_TST_OUT_SHIFT (11U)
/*! OSC2_TST_OUT - Test point inside ring oscillator 2. */
#define TRNG_OSC2_CTL_OSC2_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_TST_OUT_SHIFT)) & TRNG_OSC2_CTL_OSC2_TST_OUT_MASK)
#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK (0x3000U)
#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT (12U)
/*! OSC_FAILSAFE_LMT - Test point inside ring oscillator 2. */
#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK)
#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK (0x4000U)
#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT (14U)
/*! OSC_FAILSAFE_TEST - Test point inside ring oscillator 2. */
#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK)
/*! @} */
/*! @name VID1 - Version ID Register (MS) */
/*! @{ */
#define TRNG_VID1_MIN_REV_MASK (0xFFU)
#define TRNG_VID1_MIN_REV_SHIFT (0U)
/*! MIN_REV
* 0b00000100..Minor revision number for TRNG.
*/
#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
#define TRNG_VID1_MAJ_REV_SHIFT (8U)
/*! MAJ_REV
* 0b00010100..Major revision number for TRNG.
*/
#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
#define TRNG_VID1_IP_ID_SHIFT (16U)
/*! IP_ID
* 0b0000000000110000..ID for TRNG.
*/
#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
/*! @} */
/*! @name VID2 - Version ID Register (LS) */
/*! @{ */
#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
/*! CONFIG_OPT
* 0b00000000..TRNG_CONFIG_OPT for TRNG.
*/
#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
#define TRNG_VID2_ECO_REV_SHIFT (8U)
/*! ECO_REV
* 0b00000001..TRNG_ECO_REV for TRNG.
*/
#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
#define TRNG_VID2_INTG_OPT_SHIFT (16U)
/*! INTG_OPT
* 0b00001010..INTG_OPT for TRNG.
*/
#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
#define TRNG_VID2_ERA_MASK (0xFF000000U)
#define TRNG_VID2_ERA_SHIFT (24U)
/*! ERA
* 0b00001011..COMPILE_OPT for TRNG.
*/
#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group TRNG_Register_Masks */
/*!
* @}
*/ /* end of group TRNG_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#else
#pragma pop
#endif
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
#endif /* TRNG_H_ */
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