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277 lines
9.5 KiB
C
277 lines
9.5 KiB
C
/*
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* Copyright 2016-2021, 2023-2024 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FSL_CACHE_H_
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#define FSL_CACHE_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup cache64
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*! @{ */
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/*! @brief cache driver version. */
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#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 9))
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/*! @} */
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/*! @brief cache line size. */
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#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
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#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
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/*! @brief cache region number. */
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#define CACHE64_REGION_NUM (3U)
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/*! @brief cache region alignment. */
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#define CACHE64_REGION_ALIGNMENT (0x400U)
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/*! @brief Level 2 cache controller way size. */
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typedef enum _cache64_policy
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{
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kCACHE64_PolicyNonCacheable = 0, /*!< Non-cacheable */
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kCACHE64_PolicyWriteThrough = 1, /*!< Write through */
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kCACHE64_PolicyWriteBack = 2, /*!< Write back */
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} cache64_policy_t;
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/*! @brief CACHE64 configuration structure. */
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typedef struct _cache64_config
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{
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/*!< The cache controller can divide whole memory into 3 regions.
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* Boundary address is the FlexSPI internal address (start from 0) instead of system
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* address (start from FlexSPI AMBA base) to split adjacent regions and must be 1KB
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* aligned. The boundary address itself locates in upper region. */
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uint32_t boundaryAddr[CACHE64_REGION_NUM - 1];
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/*!< Cacheable policy for each region. */
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cache64_policy_t policy[CACHE64_REGION_NUM];
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} cache64_config_t;
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#endif
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name cache control for cache64
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*@{
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*/
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#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
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/*!
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* @brief Returns an instance number given peripheral base address.
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*
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* @param base The peripheral base address.
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* @return CACHE64_POLSEL instance number starting from 0.
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*/
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uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base);
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#endif
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/*!
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* brief Returns an instance number given physical memory address.
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*
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* param address The physical memory address.
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* @return CACHE64_CTRL instance number starting from 0.
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*/
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uint32_t CACHE64_GetInstanceByAddr(uint32_t address);
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#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
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/*!
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* @brief Initializes an CACHE64 instance with the user configuration structure.
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*
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* This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
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* to configure the configuration structure and get the default configuration.
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*
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* @param base CACHE64_POLSEL peripheral base address.
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* @param config Pointer to a user-defined configuration structure.
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* @retval kStatus_Success CACHE64 initialize succeed
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*/
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status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config);
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/*!
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* @brief Gets the default configuration structure.
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*
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* This function initializes the CACHE64 configuration structure to a default value. The default
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* values are first region covers whole cacheable area, and policy set to write back.
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*
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* @param config Pointer to a configuration structure.
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*/
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void CACHE64_GetDefaultConfig(cache64_config_t *config);
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#endif
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/*!
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* @brief Enables the cache.
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*
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* @param base CACHE64_CTRL peripheral base address.
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*
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*/
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void CACHE64_EnableCache(CACHE64_CTRL_Type *base);
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/*!
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* @brief Disables the cache.
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*
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* @param base CACHE64_CTRL peripheral base address.
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*
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*/
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void CACHE64_DisableCache(CACHE64_CTRL_Type *base);
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/*!
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* @brief Invalidates the cache.
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*
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* @param base CACHE64_CTRL peripheral base address.
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*
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*/
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void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
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/*!
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* @brief Invalidates cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be invalidated, should be larger than 0.
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* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
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* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans the cache.
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*
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* @param base CACHE64_CTRL peripheral base address.
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*
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*/
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void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
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/*!
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* @brief Cleans cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be cleaned, should be larger than 0.
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* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
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* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans and invalidates the cache.
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*
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* @param base CACHE64_CTRL peripheral base address.
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*
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*/
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void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
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/*!
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* @brief Cleans and invalidate cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
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* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
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* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
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#if !(defined(FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF) && FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF)
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/*!
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* @brief Enables/disables the write buffer.
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*
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* @param base CACHE64_CTRL peripheral base address.
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* @param enable The enable or disable flag.
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* true - enable the write buffer.
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* false - disable the write buffer.
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*/
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void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
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#endif
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/*! @} */
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/*!
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* @name Unified Cache Control for all caches
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*@{
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*/
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/*!
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* @brief Invalidates instruction cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be invalidated, should be larger than 0.
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* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
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* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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CACHE64_InvalidateCacheByRange(address, size_byte);
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}
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/*!
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* @brief Invalidates data cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be invalidated, should be larger than 0.
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* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
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* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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CACHE64_InvalidateCacheByRange(address, size_byte);
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}
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/*!
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* @brief Clean data cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be cleaned, should be larger than 0.
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* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
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* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
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{
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CACHE64_CleanCacheByRange(address, size_byte);
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}
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/*!
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* @brief Cleans and Invalidates data cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
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* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
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* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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CACHE64_CleanInvalidateCacheByRange(address, size_byte);
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}
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/*! @} */
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* FSL_CACHE_H_*/
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