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238 lines
11 KiB
C
238 lines
11 KiB
C
/*
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* Copyright 2021, 2023-2024 NXP
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_RESET_H_
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#define _FSL_RESET_H_
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "fsl_device_registers.h"
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/*!
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* @addtogroup reset
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief reset driver version 2.1.1. */
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#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
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/*@}*/
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/*!
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* @brief Reset control registers index
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*/
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#define RST_CTL0_PSCCTL0 0
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#define RST_CTL0_PSCCTL1 1
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#define RST_CTL0_PSCCTL2 2
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#define RST_CTL1_PSCCTL0 3
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#define RST_CTL1_PSCCTL1 4
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#define RST_CTL1_PSCCTL2 5
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/*!
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* @brief Enumeration for peripheral reset control bits
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*
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* Defines the enumeration for peripheral reset control bits in RSTCLTx registers
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*/
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typedef enum _RSTCTL_RSTn
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{
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kPOWERQUAD_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 8U, /**< POWERQUAD reset control */
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kPKC_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 9U, /**< PKC reset control */
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kELS_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 10U, /**< ELS reset control */
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kPUF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 11U, /**< Physical unclonable function reset control */
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kFLEXSPI_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 16U, /**< FLEXSPI reset control */
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kHPU_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 20U, /**< HPU reset control */
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kUSB_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 22U, /**< USB reset control */
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kSCT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 24U, /**< Standard ctimers reset control */
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kAON_MEM_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 25U, /**< AON MEM reset control */
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kGDMA_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 28U, /**< GDMA reset control */
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kDMA0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 29U, /**< DMA0 reset control */
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kDMA1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 30U, /**< DMA1 reset control */
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kSDIO_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 31U, /**< SDIO reset control */
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kELS_APB_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 0U, /**< ELS_APB reset control */
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kELS_GDET_REF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 1U, /**< ELS_GDET_REF_RST reset control */
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kSDIO_SLV_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO_SLV reset control */
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kGAU_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< GAU reset control */
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kOTP_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 17U, /**< OTP reset control */
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kSECURE_GPIO_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security GPIO reset control */
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kENET_IPG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 25U, /**< ENET_IPG reset control */
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kENET_IPG_S_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 26U, /**< ENET_IPG_S reset control */
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kTRNG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 27U, /**< TRNG reset control */
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kUTICK_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 0U, /**< Micro-tick timer reset control */
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kWWDT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 1U, /**< Windowed Watchdog timer reset control */
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kUSIM_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 2U, /**< USIM reset control */
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kFREEMRT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 26U, /**< FREEMRT reset control */
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kLCDIC_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 27U, /**< LCDIC reset control */
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kFC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 8U, /**< Flexcomm Interface 0 reset control */
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kFC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 9U, /**< Flexcomm Interface 1 reset control */
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kFC2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 10U, /**< Flexcomm Interface 2 reset control */
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kFC3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 11U, /**< Flexcomm Interface 3 reset control */
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kFC14_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 22U, /**< Flexcomm Interface 14 reset control */
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kDMIC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 24U, /**< Digital microphone interface reset control */
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kOSEVENT_TIMER_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 27U, /**< Osevent Timer reset control */
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kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
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kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
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kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
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kFREQME_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 31U, /**< Frequency Measure reset control */
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kCT32B0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 0U, /**< CT32B0 reset control */
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kCT32B1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 1U, /**< CT32B1 reset control */
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kCT32B2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 2U, /**< CT32B3 reset control */
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kCT32B3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 3U, /**< CT32B4 reset control */
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kCT32B4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 4U, /**< CT32B4 reset control */
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kMRT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 8U, /**< Multi-rate timer (MRT) reset control */
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kPINT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 30U, /**< GPIO_INT reset control */
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kINPUTMUX_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 31U, /**< PMUX reset control */
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} RSTCTL_RSTn_t;
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/** Array initializers with peripheral reset bits **/
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#define CRC_RSTS \
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{ \
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kCRC_RST_SHIFT_RSTn \
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} /* Reset bits for CRC peripheral */
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#define DMA_RSTS_N \
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{ \
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kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
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} /* Reset bits for DMA peripheral */
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#define DMIC_RSTS \
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{ \
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kDMIC_RST_SHIFT_RSTn \
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} /* Reset bits for ADC peripheral */
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#define FLEXCOMM_RSTS \
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{ \
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kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC14_RST_SHIFT_RSTn \
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} /* Reset bits for FLEXCOMM peripheral */
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#define GPIO_RSTS_N \
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{ \
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kHSGPIO0_RST_SHIFT_RSTn, kHSGPIO1_RST_SHIFT_RSTn \
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} /* Reset bits for GPIO peripheral */
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#define MRT_RSTS \
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{ \
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kMRT_RST_SHIFT_RSTn, kFREEMRT_RST_SHIFT_RSTn \
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} /* Reset bits for MRT peripheral */
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#define PINT_RSTS \
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{ \
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kPINT_RST_SHIFT_RSTn \
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} /* Reset bits for PINT peripheral */
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#define SCT_RSTS \
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{ \
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kSCT_RST_SHIFT_RSTn \
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} /* Reset bits for SCT peripheral */
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#define CTIMER_RSTS \
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{ \
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kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
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kCT32B4_RST_SHIFT_RSTn \
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} /* Reset bits for TIMER peripheral */
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#define USB_RSTS \
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{ \
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kUSB_RST_SHIFT_RSTn \
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} /* Reset bits for USB peripheral */
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#define UTICK_RSTS \
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{ \
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kUTICK_RST_SHIFT_RSTn \
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} /* Reset bits for UTICK peripheral */
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#define WWDT_RSTS \
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{ \
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kWWDT_RST_SHIFT_RSTn \
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} /* Reset bits for WWDT peripheral */
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#define OSTIMER_RSTS \
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{ \
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kOSEVENT_TIMER_RST_SHIFT_RSTn \
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} /* Reset bits for OSTIMER peripheral */
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#define POWERQUAD_RSTS \
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{ \
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kPOWERQUAD_RST_SHIFT_RSTn \
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} /* Reset bits for Powerquad peripheral */
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#define PUF_RSTS \
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{ \
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kPUF_RST_SHIFT_RSTn \
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} /* Reset bits for PUF peripheral */
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#define TRNG_RSTS \
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{ \
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kTRNG_RST_SHIFT_RSTn \
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} /* Reset bits for TRNG peripheral */
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#define USIM_RSTS \
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{ \
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kUSIM_RST_SHIFT_RSTn \
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} /* Reset bits for USIM peripheral */
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#define ENET_RSTS \
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{ \
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kENET_IPG_RST_SHIFT_RSTn, kENET_IPG_S_RST_SHIFT_RSTn \
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} /* Reset bits for ENET peripheral */
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/*!
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* @brief IP reset handle
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*/
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typedef RSTCTL_RSTn_t reset_ip_name_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Assert reset to peripheral.
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*
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* Asserts reset signal to specified peripheral module.
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*
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* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Clear reset to peripheral.
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*
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* Clears reset signal to specified peripheral module, allows it to operate.
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*
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* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Reset peripheral module.
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*
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* Reset peripheral module.
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*
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* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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void RESET_PeripheralReset(reset_ip_name_t peripheral);
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/*!
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* @brief Release peripheral module.
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*
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* Release peripheral module.
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*
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* @param peripheral Peripheral to release. The enum argument contains encoding of reset register
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* and reset bit position in the reset register.
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*/
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static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
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{
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RESET_ClearPeripheralReset(peripheral);
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}
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#if defined(__cplusplus)
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}
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#endif
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/*! @} */
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#endif /* _FSL_RESET_H_ */
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