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19 lines
603 B
C
19 lines
603 B
C
#pragma once
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struct mg_tcpip_driver_imxrt_data {
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// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
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// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
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// 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1))
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// ipg_clk mdc_cr VALUE
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// --------------------------
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// -1 <-- TODO() tell driver to guess the value
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// 25 MHz 4
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// 33 MHz 6
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// 40 MHz 7
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// 50 MHz 9
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// 66 MHz 13
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int mdc_cr; // Valid values: -1 to 63
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uint8_t phy_addr; // PHY address
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};
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