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48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32F) && \
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MG_ENABLE_DRIVER_STM32F
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struct mg_tcpip_driver_stm32f_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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// HCLK range DIVIDER mdc_cr VALUE
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// -------------------------------------
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// -1 <-- tell driver to guess the value
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// 60-100 MHz HCLK/42 0
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// 100-150 MHz HCLK/62 1
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// 20-35 MHz HCLK/16 2
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// 35-60 MHz HCLK/26 3
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// 150-216 MHz HCLK/102 4 <-- value for Nucleo-F* on max speed
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// 216-310 MHz HCLK/124 5
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// 110, 111 Reserved
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int mdc_cr; // Valid values: -1, 0, 1, 2, 3, 4, 5
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uint8_t phy_addr; // PHY address
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};
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#ifndef MG_TCPIP_PHY_ADDR
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#define MG_TCPIP_PHY_ADDR 0
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 4
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#endif
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#define MG_TCPIP_DRIVER_INIT(mgr) \
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do { \
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static struct mg_tcpip_driver_stm32f_data driver_data_; \
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static struct mg_tcpip_if mif_; \
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driver_data_.mdc_cr = MG_DRIVER_MDC_CR; \
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driver_data_.phy_addr = MG_TCPIP_PHY_ADDR; \
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mif_.ip = MG_TCPIP_IP; \
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mif_.mask = MG_TCPIP_MASK; \
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mif_.gw = MG_TCPIP_GW; \
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mif_.driver = &mg_tcpip_driver_stm32f; \
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mif_.driver_data = &driver_data_; \
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MG_SET_MAC_ADDRESS(mif_.mac); \
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mg_tcpip_init(mgr, &mif_); \
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MG_INFO(("Driver: stm32f, MAC: %M", mg_print_mac, mif_.mac)); \
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} while (0)
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#endif
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