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https://github.com/cesanta/mongoose.git
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323 lines
11 KiB
C
323 lines
11 KiB
C
// Copyright (c) 2026 Cesanta Software Limited
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// All rights reserved
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//
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// RM0456
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// https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf
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// https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf
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#pragma once
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#define LED_1 PIN('C', 7) // On-board LED pin (green)
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#define LED_2 PIN('B', 7) // On-board LED pin (blue)
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#define LED_3 PIN('G', 2) // On-board LED pin (red)
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#define LED LED_1 // Use green LED for blinking
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#define SPI_RDY PIN('E', 13)
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#define SPI_CS PIN('D', 14)
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#define SPI_CHIP_EN PIN('E', 11)
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#ifndef HAL_DEBUG_UART
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#define HAL_DEBUG_UART USART1
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#endif
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#ifndef UART_DEBUG
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#define UART_DEBUG HAL_DEBUG_UART
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#endif
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#ifndef WIFISPI
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#define WIFISPI SPI1
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#endif
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#include <stm32u5a5xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
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extern uint64_t hal_get_tick(void);
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extern size_t hal_ram_free(void);
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extern size_t hal_ram_used(void);
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extern uint32_t SystemCoreClock;
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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enum {
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HAL_D1PRE = 1, // actual divisor value
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HAL_HPRE = 1, // actual divisor value
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HAL_D2PRE = 1,
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HAL_D3PRE = 1,
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};
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enum { PLL1_M = 1, PLL1_N = 80, PLL1_P = 2, PLL1_Q = 2, PLL1_R = 2 };
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#define MSIS_FREQUENCY (4 * 1024 * 1024) // 4 Mhz
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#define SYS_FREQUENCY (MSIS_FREQUENCY * PLL1_N / PLL1_M / PLL1_P / HAL_D1PRE) // 160MHz
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#define AHB_FREQUENCY (SYS_FREQUENCY / HAL_HPRE)
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#define APB2_FREQUENCY (AHB_FREQUENCY / HAL_D2PRE)
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#define APB1_FREQUENCY (AHB_FREQUENCY / HAL_D1PRE)
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static inline void spin(volatile uint32_t n) {
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while (n--)
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(void)0;
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}
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enum {
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HAL_GPIO_MODE_INPUT,
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HAL_GPIO_MODE_OUTPUT,
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HAL_GPIO_MODE_AF,
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HAL_GPIO_MODE_ANALOG
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};
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enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
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enum {
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HAL_GPIO_SPEED_LOW,
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HAL_GPIO_SPEED_MEDIUM,
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HAL_GPIO_SPEED_HIGH,
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HAL_GPIO_SPEED_INSANE
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};
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enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
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#define HAL_GPIO(N) ((GPIO_TypeDef *)(GPIOA_BASE_NS + 0x400 * (N)))
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static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
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return HAL_GPIO(PINBANK(pin));
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}
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static inline void hal_gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int hal_gpio_read(uint16_t pin) {
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return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void hal_gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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uint8_t n = (uint8_t)(PINNO(pin));
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RCC->AHB2ENR1 |= BIT(PINBANK(pin)); // Enable GPIO clock
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CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t)type) << n);
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CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t)speed) << (n * 2));
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CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t)pull) << (n * 2));
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CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t)af) << ((n & 7) * 4));
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CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t)mode) << (n * 2));
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}
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static inline void hal_gpio_input(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_HIGH, HAL_GPIO_PULL_NONE, 0);
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}
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static inline void hal_gpio_output(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_HIGH, HAL_GPIO_PULL_NONE, 0);
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}
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// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
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// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
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// must be enabled for CPU access, as the kernel clock drives the BRR, not the
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// APB bus interface
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static inline void hal_uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq =
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SYS_FREQUENCY; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1)
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freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(14);
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if (uart == USART2)
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freq = APB1_FREQUENCY, RCC->APB1ENR1 |= BIT(17);
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if (uart == USART3)
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freq = APB1_FREQUENCY, RCC->APB1ENR1 |= BIT(18);
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if (uart == USART1)
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tx = PIN('A', 9), rx = PIN('A', 10);
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if (uart == USART2)
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tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == USART3)
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tx = PIN('D', 8), rx = PIN('D', 9);
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#if 0 // CONSTANT BAUD RATE FOR DEBUGGING
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CLRSET(RCC->CCIPR2, 7 << 3, 3 << 3); // use HSI for UART1
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freq = 64000000;
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#endif
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hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_HIGH, 0, af);
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hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0)
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spin(1);
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}
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static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf,
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size_t len) {
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while (len-- > 0)
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hal_uart_write_byte(uart, *(uint8_t *)buf++);
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}
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static inline int hal_uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t)(uart->RDR & 255);
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}
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static inline void hal_rng_init(void) {
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RCC->CCIPR2 |= RCC_CCIPR2_RNGSEL_0; // RNG clock source pll1_q_ck
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RCC->AHB2ENR1 |= RCC_AHB2ENR1_RNGEN; // Enable RNG clock
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RNG->CR = RNG_CR_RNGEN; // Enable RNG
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}
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static inline uint32_t hal_rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0)
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(void)0;
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return RNG->DR;
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}
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#define MG_HAL_DISABLE_ETHERNET 1
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static inline unsigned int hal_ahb_div2prescval(unsigned int div) {
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if (div == 1)
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return 0;
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unsigned int val = 7;
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while (div >>= 1)
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++val;
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return val;
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}
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static inline unsigned int hal_apb_div2prescval(unsigned int div) {
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if (div <= 1)
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return 0;
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unsigned int val = 0;
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while (div >>= 1)
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++val;
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return val + 2;
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}
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static inline void hal_clock_init(void) {
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FLASH->ACR |= BIT(8); // prefetch
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RCC->AHB3ENR |= RCC_AHB3ENR_PWREN;
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PWR->SVMCR |= PWR_SVMCR_IO2SV; // Enable VDDIO2 supply
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PWR->UCPDR |= PWR_UCPDR_UCPD_DBDIS; // Disable the internal Pull-Up in Dead
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// Battery pins of UCPD peripheral
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PWR->CR3 |= PWR_CR3_REGSEL; // enable SMPS
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while ((PWR->SVMSR & BIT(1)) == 0)
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spin(1);
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if ((PWR->SVMSR & PWR_SVMSR_ACTVOS) != (PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1)) {
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// control voltage scaling
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PWR->VOSR |= PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1 | PWR_VOSR_BOOSTEN;
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while ((PWR->VOSR & PWR_VOSR_VOSRDY) == 0)
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spin(1);
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while ((PWR->SVMSR & PWR_SVMSR_ACTVOSRDY) == 0)
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spin(1);
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}
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PWR->DBPR |= PWR_DBPR_DBP; // enable backup access
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CLRSET(RCC->BDCR, 3 << 3, 0); // RCC_LSEDRIVE_LOW
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RCC->BDCR |= RCC_BDCR_LSEON; // LSE enable
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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spin(1);
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RCC->BDCR |= RCC_BDCR_LSESYSEN; // LSESYS enable
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while ((RCC->BDCR & RCC_BDCR_LSESYSRDY) == 0)
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spin(1);
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PWR->VOSR &= ~PWR_VOSR_BOOSTEN;
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RCC->CR &= ~BIT(24); // configure PLL1
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while ((RCC->CR & RCC_CR_PLL1RDY) != 0)
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spin(1);
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RCC->PLL1CFGR = BIT(0) | ((PLL1_M - 1) << 8) | BIT(16) | BIT(17) |
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BIT(18); // source, PLL1_M, enable PLL1_P, PLL1_Q
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RCC->PLL1DIVR = (PLL1_N - 1) | ((PLL1_P - 1) << 9) | ((PLL1_Q - 1) << 16) |
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((PLL1_R - 1) << 24);
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PWR->VOSR |= PWR_VOSR_BOOSTEN;
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RCC->CR |= BIT(24); // PLL1ON
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while ((RCC->CR & RCC_CR_PLL1RDY) == 0)
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spin(1);
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CLRSET(FLASH->ACR, 0xf, 4); // flash latency 4
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RCC->CFGR1 |= 3; // set PLL as sysclk source
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CLRSET(RCC->CFGR2, 0xf, hal_ahb_div2prescval(HAL_HPRE)); // HPRE
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CLRSET(RCC->CFGR2, 0x70, hal_apb_div2prescval(HAL_D1PRE) << 4); // D1PRE
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CLRSET(RCC->CFGR2, 0x700, hal_apb_div2prescval(HAL_D2PRE) << 8); // D2PRE
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CLRSET(RCC->CFGR3, 0x70, hal_apb_div2prescval(HAL_D3PRE) << 4); // D3PRE
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}
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static inline void hal_system_init(void) {
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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__DSB();
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__ISB();
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SCB->VTOR = FLASH_BASE; // Vector Table Relocation in Internal FLASH
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}
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static inline void hal_spi_init(SPI_TypeDef *spi, uint16_t div) {
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(void)spi;
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uint32_t br = 0; // Baud rate prescaler: div = 2,4,8...256 -> MBR = 0..7
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while (div > 2)
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div >>= 1, br++;
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if (br > 7)
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br = 7;
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CLRSET(RCC->CCIPR1, 3 << 20, 1); // SYSCLK source
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RCC->APB2ENR |= BIT(12); // SPI1EN
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spin(100);
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hal_gpio_init(PIN('A', 5), HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_INSANE, HAL_GPIO_PULL_DOWN, 5); // SCK
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hal_gpio_init(PIN('A', 6), HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_INSANE, HAL_GPIO_PULL_NONE, 5); // MISO
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hal_gpio_init(PIN('A', 7), HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL,
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HAL_GPIO_SPEED_INSANE, HAL_GPIO_PULL_NONE, 5); // MOSI
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hal_gpio_output(SPI_CS); // CS
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hal_gpio_output(SPI_CHIP_EN); // CHIP_EN
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hal_gpio_input(SPI_RDY); // RDY
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spi->CR1 = 0; // disable SPI
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spi->CR1 = SPI_CR1_SSI_Msk; // SSI
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spi->CFG1 = (7 << SPI_CFG1_DSIZE_Pos) | (br << SPI_CFG1_MBR_Pos); // DSIZE = 8-bit, MBR
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spi->CFG2 = SPI_CFG2_SSM_Msk | SPI_CFG2_MASTER_Msk;
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spi->CR1 |= SPI_CR1_SPE_Msk; // Enable SPI
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spi->CR1 |= SPI_CR1_CSTART_Msk; // Start transfer
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}
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static inline uint8_t hal_spi_xfer_byte(SPI_TypeDef *spi, uint8_t byte) {
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(void)spi;
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while ((spi->SR & SPI_SR_TXP_Msk) == 0)
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spin(1); // TXP
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*(volatile uint8_t *) &spi->TXDR = byte;
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while (((spi->SR & SPI_SR_RXP_Msk) == 0) && ((spi->SR & SPI_SR_RXWNE_Msk) == 0) && ((spi->SR & SPI_SR_RXPLVL_Msk) == 0))
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spin(1); // RXP
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uint8_t rx = *(volatile uint8_t *) &spi->RXDR;
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return rx;
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}
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static inline void hal_spi_tx_rx(SPI_TypeDef *spi, uint8_t *tx, uint8_t *rx, size_t len) {
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for (size_t i = 0; i < len; i++) {
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uint8_t rx_ = hal_spi_xfer_byte(spi, tx ? tx[i] : 0);
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if (rx) rx[i] = rx_;
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}
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}
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static inline bool hal_spi_ready(SPI_TypeDef *spi) {
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(void) spi;
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return hal_gpio_read(SPI_RDY);
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}
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static inline void hal_spi_select(SPI_TypeDef *spi, bool s) {
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(void)spi;
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hal_gpio_write(SPI_CS, s);
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}
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static inline void hal_spi_done(SPI_TypeDef *spi) {
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while((spi->SR & SPI_SR_TXC_Msk) == 0) spin(1);
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spi->IFCR = 0xffff; // clear all flags
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}
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