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https://github.com/cesanta/mongoose.git
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251 lines
9.9 KiB
C
251 lines
9.9 KiB
C
#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && \
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MG_ENABLE_DRIVER_SAME54
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struct GMAC_REGS_ {
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uint32_t GMAC_NCR, GMAC_NCFGR, GMAC_NSR, GMAC_UR, GMAC_DCFGR, GMAC_TSR,
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GMAC_RBQB, GMAC_TBQB, GMAC_RSR, GMAC_ISR, GMAC_IER, GMAC_IDR, GMAC_IMR,
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GMAC_MAN, GMAC_RPQ, GMAC_TPQ, GMAC_TPSF, GMAC_RPSF, GMAC_RJFML,
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Reserved1[13], GMAC_HRB, GMAC_HRT, GMAC_SAB0, GMAC_SAT0, GMAC_SAB1,
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GMAC_SAT1, GMAC_SAB2, GMAC_SAT2, GMAC_SAB3, GMAC_SAT3, GMAC_TIDM[4],
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GMAC_WOL, GMAC_IPGS, GMAC_SVLAN, GMAC_TPFCP, GMAC_SAMB1, GMAC_SAMT1,
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Reserved2[3], GMAC_NSC, GMAC_SCL, GMAC_SCH, GMAC_EFTSH, GMAC_EFRSH,
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GMAC_PEFTSH, GMAC_PEFRSH, Reserved3[2], GMAC_OTLO, GMAC_OTHI, GMAC_FT,
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GMAC_BCFT, GMAC_MFT, GMAC_PFT, GMAC_BFT64, GMAC_TBFT127, GMAC_TBFT255,
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GMAC_TBFT511, GMAC_TBFT1023, GMAC_TBFT1518, GMAC_GTBFT1518, GMAC_TUR,
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GMAC_SCF, GMAC_MCF, GMAC_EC, GMAC_LC, GMAC_DTF, GMAC_CSE, GMAC_ORLO,
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GMAC_ORHI, GMAC_FR, GMAC_BCFR, GMAC_MFR, GMAC_PFR, GMAC_BFR64,
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GMAC_TBFR127, GMAC_TBFR255, GMAC_TBFR511, GMAC_TBFR1023, GMAC_TBFR1518,
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GMAC_TMXBFR, GMAC_UFR, GMAC_OFR, GMAC_JR, GMAC_FCSE, GMAC_LFFE, GMAC_RSE,
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GMAC_AE, GMAC_RRE, GMAC_ROE, GMAC_IHCE, GMAC_TCE, GMAC_UCE, Reserved4[2],
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GMAC_TISUBN, GMAC_TSH, Reserved5, GMAC_TSSSL, GMAC_TSSN, GMAC_TSL,
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GMAC_TN, GMAC_TA, GMAC_TI, GMAC_EFTSL, GMAC_EFTN, GMAC_EFRSL, GMAC_EFRN,
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GMAC_PEFTSL, GMAC_PEFTN, GMAC_PEFRSL, GMAC_PEFRN, Reserved6[28],
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GMAC_RLPITR, GMAC_RLPITI, GMAC_TLPITR, GMAC_TLPITI;
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};
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struct GCLK_REGS_ {
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uint32_t GCLK_CTRLA_RESERVED, GCLK_SYNCBUSY, Reserved2[6], GCLK_GENCTRL[12],
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Reserved3[12], GCLK_PCHCTRL[48];
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};
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#define GMAC_REGS ((struct GMAC_REGS_ *) 0x42000800)
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#define GCLK_REGS ((struct GCLK_REGS_ *) 0x40001c00)
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#define ETH_PKT_SIZE 1536 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 2 // Descriptor size (words)
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_txno; // Current TX descriptor
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static uint8_t s_rxno; // Current RX descriptor
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static struct mg_tcpip_if *s_ifp; // MIP interface
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static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
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GMAC_REGS->GMAC_MAN = MG_BIT(30) | // Clause 22
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MG_BIT(29) | // Setting the read operation
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MG_BIT(17) | ((addr & 0x1f) << 23) | // PHY address
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((reg & 0x1f) << 18); // Setting the register
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while (!(GMAC_REGS->GMAC_NSR & MG_BIT(2))) (void) 0;
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return GMAC_REGS->GMAC_MAN & 0xffff; // Getting the read value
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint16_t val) {
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GMAC_REGS->GMAC_MAN = MG_BIT(30) |
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MG_BIT(28) | // Setting the write operation
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MG_BIT(17) | ((addr & 0x1f) << 23) | // PHY address
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((reg & 0x1f) << 18) | val; // Setting the register
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while (!(GMAC_REGS->GMAC_NSR & MG_BIT(2)))
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; // Waiting until the write op is complete
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}
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uint32_t get_clock_rate(struct mg_tcpip_driver_same54_data *d) {
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if (d && d->mdc_cr >= 0 && d->mdc_cr <= 5) {
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return d->mdc_cr;
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} else {
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// get MCLK from GCLK_GENERATOR 0
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uint32_t div = 512;
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uint32_t mclk;
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if (!(GCLK_REGS->GCLK_GENCTRL[0] & MG_BIT(12))) {
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div = ((GCLK_REGS->GCLK_GENCTRL[0] & 0x00FF0000) >> 16);
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if (div == 0) div = 1;
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}
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switch (GCLK_REGS->GCLK_GENCTRL[0] & 0xF) {
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case 0: // GCLK_GENCTRL_SRC_XOSC0_Val
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mclk = 32000000UL; // 32MHz
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break;
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case 1: // GCLK_GENCTRL_SRC_XOSC1_Val
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mclk = 32000000UL; // 32MHz
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break;
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case 4: // GCLK_GENCTRL_SRC_OSCULP32K_Val
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mclk = 32000UL; // 32Khz
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break;
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case 5: // GCLK_GENCTRL_SRC_XOSC32K_Val
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mclk = 32000UL; // 32Khz
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break;
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case 6: // GCLK_GENCTRL_SRC_DFLL_Val
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mclk = 48000000UL; // 48MHz
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break;
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case 7: // GCLK_GENCTRL_SRC_DPLL0_Val:
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mclk = 200000000UL; // 200MHz
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break;
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case 8: // GCLK_GENCTRL_SRC_DPLL1_Val
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mclk = 200000000UL; // 200MHz
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break;
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default:
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mclk = 200000000UL; // 200MHz
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}
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mclk /= div;
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uint8_t crs[] = {0, 1, 2, 3, 4, 5}; // GMAC->NCFGR::CLK values
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uint8_t dividers[] = {8, 16, 32, 48, 64, 96}; // Respective CLK dividers
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for (int i = 0; i < 6; i++) {
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if (mclk / dividers[i] <= 2375000UL) { // 2.5MHz - 5%
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return crs[i];
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}
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}
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return 5;
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}
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}
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static bool mg_tcpip_driver_same54_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_same54_data *d =
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(struct mg_tcpip_driver_same54_data *) ifp->driver_data;
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s_ifp = ifp;
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GMAC_REGS->GMAC_NCFGR = get_clock_rate(d) << 18; // Set MDC divider
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GMAC_REGS->GMAC_NCR = 0; // Disable RX & TX
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GMAC_REGS->GMAC_NCR |= MG_BIT(4); // Enable MDC & MDIO
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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mg_phy_init(&phy, d->phy_addr, 0);
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init TX descriptors
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s_txdesc[i][0] = (uint32_t) s_txbuf[i]; // Point to data buffer
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s_txdesc[i][1] = MG_BIT(31); // OWN bit
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}
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s_txdesc[ETH_DESC_CNT - 1][1] |= MG_BIT(30); // Last tx descriptor - wrap
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GMAC_REGS->GMAC_DCFGR = (0x18 << 16) | // DMA recv buf 1536
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(3 << 8) | // RXBMS
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MG_BIT(10); // See #2487
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init RX descriptors
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s_rxdesc[i][0] = (uint32_t) s_rxbuf[i]; // Address of the data buffer
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s_rxdesc[i][1] = 0; // Clear status
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}
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s_rxdesc[ETH_DESC_CNT - 1][0] |= MG_BIT(1); // Last rx descriptor - wrap
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GMAC_REGS->GMAC_TBQB = (uint32_t) s_txdesc; // about the descriptor addresses
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GMAC_REGS->GMAC_RBQB = (uint32_t) s_rxdesc; // Let the controller know
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GMAC_REGS->GMAC_SAB0 =
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MG_U32(ifp->mac[3], ifp->mac[2], ifp->mac[1], ifp->mac[0]);
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GMAC_REGS->GMAC_SAT0 = MG_U32(0, 0, ifp->mac[5], ifp->mac[4]);
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GMAC_REGS->GMAC_UR &= ~MG_BIT(0); // Disable MII, use RMII
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GMAC_REGS->GMAC_NCFGR |= MG_BIT(8) | MG_BIT(6) | // MAXFX, MTIHEN
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MG_BIT(25) | MG_BIT(4); // EFRHD, CAF
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GMAC_REGS->GMAC_TSR = 0x17f; // all transmit statuses
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GMAC_REGS->GMAC_RSR = 0xf; // all recv statuses
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GMAC_REGS->GMAC_IDR = ~0U; // Disable interrupts, then enable required
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GMAC_REGS->GMAC_IER = MG_BIT(11) | MG_BIT(10) | // HRESP, ROVR
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MG_BIT(7) | MG_BIT(6) | // TCOMP, TFC
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MG_BIT(5) | MG_BIT(4) | // RLEX, TUR
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MG_BIT(2) | MG_BIT(1); // RXUBR, RCOMP
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GMAC_REGS->GMAC_NCR |= MG_BIT(3) | MG_BIT(2); // TXEN, RXEN
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return true;
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}
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static size_t mg_tcpip_driver_same54_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[s_txno])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][1] & MG_BIT(31)) == 0) {
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ifp->nerr++;
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MG_ERROR(("No free descriptors"));
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len = 0; // All descriptors are busy, fail
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} else {
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uint32_t status = len | MG_BIT(15); // Frame length, last chunk
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if (s_txno == ETH_DESC_CNT - 1) status |= MG_BIT(30); // wrap
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = status;
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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MG_DSB(); // Ensure descriptors have been written
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GMAC_REGS->GMAC_NCR |= MG_BIT(9); // Enable transmission
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return len;
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}
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static void mg_tcpip_driver_same54_update_hash_table(struct mg_tcpip_if *ifp) {
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// TODO(): read database, rebuild hash table
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// Setting Hash Index for 01:00:5e:00:00:fb (multicast)
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// 24.6.9 Hash addressing
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// computed hash is 55, which means bit 23 (55 - 32) in
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// HRT register must be set
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GMAC_REGS->GMAC_HRT = MG_BIT(23);
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GMAC_REGS->GMAC_NCFGR |= MG_BIT(6); // enable multicast hash filtering
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(void) ifp;
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}
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static bool mg_tcpip_driver_same54_poll(struct mg_tcpip_if *ifp, bool s1) {
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if (ifp->update_mac_hash_table) {
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mg_tcpip_driver_same54_update_hash_table(ifp);
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ifp->update_mac_hash_table = false;
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}
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bool up = false;
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if (s1) {
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uint8_t speed = MG_PHY_SPEED_10M;
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bool full_duplex = false;
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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up = mg_phy_up(&phy, 0, &full_duplex, &speed);
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// If PHY is ready, update NCFGR accordingly
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if (ifp->state == MG_TCPIP_STATE_DOWN && up) {
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GMAC_REGS->GMAC_NCFGR =
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(GMAC_REGS->GMAC_NCFGR & ~(MG_BIT(0) | MG_BIT(1))) | (speed & 1) |
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(full_duplex << 1);
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}
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}
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return up;
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}
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void GMAC_Handler(void);
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void GMAC_Handler(void) {
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uint32_t isr = GMAC_REGS->GMAC_ISR;
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uint32_t rsr = GMAC_REGS->GMAC_RSR;
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uint32_t tsr = GMAC_REGS->GMAC_TSR;
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if (isr & MG_BIT(1)) {
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if (rsr & MG_BIT(1)) {
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for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
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if ((s_rxdesc[s_rxno][0] & MG_BIT(0)) == 0) break;
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size_t len = s_rxdesc[s_rxno][1] & (MG_BIT(13) - 1);
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
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s_rxdesc[s_rxno][0] &= ~MG_BIT(0); // Disown
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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}
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}
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if (tsr != 0) {
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// MG_INFO((" --> %#x %#x", s_txdesc[s_txno][1], tsr));
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if (!(s_txdesc[s_txno][1] & MG_BIT(31))) s_txdesc[s_txno][1] |= MG_BIT(31);
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}
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GMAC_REGS->GMAC_RSR = rsr;
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GMAC_REGS->GMAC_TSR = tsr;
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}
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struct mg_tcpip_driver mg_tcpip_driver_same54 = {
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mg_tcpip_driver_same54_init, mg_tcpip_driver_same54_tx, NULL,
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mg_tcpip_driver_same54_poll};
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#endif
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