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213 lines
9.0 KiB
C
213 lines
9.0 KiB
C
// Copyright (c) 2026 Cesanta Software Limited
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// All rights reserved
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//
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// Seeed Studio XIAO MG24 hardware abstraction layer. EFR32MG24B220F1536IM48
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// reference: Simplicity SDK, https://github.com/SiliconLabs/simplicity_sdk,
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// platform/Device/SiliconLabs/EFR32MG24. Board: Seeed XIAO MG24 schematic,
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// pin names from Silicon Labs Arduino core, variants/xiao_mg24
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#pragma once
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#include "em_device.h"
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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uint64_t hal_get_tick(void);
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bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now);
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size_t hal_ram_used(void);
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size_t hal_ram_free(void);
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uint32_t hal_rng_read(void); // Random 32 bits, Secure Engine TRNG. See hal.c
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#define BIT(x) (1UL << (x))
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#define PIN(port, num) ((((port) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINPORT(pin) (pin >> 8)
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#define RF_SW_PIN PIN('B', 4) // Antenna switch VCTL: low onboard, high UFL
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#define RF_SW_PWR_PIN PIN('B', 5) // Antenna switch power
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// HFXO crystal tuning, XIAO MG24 board value: Silicon Labs Arduino core,
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// sl_device_init_hfxo_config.h. XO gets +40, see ctuneDelta in em_cmu.c
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#define HFXO_CTUNE 95
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#define HFXO_CTUNE_XO_DELTA 40
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enum { GPIO_MODE_DISABLED = 0, GPIO_MODE_INPUT = 1, GPIO_MODE_PUSHPULL = 4 };
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static inline void gpio_set_mode(uint16_t pin, uint32_t mode) {
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volatile uint32_t *r = PINNO(pin) < 8 ? &GPIO->P[PINPORT(pin)].MODEL
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: &GPIO->P[PINPORT(pin)].MODEH;
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uint32_t shift = (PINNO(pin) & 7) * 4;
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*r = (*r & ~(15UL << shift)) | (mode << shift);
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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if (val) {
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GPIO->P_SET[PINPORT(pin)].DOUT = BIT(PINNO(pin));
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} else {
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GPIO->P_CLR[PINPORT(pin)].DOUT = BIT(PINNO(pin));
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}
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}
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static inline void gpio_output(uint16_t pin, bool val) {
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gpio_write(pin, val);
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gpio_set_mode(pin, GPIO_MODE_PUSHPULL);
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}
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// Start the HFXO crystal oscillator, 39 MHz, and wait until it is ready.
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// Steps and default values as in CMU_HFXOInit() and CMU_HFXOINIT_DEFAULT,
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// emlib em_cmu.c. The radio needs HFXO, and RAIL expects it configured
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static inline void hal_hfxo_init(void) {
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CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0;
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HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK;
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HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND | HFXO_CTRL_DISONDEMANDBUFOUT;
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HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
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while (HFXO0->STATUS & HFXO_STATUS_ENS) (void) 0; // Wait until disabled
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while (HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) (void) 0;
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HFXO0->XTALCFG = HFXO_XTALCFG_TIMEOUTCBLSB_T416US |
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HFXO_XTALCFG_TIMEOUTSTEADY_T833US | // First lock
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(32U << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) |
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(32U << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT);
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HFXO0->XTALCTRL =
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(HFXO0->XTALCTRL & _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK) |
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HFXO_XTALCTRL_CTUNEFIXANA_XO | // 20 dBm PA parts, see em_cmu.h
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((uint32_t) (HFXO_CTUNE + HFXO_CTUNE_XO_DELTA)
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<< _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) |
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((uint32_t) HFXO_CTUNE << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) |
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(60U << _HFXO_XTALCTRL_COREBIASANA_SHIFT);
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HFXO0->CFG &= ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK | _HFXO_CFG_ENXIDCBIASANA_MASK |
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_HFXO_CFG_MODE_MASK); // Crystal mode
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HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK |
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_HFXO_CTRL_FORCEXI2GNDANA_MASK |
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_HFXO_CTRL_DISONDEMAND_MASK |
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_HFXO_CTRL_EM23ONDEMAND_MASK)) |
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HFXO_CTRL_FORCEEN;
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uint32_t ready = HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY |
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HFXO_STATUS_ENS;
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while ((HFXO0->STATUS & ready) != ready) (void) 0;
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HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
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HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) |
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HFXO_XTALCFG_TIMEOUTSTEADY_T83US; // Subsequent locks
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HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT;
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HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; // Radio can request it on demand
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}
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// Lock HFRCODPLL to HFXO at 78 MHz: 39 MHz * (N + 1) / (M + 1), N 3839,
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// M 1919, phase lock, falling edge, auto recover. Values and steps as in
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// Simplicity SDK CMU_DPLLLock() and the xG24 clock manager configuration.
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// HFRCO band 72.6..80 MHz, tuned with its factory calibration from DEVINFO
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static inline bool hal_dpll_78mhz(void) {
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uint32_t lock = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH;
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CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0;
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DPLL0->EN_CLR = DPLL_EN_EN;
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while (DPLL0->EN & DPLL_EN_DISABLING) (void) 0;
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while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY))
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(void) 0;
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HFRCO0->CAL = 0xCCF09F00UL | (DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL &
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_HFRCO_CAL_TUNING_MASK);
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DPLL0->CFG1 = (3839UL << _DPLL_CFG1_N_SHIFT) | (1919UL << _DPLL_CFG1_M_SHIFT);
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CMU->DPLLREFCLKCTRL = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO;
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DPLL0->CFG = (1UL << _DPLL_CFG_AUTORECOVER_SHIFT) | // Edge: falling, 0
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(_DPLL_CFG_MODE_PLL << _DPLL_CFG_MODE_SHIFT);
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DPLL0->IF_CLR = lock;
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DPLL0->EN_SET = DPLL_EN_EN;
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while ((DPLL0->IF & lock) == 0) (void) 0;
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return (DPLL0->IF & lock) == DPLL_IF_LOCK;
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}
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// Run the CPU at its maximum, 78 MHz, from HFRCODPLL locked to HFXO. First
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// set the limits for 78 MHz, datasheet table 4.2 and em_cmu.c: flash 1 wait
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// state above 40 MHz; PCLK max 50 MHz, so SYSCLK / 2; radio HCLK max 40 MHz,
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// so SYSCLK / 2. Voltage scaling is VSCALE2 after reset, fine for 78 MHz.
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// If the DPLL does not lock, stay on HFXO, 39 MHz
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static inline void hal_clock_init(void) {
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hal_hfxo_init();
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CMU->CLKEN1_SET = CMU_CLKEN1_MSC;
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MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK;
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MSC->READCTRL = (MSC->READCTRL & ~_MSC_READCTRL_MODE_MASK) |
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MSC_READCTRL_MODE_WS1;
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CMU->SYSCLKCTRL_SET = CMU_SYSCLKCTRL_PCLKPRESC | CMU_SYSCLKCTRL_RHCLKPRESC;
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if (hal_dpll_78mhz()) {
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SystemHFRCODPLLClockSet(78000000);
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CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) |
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CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL;
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} else {
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CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) |
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CMU_SYSCLKCTRL_CLKSEL_HFXO;
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}
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SystemCoreClock = SystemSYSCLKGet(); // HCLK = SYSCLK, no prescaler
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SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
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}
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// PCLK, the peripheral clock: SYSCLK, divided by 2 if PCLKPRESC is set
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static inline uint32_t hal_pclk(void) {
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bool half = (CMU->SYSCLKCTRL & CMU_SYSCLKCTRL_PCLKPRESC) != 0;
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return half ? SystemCoreClock / 2 : SystemCoreClock;
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}
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static inline void hal_gpio_output(uint16_t pin) {
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CMU->CLKEN0_SET = CMU_CLKEN0_GPIO;
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gpio_set_mode(pin, GPIO_MODE_PUSHPULL);
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}
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static inline void hal_gpio_toggle(uint16_t pin) {
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GPIO->P_TGL[PINPORT(pin)].DOUT = BIT(PINNO(pin));
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}
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// USART0, 8N1, on tx and rx pins: any pin, through GPIO routing. On XIAO
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// MG24, PA8 TX and PA9 RX go to the SAMD11 USB serial bridge. USART0 is
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// clocked by PCLK
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static inline void hal_uart_init(USART_TypeDef *uart, uint16_t tx, uint16_t rx,
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unsigned long baud) {
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uint32_t ovs = 16, div, pclk = hal_pclk();
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CMU->CLKEN0_SET = CMU_CLKEN0_GPIO | CMU_CLKEN0_USART0;
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gpio_output(tx, 1);
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gpio_set_mode(rx, GPIO_MODE_INPUT);
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GPIO->USARTROUTE[0].TXROUTE =
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((uint32_t) PINPORT(tx) << _GPIO_USART_TXROUTE_PORT_SHIFT) |
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((uint32_t) PINNO(tx) << _GPIO_USART_TXROUTE_PIN_SHIFT);
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GPIO->USARTROUTE[0].RXROUTE =
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((uint32_t) PINPORT(rx) << _GPIO_USART_RXROUTE_PORT_SHIFT) |
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((uint32_t) PINNO(rx) << _GPIO_USART_RXROUTE_PIN_SHIFT);
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GPIO->USARTROUTE[0].ROUTEEN =
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GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN;
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uart->EN = USART_EN_EN;
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uart->CTRL = 0; // Async, 16x oversampling
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uart->FRAME = USART_FRAME_DATABITS_EIGHT | USART_FRAME_STOPBITS_ONE |
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USART_FRAME_PARITY_NONE;
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// CLKDIV = 256 * (fPCLK / (ovs * baud) - 1), see USART_BaudrateAsyncSet()
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div = (32 * pclk + (ovs * baud) / 2) / (ovs * baud) - 32;
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uart->CLKDIV = (div * 8) & _USART_CLKDIV_DIV_MASK;
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uart->CMD = USART_CMD_TXEN | USART_CMD_RXEN;
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}
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static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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while ((uart->STATUS & USART_STATUS_TXBL) == 0) (void) 0;
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uart->TXDATA = byte;
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}
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static inline void hal_uart_write_buf(USART_TypeDef *uart, const char *buf,
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size_t len) {
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while (len-- > 0) hal_uart_write_byte(uart, *(const uint8_t *) buf++);
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}
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// Random numbers come from the Secure Engine TRNG, see hal_rng_read(): clock
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// its mailbox
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static inline void hal_rng_init(void) {
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CMU->CLKEN1_SET = CMU_CLKEN1_SEMAILBOXHOST;
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}
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// Prepare for RAIL. Set all IRQs to priority 5, as Silicon Labs
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// sl_interrupt_manager_init() does: RAIL atomic sections mask priority
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// numbers 3 and above. Route the radio to the onboard ceramic antenna.
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// FM8625H switch: VCTL low connects ANT to RF1, the chip antenna; high RF2,
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// the U.FL socket
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static inline void hal_radio_init(void) {
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for (int i = 0; i < EXT_IRQ_COUNT; i++) NVIC_SetPriority((IRQn_Type) i, 5);
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CMU->CLKEN0_SET = CMU_CLKEN0_GPIO;
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gpio_output(RF_SW_PWR_PIN, 1);
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gpio_output(RF_SW_PIN, 0);
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}
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