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Add STM32N driver support
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robert committed
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@@ -24230,9 +24230,10 @@ struct mg_tcpip_driver mg_tcpip_driver_stm32f = {
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#endif
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#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
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#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
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MG_ENABLE_DRIVER_STM32N)
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// STM32H: vendor modded single-queue Synopsys v4.2
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// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
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// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
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// RT1170 ENET_QOS: quad-queue Synopsys v5.1
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struct synopsys_enet_qos {
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volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
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@@ -24271,17 +24272,20 @@ struct synopsys_enet_qos {
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0x8000UL))
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#elif MG_ENABLE_DRIVER_MCXN
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#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
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#elif MG_ENABLE_DRIVER_STM32N
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#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
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#endif
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static struct mg_tcpip_if *s_ifp; // MIP interface
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#define MG_8BYTE_ALIGNED __attribute__((aligned(8)))
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static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
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static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
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static struct mg_tcpip_if *s_ifp; // MIP interface
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static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMDIOAR &= (0xF << 8);
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@@ -24332,7 +24336,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
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ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
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ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
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ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
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#if !MG_ENABLE_DRIVER_MCXN
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#if MG_ENABLE_DRIVER_STM32H
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ETH->MACPFR = MG_BIT(10); // Perfect filtering
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#endif
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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@@ -24401,7 +24405,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
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}
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static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
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#if MG_ENABLE_DRIVER_MCXN
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#if MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
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ETH->MACPFR = MG_BIT(4); // Pass Multicast (pass all multicast frames)
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#else
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// TODO(): read database, rebuild hash table
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@@ -24412,7 +24416,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
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ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
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ETH->MACA1HR |= MG_BIT(31); // AE
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#endif
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(void) ifp;
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(void) ifp;
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}
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static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
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@@ -24446,9 +24450,12 @@ static uint32_t s_rxno;
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#if MG_ENABLE_DRIVER_MCXN
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void ETHERNET_IRQHandler(void);
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void ETHERNET_IRQHandler(void) {
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#else
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#elif MG_ENABLE_DRIVER_STM32H
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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#else
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void ETH1_IRQHandler(void);
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void ETH1_IRQHandler(void) {
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#endif
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if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
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ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag
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+4
-1
@@ -3596,7 +3596,10 @@ struct mg_tcpip_driver_stm32f_data {
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#if !defined(MG_ENABLE_DRIVER_MCXN)
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#define MG_ENABLE_DRIVER_MCXN 0
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#endif
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#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
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#if !defined(MG_ENABLE_DRIVER_STM32N)
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#define MG_ENABLE_DRIVER_STM32N 0
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#endif
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#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
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struct mg_tcpip_driver_stm32h_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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+18
-11
@@ -1,8 +1,9 @@
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#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
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#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
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MG_ENABLE_DRIVER_STM32N)
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// STM32H: vendor modded single-queue Synopsys v4.2
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// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
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// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
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// RT1170 ENET_QOS: quad-queue Synopsys v5.1
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struct synopsys_enet_qos {
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volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
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@@ -41,17 +42,20 @@ struct synopsys_enet_qos {
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0x8000UL))
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#elif MG_ENABLE_DRIVER_MCXN
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#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
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#elif MG_ENABLE_DRIVER_STM32N
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#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
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#endif
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static struct mg_tcpip_if *s_ifp; // MIP interface
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#define MG_8BYTE_ALIGNED __attribute__((aligned(8)))
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static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
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static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
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static struct mg_tcpip_if *s_ifp; // MIP interface
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static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMDIOAR &= (0xF << 8);
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@@ -102,7 +106,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
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ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
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ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
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ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
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#if !MG_ENABLE_DRIVER_MCXN
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#if MG_ENABLE_DRIVER_STM32H
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ETH->MACPFR = MG_BIT(10); // Perfect filtering
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#endif
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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@@ -171,7 +175,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
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}
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static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
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#if MG_ENABLE_DRIVER_MCXN
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#if MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
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ETH->MACPFR = MG_BIT(4); // Pass Multicast (pass all multicast frames)
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#else
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// TODO(): read database, rebuild hash table
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@@ -182,7 +186,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
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ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
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ETH->MACA1HR |= MG_BIT(31); // AE
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#endif
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(void) ifp;
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(void) ifp;
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}
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static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
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@@ -216,9 +220,12 @@ static uint32_t s_rxno;
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#if MG_ENABLE_DRIVER_MCXN
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void ETHERNET_IRQHandler(void);
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void ETHERNET_IRQHandler(void) {
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#else
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#elif MG_ENABLE_DRIVER_STM32H
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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#else
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void ETH1_IRQHandler(void);
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void ETH1_IRQHandler(void) {
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#endif
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if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
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ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag
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@@ -7,7 +7,10 @@
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#if !defined(MG_ENABLE_DRIVER_MCXN)
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#define MG_ENABLE_DRIVER_MCXN 0
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#endif
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#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
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#if !defined(MG_ENABLE_DRIVER_STM32N)
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#define MG_ENABLE_DRIVER_STM32N 0
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#endif
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#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
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struct mg_tcpip_driver_stm32h_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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