mirror of
https://github.com/cesanta/mongoose.git
synced 2026-10-29 12:41:03 +00:00
ETH driver: use the same scheme for RX
This commit is contained in:
1 parent
0a86bc0af2
commit
5269eb9c39
4 files changed
+54
-60
No files matched your search
+27
-30
@@ -21875,19 +21875,18 @@ void EMAC_RX_IRQHandler(void) {
|
||||
uint32_t i;
|
||||
//MG_INFO(("RX interrupt"));
|
||||
for (i = 0; i < 10; i++) { // read as they arrive but not forever
|
||||
if ((s_rxdesc[s_rxno][3] & SWAP32(MG_BIT(29))) == 0) {
|
||||
uint32_t len = SWAP32(s_rxdesc[s_rxno][3]) & 0xffff;
|
||||
//MG_INFO(("recv len: %d", len));
|
||||
//mg_hexdump(s_rxbuf[s_rxno], len);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
|
||||
uint32_t flags = s_rxdesc[s_rxno][3];
|
||||
s_rxdesc[s_rxno][3] = SWAP32(MG_BIT(29));
|
||||
s_rxdesc[s_rxno][2] = SWAP32(ETH_PKT_SIZE);
|
||||
EMAC->RXCP[0] = (uint32_t) &s_rxdesc[s_rxno][0];
|
||||
if (flags & SWAP32(MG_BIT(28))) {
|
||||
//MG_INFO(("EOQ detected"));
|
||||
EMAC->RXHDP[0] = (uint32_t) &s_rxdesc[0][0];
|
||||
}
|
||||
if (s_rxdesc[s_rxno][3] & SWAP32(MG_BIT(29))) break;
|
||||
uint32_t len = SWAP32(s_rxdesc[s_rxno][3]) & 0xffff;
|
||||
//MG_INFO(("recv len: %d", len));
|
||||
//mg_hexdump(s_rxbuf[s_rxno], len);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
|
||||
uint32_t flags = s_rxdesc[s_rxno][3];
|
||||
s_rxdesc[s_rxno][3] = SWAP32(MG_BIT(29));
|
||||
s_rxdesc[s_rxno][2] = SWAP32(ETH_PKT_SIZE);
|
||||
EMAC->RXCP[0] = (uint32_t) &s_rxdesc[s_rxno][0];
|
||||
if (flags & SWAP32(MG_BIT(28))) {
|
||||
//MG_INFO(("EOQ detected"));
|
||||
EMAC->RXHDP[0] = (uint32_t) &s_rxdesc[0][0];
|
||||
}
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
@@ -22311,16 +22310,15 @@ void ETH0_0_IRQHandler(void) {
|
||||
|
||||
// check if a frame was received
|
||||
if (irq_status & MG_BIT(6)) {
|
||||
for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
|
||||
if ((s_rxdesc[s_rxno][0] & MG_BIT(31)) == 0) {
|
||||
size_t len = (s_rxdesc[s_rxno][0] & 0x3fff0000) >> 16;
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] = MG_BIT(31); // OWN bit: handle control to DMA
|
||||
// Resume processing
|
||||
ETH0->STATUS = MG_BIT(7) | MG_BIT(6); // clear RU and RI
|
||||
ETH0->RECEIVE_POLL_DEMAND = 0;
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
for (uint8_t i = 0; i < 10; i++) { // read as they arrive, but not forever
|
||||
if (s_rxdesc[s_rxno][0] & MG_BIT(31)) break;
|
||||
size_t len = (s_rxdesc[s_rxno][0] & 0x3fff0000) >> 16;
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] = MG_BIT(31); // OWN bit: handle control to DMA
|
||||
// Resume processing
|
||||
ETH0->STATUS = MG_BIT(7) | MG_BIT(6); // clear RU and RI
|
||||
ETH0->RECEIVE_POLL_DEMAND = 0;
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
ETH0->STATUS = MG_BIT(6);
|
||||
}
|
||||
@@ -22565,13 +22563,12 @@ static bool mg_tcpip_driver_xmc7_up(struct mg_tcpip_if *ifp) {
|
||||
void ETH_IRQHandler(void) {
|
||||
uint32_t irq_status = ETH0->INT_STATUS;
|
||||
if (irq_status & MG_BIT(1)) {
|
||||
for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
|
||||
if (s_rxdesc[s_rxno][0] & MG_BIT(0)) {
|
||||
size_t len = s_rxdesc[s_rxno][1] & (MG_BIT(13) - 1);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] &= ~MG_BIT(0); // OWN bit: handle control to DMA
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
for (uint8_t i = 0; i < 10; i++) { // read as they arrive, but not forever
|
||||
if ((s_rxdesc[s_rxno][0] & MG_BIT(0)) == 0) break;
|
||||
size_t len = s_rxdesc[s_rxno][1] & (MG_BIT(13) - 1);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] &= ~MG_BIT(0); // OWN bit: handle control to DMA
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
+12
-13
@@ -206,19 +206,18 @@ void EMAC_RX_IRQHandler(void) {
|
||||
uint32_t i;
|
||||
//MG_INFO(("RX interrupt"));
|
||||
for (i = 0; i < 10; i++) { // read as they arrive but not forever
|
||||
if ((s_rxdesc[s_rxno][3] & SWAP32(MG_BIT(29))) == 0) {
|
||||
uint32_t len = SWAP32(s_rxdesc[s_rxno][3]) & 0xffff;
|
||||
//MG_INFO(("recv len: %d", len));
|
||||
//mg_hexdump(s_rxbuf[s_rxno], len);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
|
||||
uint32_t flags = s_rxdesc[s_rxno][3];
|
||||
s_rxdesc[s_rxno][3] = SWAP32(MG_BIT(29));
|
||||
s_rxdesc[s_rxno][2] = SWAP32(ETH_PKT_SIZE);
|
||||
EMAC->RXCP[0] = (uint32_t) &s_rxdesc[s_rxno][0];
|
||||
if (flags & SWAP32(MG_BIT(28))) {
|
||||
//MG_INFO(("EOQ detected"));
|
||||
EMAC->RXHDP[0] = (uint32_t) &s_rxdesc[0][0];
|
||||
}
|
||||
if (s_rxdesc[s_rxno][3] & SWAP32(MG_BIT(29))) break;
|
||||
uint32_t len = SWAP32(s_rxdesc[s_rxno][3]) & 0xffff;
|
||||
//MG_INFO(("recv len: %d", len));
|
||||
//mg_hexdump(s_rxbuf[s_rxno], len);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
|
||||
uint32_t flags = s_rxdesc[s_rxno][3];
|
||||
s_rxdesc[s_rxno][3] = SWAP32(MG_BIT(29));
|
||||
s_rxdesc[s_rxno][2] = SWAP32(ETH_PKT_SIZE);
|
||||
EMAC->RXCP[0] = (uint32_t) &s_rxdesc[s_rxno][0];
|
||||
if (flags & SWAP32(MG_BIT(28))) {
|
||||
//MG_INFO(("EOQ detected"));
|
||||
EMAC->RXHDP[0] = (uint32_t) &s_rxdesc[0][0];
|
||||
}
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
|
||||
+9
-10
@@ -199,16 +199,15 @@ void ETH0_0_IRQHandler(void) {
|
||||
|
||||
// check if a frame was received
|
||||
if (irq_status & MG_BIT(6)) {
|
||||
for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
|
||||
if ((s_rxdesc[s_rxno][0] & MG_BIT(31)) == 0) {
|
||||
size_t len = (s_rxdesc[s_rxno][0] & 0x3fff0000) >> 16;
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] = MG_BIT(31); // OWN bit: handle control to DMA
|
||||
// Resume processing
|
||||
ETH0->STATUS = MG_BIT(7) | MG_BIT(6); // clear RU and RI
|
||||
ETH0->RECEIVE_POLL_DEMAND = 0;
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
for (uint8_t i = 0; i < 10; i++) { // read as they arrive, but not forever
|
||||
if (s_rxdesc[s_rxno][0] & MG_BIT(31)) break;
|
||||
size_t len = (s_rxdesc[s_rxno][0] & 0x3fff0000) >> 16;
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] = MG_BIT(31); // OWN bit: handle control to DMA
|
||||
// Resume processing
|
||||
ETH0->STATUS = MG_BIT(7) | MG_BIT(6); // clear RU and RI
|
||||
ETH0->RECEIVE_POLL_DEMAND = 0;
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
ETH0->STATUS = MG_BIT(6);
|
||||
}
|
||||
|
||||
+6
-7
@@ -219,13 +219,12 @@ static bool mg_tcpip_driver_xmc7_up(struct mg_tcpip_if *ifp) {
|
||||
void ETH_IRQHandler(void) {
|
||||
uint32_t irq_status = ETH0->INT_STATUS;
|
||||
if (irq_status & MG_BIT(1)) {
|
||||
for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
|
||||
if (s_rxdesc[s_rxno][0] & MG_BIT(0)) {
|
||||
size_t len = s_rxdesc[s_rxno][1] & (MG_BIT(13) - 1);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] &= ~MG_BIT(0); // OWN bit: handle control to DMA
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
for (uint8_t i = 0; i < 10; i++) { // read as they arrive, but not forever
|
||||
if ((s_rxdesc[s_rxno][0] & MG_BIT(0)) == 0) break;
|
||||
size_t len = s_rxdesc[s_rxno][1] & (MG_BIT(13) - 1);
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxdesc[s_rxno][0] &= ~MG_BIT(0); // OWN bit: handle control to DMA
|
||||
if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in new issue
Block a user