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Fix MAC address filtering on STM32 and TM4C

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Sergio R. Caprile committed 2022-11-28 10:16:10 -03:00
1 parent 90910a7a4f
commit 858f4da0d1
3 files changed
+4 -4
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mip/driver_stm32.c
+1 -1
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@@ -131,7 +131,7 @@ static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
ETH->MACFCR = BIT(7); // Disable zero quarta pause
ETH->MACFFR = BIT(31); // Receive all
// ETH->MACFFR = BIT(31); // Receive all
eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
ETH->DMARDLAR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
mip/driver_tm4c.c
+1 -1
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@@ -145,7 +145,7 @@ static bool mip_driver_tm4c_init(uint8_t *mac, void *userdata) {
// EMAC->EMACDMABUSMOD = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
EMAC->EMACIM = BIT(3) | BIT(9); // Mask timestamp & PMT IT
EMAC->EMACFLOWCTL = BIT(7); // Disable zero-quanta pause
EMAC->EMACFRAMEFLTR = BIT(31); // Receive all
// EMAC->EMACFRAMEFLTR = BIT(31); // Receive all
// EMAC->EMACPC defaults to internal PHY (EPHY) in MMI mode
emac_write_phy(EPHY_ADDR, EPHYBMCR, BIT(15)); // Reset internal PHY (EPHY)
emac_write_phy(EPHY_ADDR, EPHYBMCR, BIT(12)); // Set autonegotiation
mongoose.c
+2 -2
View File
@@ -6116,7 +6116,7 @@ static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
ETH->MACFCR = BIT(7); // Disable zero quarta pause
ETH->MACFFR = BIT(31); // Receive all
// ETH->MACFFR = BIT(31); // Receive all
eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
ETH->DMARDLAR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
@@ -6339,7 +6339,7 @@ static bool mip_driver_tm4c_init(uint8_t *mac, void *userdata) {
// EMAC->EMACDMABUSMOD = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
EMAC->EMACIM = BIT(3) | BIT(9); // Mask timestamp & PMT IT
EMAC->EMACFLOWCTL = BIT(7); // Disable zero-quanta pause
EMAC->EMACFRAMEFLTR = BIT(31); // Receive all
// EMAC->EMACFRAMEFLTR = BIT(31); // Receive all
// EMAC->EMACPC defaults to internal PHY (EPHY) in MMI mode
emac_write_phy(EPHY_ADDR, EPHYBMCR, BIT(15)); // Reset internal PHY (EPHY)
emac_write_phy(EPHY_ADDR, EPHYBMCR, BIT(12)); // Set autonegotiation