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Add nucleo-c5a3zg
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@@ -3646,7 +3646,7 @@ struct mg_fs mg_fs_posix = {p_stat, p_list, p_open, p_close, p_read,
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struct mg_health mg_health_record MG_HEALTH_RAM;
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// STM32 H723 support. Needs the _estack symbol from the linker script
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#if MG_ENABLE_HEALTH && (defined(STM32H7_DEV_ID) || defined(STM32H5))
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#if MG_ENABLE_HEALTH && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5))
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// Fault handler body. Runs in exception context: no printf, no malloc, no
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// blocking calls. Copies the unwind registers and raw stack into the health
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// record, then resets.
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@@ -13275,7 +13275,7 @@ struct mg_flash *mg_flash = &s_mg_flash_stm32f;
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#if MG_OTA == MG_OTA_STM32H5
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#if MG_OTA == MG_OTA_STM32H5 || MG_OTA == MG_OTA_STM32C5
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static bool mg_stm32h5_write(void *, const void *, size_t);
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static bool mg_stm32h5_swap(void);
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@@ -34396,7 +34396,7 @@ static uint32_t s_rxno;
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#if MG_ENABLE_DRIVER_MCXN
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void ETHERNET_IRQHandler(void);
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void ETHERNET_IRQHandler(void) {
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#elif MG_ENABLE_DRIVER_STM32H
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#elif MG_ENABLE_DRIVER_STM32H && !MG_ENABLE_DRIVER_STM32C
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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#else
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@@ -34425,8 +34425,10 @@ void ETH1_IRQHandler(void) {
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}
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ETH->DMACSR =
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MG_BIT(7) | MG_BIT(8); // Clear possible RBU RPS while processing
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ETH->DMACRDTPR =
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(uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT - 1]; // and resume RX
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// Resume RX: tail is the last descriptor given back to DMA. It must differ
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// from the DMA current descriptor, or some DMAs, e.g. STM32C5, stay suspended
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ETH->DMACRDTPR = (uint32_t) (uintptr_t) &s_rxdesc[(s_rxno + ETH_DESC_CNT - 1) %
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ETH_DESC_CNT];
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}
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struct mg_tcpip_driver mg_tcpip_driver_stm32h = {
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