fix mg_send() failing on 0 length

Fix 2-way auth max msg size, + some neats

.github/workflows/nightly.yml

@@ -33,11 +33,19 @@ jobs:
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
-      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST
+      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST -DNO_ABORT
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && test/setup_mqtt_server.sh && make -C test ${{ matrix.target }}
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/linux_${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
   mip:
     runs-on: ubuntu-latest
     strategy:
@@ -54,11 +62,20 @@ jobs:
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
-      TFLAGS: -DMQTT_LOCALHOST
+      TFLAGS: -DMQTT_LOCALHOST -DNO_ABORT
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: if [ "${{ matrix.target }}" == "mip_tap_test" ]; then ./test/setup_ga_network.sh ; fi && sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }} IPV6=0
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: if [ "${{ matrix.target }}" == "mip_tap_test" ]; then ./test/setup_ga_network.sh ; fi && sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }} IPV6=0 > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_$(date +"%Y%m%d").json"
+
   mip89:
     runs-on: ubuntu-latest
     strategy:
@@ -151,9 +168,18 @@ jobs:
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: brew install mbedtls wolfssl mosquitto # jq openssl already pre-installed
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: brew install mbedtls wolfssl mosquitto gawk # jq openssl already pre-installed
     - run: /opt/homebrew/opt/mosquitto/sbin/mosquitto -c /Users/runner/work/mongoose/mongoose/test/mosquitto.conf.macos &
-    - run: make -C test test ASAN_OPTIONS= MBEDTLS=$(echo $(brew --cellar)/mbedtls*/*) OPENSSL=$(echo $(brew --cellar)/openssl*/*) WOLFSSL=$(echo $(brew --cellar)/wolfssl*/*)
+    - run: make -C test test ASAN_OPTIONS= MBEDTLS=$(echo $(brew --cellar)/mbedtls*/*) OPENSSL=$(echo $(brew --cellar)/openssl*/*) WOLFSSL=$(echo $(brew --cellar)/wolfssl*/*) > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/macos_test_cc_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
+
   windows:
     runs-on: ubuntu-latest
     strategy:
@@ -173,7 +199,16 @@ jobs:
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: ./test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} 
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: ./test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/windows_${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
+ 
   arm:
     runs-on: ubuntu-latest
     strategy:
@@ -204,9 +239,18 @@ jobs:
     name: tutorials ${{ matrix.ssl }}
     steps:
     - uses: actions/checkout@v4
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
     - run: sudo apt -y install libpcap-dev
-    - run: make -C test tutorials CFLAGS_EXTRA="${{ matrix.ssl }}"
+    - run: make -C test tutorials CFLAGS_EXTRA="${{ matrix.ssl }}" > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/tutorials_${{ matrix.ssl }}_$(date +"%Y%m%d").json"
     - run: make -C test clean_tutorials
+
   tutorials_win:
     runs-on: windows-latest
     strategy:
@@ -466,9 +510,9 @@ jobs:
     - run: make -C tutorials/stm32/nucleo-f746zg-make-freertos-tcp test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     - name: Cube
       run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
-    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
 
   test_f4:
     runs-on: ubuntu-latest
@@ -481,9 +525,9 @@ jobs:
     - run: make -C tutorials/stm32/nucleo-f429zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     - name: Cube
       run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
 
   test_h743:
     runs-on: ubuntu-latest
@@ -496,8 +540,8 @@ jobs:
     - run: make -C tutorials/stm32/nucleo-h743zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #    - name: Cube
 #      run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
-#    - run: make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
 
   test_h723:
     runs-on: ubuntu-latest

README.md

@@ -209,6 +209,8 @@ Technical guides and deep dives into embedded web servers, WebUI integration and
 - [STM32 WebSocket Guide](https://mongoose.ws/articles/stm32-websocket-guide/)
 - [Web File Manager on STM32, ESP32 and Embedded Linux](https://mongoose.ws/articles/building-a-web-file-manager-on-stm32-esp32-embedded-linux/)
 - [Web dashboard on Zephyr RTOS](https://mongoose.ws/articles/web-dashboard-on-zephyr-rtos/)
+- [Limiting TCP/IP RAM usage on STM32](https://mongoose.ws/articles/limiting-tcpip-ram-usage-on-stm32/)
+- [STM32 Ethernet explained](https://mongoose.ws/articles/stm32-ethernet-explained/)
 
 
 ## Contributions

mongoose.h

@@ -20,7 +20,7 @@
 #ifndef MONGOOSE_H
 #define MONGOOSE_H
 
-#define MG_VERSION "7.19"
+#define MG_VERSION "7.20"
 
 #ifdef __cplusplus
 extern "C" {
@@ -285,6 +285,7 @@ extern "C" {
 #define mode_t size_t
 #include <alloca.h>
 #include <time.h>
+#define strdup(s) ((char *) mg_strdup(mg_str(s)).buf)
 #elif defined(__CCRH__)
 #else
 #include <sys/stat.h>
@@ -1056,10 +1057,34 @@ struct timeval {
 #define MG_TCPIP_GW MG_IPV4(0, 0, 0, 0)  // Default is 0.0.0.0 (DHCP)
 #endif
 
+#if MG_ENABLE_IPV6
+
+#ifndef MG_TCPIP_GLOBAL
+#define MG_TCPIP_GLOBAL MG_IPV6(0, 0, 0, 0, 0, 0, 0, 0)
+#endif
+
+#ifndef MG_TCPIP_IPV6_LINKLOCAL
+#define MG_TCPIP_IPV6_LINKLOCAL MG_IPV6(0, 0, 0, 0, 0, 0, 0, 0)
+#endif
+
+#ifndef MG_TCPIP_PREFIX_LEN
+#define MG_TCPIP_PREFIX_LEN 0
+#endif
+
+#ifndef MG_TCPIP_GW6
+#define MG_TCPIP_GW6 MG_IPV6(0, 0, 0, 0, 0, 0, 0, 0)
+#endif
+
+#endif
+
 #ifndef MG_SET_MAC_ADDRESS
 #define MG_SET_MAC_ADDRESS(mac)
 #endif
 
+#ifndef MG_TCPIP_DHCPNAME_SIZE
+#define MG_TCPIP_DHCPNAME_SIZE 18  // struct mg_tcpip_if :: dhcp_name size
+#endif
+
 #ifndef MG_SET_WIFI_CONFIG
 #define MG_SET_WIFI_CONFIG(data)
 #endif
@@ -1206,7 +1231,6 @@ size_t mg_vsnprintf(char *buf, size_t len, const char *fmt, va_list *ap);
 size_t mg_snprintf(char *, size_t, const char *fmt, ...);
 char *mg_vmprintf(const char *fmt, va_list *ap);
 char *mg_mprintf(const char *fmt, ...);
-size_t mg_queue_vprintf(struct mg_queue *, const char *fmt, va_list *);
 size_t mg_queue_printf(struct mg_queue *, const char *fmt, ...);
 
 // %M print helper functions
@@ -1364,6 +1388,16 @@ void mg_delayms(unsigned int ms);
 
 #define MG_IPV4(a, b, c, d) mg_htonl(MG_U32(a, b, c, d))
 
+#define MG_IPV6(a, b, c, d, e, f, g ,h) \
+  { (uint8_t)((a)>>8),(uint8_t)(a), \
+    (uint8_t)((b)>>8),(uint8_t)(b), \
+    (uint8_t)((c)>>8),(uint8_t)(c), \
+    (uint8_t)((d)>>8),(uint8_t)(d), \
+    (uint8_t)((e)>>8),(uint8_t)(e), \
+    (uint8_t)((f)>>8),(uint8_t)(f), \
+    (uint8_t)((g)>>8),(uint8_t)(g), \
+    (uint8_t)((h)>>8),(uint8_t)(h) }
+
 // For printing IPv4 addresses: printf("%d.%d.%d.%d\n", MG_IPADDR_PARTS(&ip))
 #define MG_U8P(ADDR) ((uint8_t *) (ADDR))
 #define MG_IPADDR_PARTS(ADDR) \
@@ -1378,6 +1412,14 @@ void mg_delayms(unsigned int ms);
   ((uint32_t) (((uint32_t) MG_U8P(p)[0] << 24U) | \
                ((uint32_t) MG_U8P(p)[1] << 16U) | \
                ((uint32_t) MG_U8P(p)[2] << 8U) | MG_U8P(p)[3]))
+#define MG_LOAD_BE64(p)                           \
+  ((uint64_t) (((uint64_t) MG_U8P(p)[0] << 56U) | \
+               ((uint64_t) MG_U8P(p)[1] << 48U) | \
+               ((uint64_t) MG_U8P(p)[2] << 40U) | \
+               ((uint64_t) MG_U8P(p)[3] << 32U) | \
+               ((uint64_t) MG_U8P(p)[4] << 24U) | \
+               ((uint64_t) MG_U8P(p)[5] << 16U) | \
+               ((uint64_t) MG_U8P(p)[6] << 8U) | MG_U8P(p)[7]))
 #define MG_STORE_BE16(p, n)           \
   do {                                \
     MG_U8P(p)[0] = ((n) >> 8U) & 255; \
@@ -1396,11 +1438,24 @@ void mg_delayms(unsigned int ms);
     MG_U8P(p)[2] = ((n) >> 8U) & 255;  \
     MG_U8P(p)[3] = (n) &255;           \
   } while (0)
+#define MG_STORE_BE64(p, n)            \
+  do {                                 \
+    MG_U8P(p)[0] = ((n) >> 56U) & 255; \
+    MG_U8P(p)[1] = ((n) >> 48U) & 255; \
+    MG_U8P(p)[2] = ((n) >> 40U) & 255; \
+    MG_U8P(p)[3] = ((n) >> 32U) & 255; \
+    MG_U8P(p)[4] = ((n) >> 24U) & 255; \
+    MG_U8P(p)[5] = ((n) >> 16U) & 255; \
+    MG_U8P(p)[6] = ((n) >> 8U) & 255;  \
+    MG_U8P(p)[7] = (n) &255;           \
+  } while (0)
 
 uint16_t mg_ntohs(uint16_t net);
 uint32_t mg_ntohl(uint32_t net);
+uint64_t mg_ntohll(uint64_t net);
 #define mg_htons(x) mg_ntohs(x)
 #define mg_htonl(x) mg_ntohl(x)
+#define mg_htonll(x) mg_ntohll(x)
 
 #define MG_REG(x) ((volatile uint32_t *) (x))[0]
 #define MG_BIT(x) (((uint32_t) 1U) << (x))
@@ -1484,8 +1539,8 @@ struct mg_iobuf {
   size_t align;        // Alignment during allocation
 };
 
-int mg_iobuf_init(struct mg_iobuf *, size_t, size_t);
+bool mg_iobuf_init(struct mg_iobuf *, size_t, size_t);
-int mg_iobuf_resize(struct mg_iobuf *, size_t);
+bool mg_iobuf_resize(struct mg_iobuf *, size_t);
 void mg_iobuf_free(struct mg_iobuf *);
 size_t mg_iobuf_add(struct mg_iobuf *, size_t, const void *, size_t);
 size_t mg_iobuf_del(struct mg_iobuf *, size_t ofs, size_t len);
@@ -1604,7 +1659,11 @@ struct mg_dns {
 };
 
 struct mg_addr {
-  uint8_t ip[16];    // Holds IPv4 or IPv6 address, in network byte order
+  union {    // Holds IPv4 or IPv6 address, in network byte order
+    uint8_t ip[16];
+    uint32_t ip4;
+    uint64_t ip6[2];
+  };
   uint16_t port;     // TCP or UDP port in network byte order
   uint8_t scope_id;  // IPv6 scope ID
   bool is_ip6;       // True when address is IPv6 address
@@ -1740,7 +1799,6 @@ int mg_http_parse(const char *s, size_t len, struct mg_http_message *);
 int mg_http_get_request_len(const unsigned char *buf, size_t buf_len);
 void mg_http_printf_chunk(struct mg_connection *cnn, const char *fmt, ...);
 void mg_http_write_chunk(struct mg_connection *c, const char *buf, size_t len);
-void mg_http_delete_chunk(struct mg_connection *c, struct mg_http_message *hm);
 struct mg_connection *mg_http_listen(struct mg_mgr *, const char *url,
                                      mg_event_handler_t fn, void *fn_data);
 struct mg_connection *mg_http_connect(struct mg_mgr *, const char *url,
@@ -3023,28 +3081,37 @@ bool mg_ota_flash_end(struct mg_flash *flash);
 
 
 
-struct mg_wifi_scan_bss_data {
+struct mg_wifi_data {
-    struct mg_str SSID;
+  char *ssid, *pass;      // STA mode, SSID to connect to
-    char *BSSID;
+  char *apssid, *appass;  // AP mode, our SSID
-    int16_t RSSI;
+  uint32_t apip, apmask;  // AP mode, our IP address and mask
-    uint8_t security;
+  uint8_t security;       // STA mode, TBD
-#define MG_WIFI_SECURITY_OPEN 0
+  uint8_t apsecurity;     // AP mode, TBD
-#define MG_WIFI_SECURITY_WEP  MG_BIT(0)
+  uint8_t apchannel;      // AP mode, channel to use
-#define MG_WIFI_SECURITY_WPA  MG_BIT(1)
+  bool apmode;  // start in AP mode; 'false' -> connect to 'ssid' != NULL
-#define MG_WIFI_SECURITY_WPA2 MG_BIT(2)
-#define MG_WIFI_SECURITY_WPA3 MG_BIT(3)
-    uint8_t channel;
-    unsigned band :2;
-#define MG_WIFI_BAND_2G 0
-#define MG_WIFI_BAND_5G 1
-    unsigned has_n :1;
 };
 
+struct mg_wifi_scan_bss_data {
+  struct mg_str SSID;
+  char *BSSID;
+  int16_t RSSI;
+  uint8_t security;
+#define MG_WIFI_SECURITY_OPEN 0
+#define MG_WIFI_SECURITY_WEP MG_BIT(0)
+#define MG_WIFI_SECURITY_WPA MG_BIT(1)
+#define MG_WIFI_SECURITY_WPA2 MG_BIT(2)
+#define MG_WIFI_SECURITY_WPA3 MG_BIT(3)
+  uint8_t channel;
+  unsigned band : 2;
+#define MG_WIFI_BAND_2G 0
+#define MG_WIFI_BAND_5G 1
+  unsigned has_n : 1;
+};
 
 bool mg_wifi_scan(void);
-bool mg_wifi_connect(char *ssid, char *pass);
+bool mg_wifi_connect(struct mg_wifi_data *);
 bool mg_wifi_disconnect(void);
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel);
+bool mg_wifi_ap_start(struct mg_wifi_data *);
 bool mg_wifi_ap_stop(void);
 
 
@@ -3077,10 +3144,10 @@ enum {
   MG_TCPIP_EV_WIFI_SCAN_END,    // Wi-Fi scan has finished        NULL
   MG_TCPIP_EV_WIFI_CONNECT_ERR, // Wi-Fi connect has failed       driver and chip specific
   MG_TCPIP_EV_DRIVER,           // Driver event                   driver specific
+  MG_TCPIP_EV_ST6_CHG,          // state6 change                  uint8_t * (&ifp->state6)
   MG_TCPIP_EV_USER              // Starting ID for user events
 };
 
-
 // Network interface
 struct mg_tcpip_if {
   uint8_t mac[6];                  // MAC address. Must be set to a valid MAC
@@ -3096,12 +3163,20 @@ struct mg_tcpip_if {
   bool update_mac_hash_table;      // Signal drivers to update MAC controller
   struct mg_tcpip_driver *driver;  // Low level driver
   void *driver_data;               // Driver-specific data
+  mg_tcpip_event_handler_t pfn;    // Driver-specific event handler function
   mg_tcpip_event_handler_t fn;     // User-specified event handler function
   struct mg_mgr *mgr;              // Mongoose event manager
   struct mg_queue recv_queue;      // Receive queue
-  char dhcp_name[12];              // Name reported to DHCP, "mip" if unset
+  char dhcp_name[MG_TCPIP_DHCPNAME_SIZE];  // Name for DHCP, "mip" if unset
-  uint16_t mtu;                    // Interface MTU
+  uint16_t mtu;                            // Interface MTU
 #define MG_TCPIP_MTU_DEFAULT 1500
+#if MG_ENABLE_IPV6
+  uint64_t ip6ll[2], ip6[2];       // IPv6 link-local and global addresses
+  uint8_t prefix_len;              // Prefix length
+  uint64_t gw6[2];                 // Default gateway
+  bool enable_slaac;               // Enable IPv6 address autoconfiguration
+  bool enable_dhcp6_client;        // Enable DCHPv6 client
+#endif
 
   // Internal state, user can use it but should not change it
   uint8_t gwmac[6];             // Router's MAC
@@ -3114,14 +3189,17 @@ struct mg_tcpip_if {
   volatile uint32_t nrecv;      // Number of received frames
   volatile uint32_t nsent;      // Number of transmitted frames
   volatile uint32_t nerr;       // Number of driver errors
-  uint8_t state;                // Current state
+  uint8_t state;                // Current link and IPv4 state
 #define MG_TCPIP_STATE_DOWN 0   // Interface is down
 #define MG_TCPIP_STATE_UP 1     // Interface is up
 #define MG_TCPIP_STATE_REQ 2    // Interface is up, DHCP REQUESTING state
 #define MG_TCPIP_STATE_IP 3     // Interface is up and has an IP assigned
 #define MG_TCPIP_STATE_READY 4  // Interface has fully come up, ready to work
+#if MG_ENABLE_IPV6
+  uint8_t gw6mac[6];             // IPv6 Router's MAC
+  uint8_t state6;                // Current IPv6 state
+#endif
 };
-
 void mg_tcpip_init(struct mg_mgr *, struct mg_tcpip_if *);
 void mg_tcpip_free(struct mg_tcpip_if *);
 void mg_tcpip_qwrite(void *buf, size_t len, struct mg_tcpip_if *ifp);
@@ -3143,6 +3221,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_ppp;
 extern struct mg_tcpip_driver mg_tcpip_driver_pico_w;
 extern struct mg_tcpip_driver mg_tcpip_driver_rw612;
 extern struct mg_tcpip_driver mg_tcpip_driver_cyw;
+extern struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi;
 
 // Drivers that require SPI, can use this SPI abstraction
 struct mg_tcpip_spi {
@@ -3153,6 +3232,43 @@ struct mg_tcpip_spi {
 };
 
 
+// Alignment and memory section requirements
+#ifndef MG_8BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_8BYTE_ALIGNED __attribute__((aligned((8U))))
+#else
+#define MG_8BYTE_ALIGNED
+#endif // compiler
+#endif // 8BYTE_ALIGNED
+
+#ifndef MG_16BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_16BYTE_ALIGNED __attribute__((aligned((16U))))
+#else
+#define MG_16BYTE_ALIGNED
+#endif // compiler
+#endif // 16BYTE_ALIGNED
+
+#ifndef MG_32BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_32BYTE_ALIGNED __attribute__((aligned((32U))))
+#else
+#define MG_32BYTE_ALIGNED
+#endif // compiler
+#endif // 32BYTE_ALIGNED
+
+#ifndef MG_64BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_64BYTE_ALIGNED __attribute__((aligned((64U))))
+#else
+#define MG_64BYTE_ALIGNED
+#endif // compiler
+#endif // 64BYTE_ALIGNED
+
+#ifndef MG_ETH_RAM
+#define MG_ETH_RAM
+#endif
+
 #endif
 
 
@@ -3186,43 +3302,35 @@ struct mg_tcpip_driver_cyw_firmware {
 };
 
 struct mg_tcpip_driver_cyw_data {
+  struct mg_wifi_data wifi;
   void *bus;
   struct mg_tcpip_driver_cyw_firmware *fw;
-  char *ssid;
+  bool hs;  // use chip "high-speed" mode; otherwise SPI CPOL0 CPHA0 (DS 4.2.3 Table 6)
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
-  bool hs;          // use chip "high-speed" mode; otherwise SPI CPOL0 CPHA0 (DS 4.2.3 Table 6)
 };
 
-#if 0
+#define MG_TCPIP_DRIVER_INIT(mgr)                              \
-#define MG_TCPIP_DRIVER_INIT(mgr)                                 \
+  do {                                                         \
-  do {                                                            \
+    static struct mg_tcpip_driver_cyw_data driver_data_;       \
-    static struct mg_tcpip_driver_cyw_data driver_data_;          \
+    static struct mg_tcpip_if mif_;                            \
-    static struct mg_tcpip_if mif_;                               \
+    MG_SET_WIFI_CONFIG(&driver_data_);                         \
-    MG_SET_WIFI_CONFIG(&driver_data_);                            \
+    mif_.ip = MG_TCPIP_IP;                                     \
-    mif_.ip = MG_TCPIP_IP;                                        \
+    mif_.mask = MG_TCPIP_MASK;                                 \
-    mif_.mask = MG_TCPIP_MASK;                                    \
+    mif_.gw = MG_TCPIP_GW;                                     \
-    mif_.gw = MG_TCPIP_GW;                                        \
+    mif_.driver = &mg_tcpip_driver_cyw;                        \
-    mif_.driver = &mg_tcpip_driver_pico_w;                        \
+    mif_.driver_data = &driver_data_;                          \
-    mif_.driver_data = &driver_data_;                             \
+    mif_.recv_queue.size = 8192;                               \
-    mif_.recv_queue.size = 8192;                                  \
+    mif_.mac[0] = 2; /* MAC read from OTP at driver init */    \
-    mif_.mac[0] = 2; /* MAC read from OTP at driver init */       \
+    mg_tcpip_init(mgr, &mif_);                                 \
-    mg_tcpip_init(mgr, &mif_);                                    \
     MG_INFO(("Driver: cyw, MAC: %M", mg_print_mac, mif_.mac)); \
   } while (0)
-#endif
 
 #endif
 
 
 #if MG_ENABLE_TCPIP && \
   (defined(MG_ENABLE_DRIVER_IMXRT10) && MG_ENABLE_DRIVER_IMXRT10) || \
-  (defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11)
+  (defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11) || \
+  (defined(MG_ENABLE_DRIVER_MCXE) && MG_ENABLE_DRIVER_MCXE)
 
 struct mg_tcpip_driver_imxrt_data {
   // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
@@ -3268,6 +3376,34 @@ struct mg_tcpip_driver_imxrt_data {
 #endif
 
 
+#if MG_ENABLE_TCPIP  && \
+    defined(MG_ENABLE_DRIVER_NXP_WIFI) && MG_ENABLE_DRIVER_NXP_WIFI
+
+
+struct mg_tcpip_driver_nxp_wifi_data {
+  struct mg_wifi_data wifi;
+};
+
+
+#define MG_TCPIP_DRIVER_INIT(mgr)                                   \
+  do {                                                              \
+    static struct mg_tcpip_driver_nxp_wifi_data driver_data_;       \
+    static struct mg_tcpip_if mif_;                                 \
+    MG_SET_WIFI_CONFIG(&driver_data_);                              \
+    mif_.ip = MG_TCPIP_IP;                                          \
+    mif_.mask = MG_TCPIP_MASK;                                      \
+    mif_.gw = MG_TCPIP_GW;                                          \
+    mif_.driver = &mg_tcpip_driver_nxp_wifi;                        \
+    mif_.driver_data = &driver_data_;                               \
+    mif_.recv_queue.size = 8192;                                    \
+    mif_.mac[0] = 2; /* MAC read from OTP at driver init */         \
+    mg_tcpip_init(mgr, &mif_);                                      \
+    MG_INFO(("Driver: nxp wifi, MAC: %M", mg_print_mac, mif_.mac)); \
+  } while (0)
+
+#endif
+
+
 
 
 struct mg_phy {
@@ -3298,14 +3434,7 @@ bool mg_phy_up(struct mg_phy *, uint8_t addr, bool *full_duplex,
 #include "pico/unique_id.h"     // keep this include
 
 struct mg_tcpip_driver_pico_w_data {
-  char *ssid;
+  struct mg_wifi_data wifi;
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
 };
 
 #define MG_TCPIP_DRIVER_INIT(mgr)                                 \
@@ -3562,7 +3691,10 @@ struct mg_tcpip_driver_stm32f_data {
 #if !defined(MG_ENABLE_DRIVER_MCXN)
 #define MG_ENABLE_DRIVER_MCXN 0
 #endif
-#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
+#if !defined(MG_ENABLE_DRIVER_STM32N)
+#define MG_ENABLE_DRIVER_STM32N 0
+#endif
+#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
 
 struct mg_tcpip_driver_stm32h_data {
   // MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
@@ -3601,6 +3733,18 @@ struct mg_tcpip_driver_stm32h_data {
 #define MG_ENABLE_ETH_IRQ()
 #endif
 
+#if MG_ENABLE_IPV6
+#define MG_IPV6_INIT(mif)                                         \
+  do {                                                            \
+    memcpy(mif.ip6ll, (uint8_t[16]) MG_TCPIP_IPV6_LINKLOCAL, 16);     \
+    memcpy(mif.ip6, (uint8_t[16]) MG_TCPIP_GLOBAL, 16);           \
+    memcpy(mif.gw6, (uint8_t[16]) MG_TCPIP_GW6, 16);              \
+    mif.prefix_len = MG_TCPIP_PREFIX_LEN;                        \
+  } while(0)
+#else
+#define MG_IPV6_INIT(mif)
+#endif
+
 #define MG_TCPIP_DRIVER_INIT(mgr)                                 \
   do {                                                            \
     static struct mg_tcpip_driver_stm32h_data driver_data_;       \
@@ -3614,6 +3758,7 @@ struct mg_tcpip_driver_stm32h_data {
     mif_.driver = &mg_tcpip_driver_stm32h;                        \
     mif_.driver_data = &driver_data_;                             \
     MG_SET_MAC_ADDRESS(mif_.mac);                                 \
+    MG_IPV6_INIT(mif_);                                           \
     mg_tcpip_init(mgr, &mif_);                                    \
     MG_ENABLE_ETH_IRQ();                                          \
     MG_INFO(("Driver: stm32h, MAC: %M", mg_print_mac, mif_.mac)); \
@@ -3693,6 +3838,41 @@ struct mg_tcpip_driver_tms570_data {
 
 
 
+#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_XMC7) && MG_ENABLE_DRIVER_XMC7
+
+struct mg_tcpip_driver_xmc7_data {
+  int mdc_cr;  // Valid values: -1, 0, 1, 2, 3, 4, 5
+  uint8_t phy_addr;
+};
+
+#ifndef MG_TCPIP_PHY_ADDR
+#define MG_TCPIP_PHY_ADDR 0
+#endif
+
+#ifndef MG_DRIVER_MDC_CR
+#define MG_DRIVER_MDC_CR 3
+#endif
+
+#define MG_TCPIP_DRIVER_INIT(mgr)                                 \
+  do {                                                            \
+    static struct mg_tcpip_driver_xmc7_data driver_data_;       \
+    static struct mg_tcpip_if mif_;                               \
+    driver_data_.mdc_cr = MG_DRIVER_MDC_CR;                       \
+    driver_data_.phy_addr = MG_TCPIP_PHY_ADDR;                    \
+    mif_.ip = MG_TCPIP_IP;                                        \
+    mif_.mask = MG_TCPIP_MASK;                                    \
+    mif_.gw = MG_TCPIP_GW;                                        \
+    mif_.driver = &mg_tcpip_driver_xmc7;                        \
+    mif_.driver_data = &driver_data_;                             \
+    MG_SET_MAC_ADDRESS(mif_.mac);                                 \
+    mg_tcpip_init(mgr, &mif_);                                    \
+    MG_INFO(("Driver: xmc7, MAC: %M", mg_print_mac, mif_.mac)); \
+  } while (0)
+
+#endif
+
+
+
 #if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_XMC) && MG_ENABLE_DRIVER_XMC
 
 struct mg_tcpip_driver_xmc_data {
@@ -3739,41 +3919,6 @@ struct mg_tcpip_driver_xmc_data {
 
 #endif
 
-
-#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_XMC7) && MG_ENABLE_DRIVER_XMC7
-
-struct mg_tcpip_driver_xmc7_data {
-  int mdc_cr;  // Valid values: -1, 0, 1, 2, 3, 4, 5
-  uint8_t phy_addr;
-};
-
-#ifndef MG_TCPIP_PHY_ADDR
-#define MG_TCPIP_PHY_ADDR 0
-#endif
-
-#ifndef MG_DRIVER_MDC_CR
-#define MG_DRIVER_MDC_CR 3
-#endif
-
-#define MG_TCPIP_DRIVER_INIT(mgr)                                 \
-  do {                                                            \
-    static struct mg_tcpip_driver_xmc7_data driver_data_;       \
-    static struct mg_tcpip_if mif_;                               \
-    driver_data_.mdc_cr = MG_DRIVER_MDC_CR;                       \
-    driver_data_.phy_addr = MG_TCPIP_PHY_ADDR;                    \
-    mif_.ip = MG_TCPIP_IP;                                        \
-    mif_.mask = MG_TCPIP_MASK;                                    \
-    mif_.gw = MG_TCPIP_GW;                                        \
-    mif_.driver = &mg_tcpip_driver_xmc7;                        \
-    mif_.driver_data = &driver_data_;                             \
-    MG_SET_MAC_ADDRESS(mif_.mac);                                 \
-    mg_tcpip_init(mgr, &mif_);                                    \
-    MG_INFO(("Driver: xmc7, MAC: %M", mg_print_mac, mif_.mac)); \
-  } while (0)
-
-#endif
-
-
 #ifdef __cplusplus
 }
 #endif

src/arch_freertos.h

@@ -17,6 +17,7 @@
 #define mode_t size_t
 #include <alloca.h>
 #include <time.h>
+#define strdup(s) ((char *) mg_strdup(mg_str(s)).buf)
 #elif defined(__CCRH__)
 #else
 #include <sys/stat.h>

src/config.h

@@ -175,10 +175,34 @@
 #define MG_TCPIP_GW MG_IPV4(0, 0, 0, 0)  // Default is 0.0.0.0 (DHCP)
 #endif
 
+#if MG_ENABLE_IPV6
+
+#ifndef MG_TCPIP_GLOBAL
+#define MG_TCPIP_GLOBAL MG_IPV6(0, 0, 0, 0, 0, 0, 0, 0)
+#endif
+
+#ifndef MG_TCPIP_IPV6_LINKLOCAL
+#define MG_TCPIP_IPV6_LINKLOCAL MG_IPV6(0, 0, 0, 0, 0, 0, 0, 0)
+#endif
+
+#ifndef MG_TCPIP_PREFIX_LEN
+#define MG_TCPIP_PREFIX_LEN 0
+#endif
+
+#ifndef MG_TCPIP_GW6
+#define MG_TCPIP_GW6 MG_IPV6(0, 0, 0, 0, 0, 0, 0, 0)
+#endif
+
+#endif
+
 #ifndef MG_SET_MAC_ADDRESS
 #define MG_SET_MAC_ADDRESS(mac)
 #endif
 
+#ifndef MG_TCPIP_DHCPNAME_SIZE
+#define MG_TCPIP_DHCPNAME_SIZE 18  // struct mg_tcpip_if :: dhcp_name size
+#endif
+
 #ifndef MG_SET_WIFI_CONFIG
 #define MG_SET_WIFI_CONFIG(data)
 #endif

src/drivers/cyw.c

@@ -13,28 +13,42 @@
 #endif
 
 static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
 static bool s_link, s_auth, s_join;
 
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi = &((struct mg_tcpip_driver_cyw_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
+
 static bool cyw_init(uint8_t *mac);
 static void cyw_poll(void);
 
 static bool mg_tcpip_driver_cyw_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
+  struct mg_wifi_data *wifi = &d->wifi;
   if (MG_BIG_ENDIAN) {
     MG_ERROR(("Big-endian host"));
     return false;
   }
   s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
   s_link = s_auth = s_join = false;
+  ifp->pfn = wifi_cb;
   if (!cyw_init(ifp->mac)) return false;
 
-  if (d->apmode) {
+  if (wifi->apmode) {
-    MG_DEBUG(("Starting AP '%s' (%u)", d->apssid, d->apchannel));
+    return mg_wifi_ap_start(wifi);
-    return mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
+  } else if (wifi->ssid != NULL && wifi->pass != NULL) {
-  } else if (d->ssid != NULL && d->pass != NULL) {
+    return mg_wifi_connect(wifi);
-    MG_DEBUG(("Connecting to '%s'", d->ssid));
-    return mg_wifi_connect(d->ssid, d->pass);
   }
   return true;
 }
@@ -44,7 +58,7 @@ size_t mg_tcpip_driver_cyw_output(const void *buf, size_t len,
                                   struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-  return mg_cyw_tx(d->apmode ? 1 : 0, (void *) buf, len) >= len ? len : 0;
+  return mg_cyw_tx(d->wifi.apmode ? 1 : 0, (void *) buf, len) >= len ? len : 0;
 }
 
 static bool mg_tcpip_driver_cyw_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -52,7 +66,7 @@ static bool mg_tcpip_driver_cyw_poll(struct mg_tcpip_if *ifp, bool s1) {
   if (!s1) return false;
   struct mg_tcpip_driver_cyw_data *d =
       (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
-  return d->apmode ? s_link : s_link && s_auth && s_join;
+  return d->wifi.apmode ? s_link : s_link && s_auth && s_join;
 }
 
 struct mg_tcpip_driver mg_tcpip_driver_cyw = {mg_tcpip_driver_cyw_init,
@@ -1035,7 +1049,7 @@ static size_t cyw_spi_poll(uint8_t *response) {
     cyw_spi_write(CYW_SPID_FUNC_BUS, CYW_BUS_SPI_INT, &val, sizeof(val));
     return 0;
   }
-  cyw_spi_read(CYW_SPID_FUNC_WLAN, 0,  response, len);
+  cyw_spi_read(CYW_SPID_FUNC_WLAN, 0,  response, (uint16_t)len);
   return len;
 }
 
@@ -1098,7 +1112,7 @@ static bool cyw_spi_init() {
   cyw_set_backplane_window(CYW_CHIP_CHIPCOMMON); // set backplane window to start of CHIPCOMMON area
   cyw_spi_read(CYW_SPID_FUNC_CHIP, (CYW_CHIP_CHIPCOMMON + 0x00) & CYW_CHIP_BCKPLN_ADDRMSK, &val, 2);
   if (val == 43430) val = 4343;
-  MG_INFO(("WLAN chip is CYW%u%c", val), val == 4343 ? 'W' : ' '));
+  MG_INFO(("WLAN chip is CYW%u%c", val, val == 4343 ? 'W' : ' '));
 
   // Load firmware (code and NVRAM)
   if (!cyw_load_firmware(d->fw)) return false;
@@ -1376,16 +1390,22 @@ bool mg_wifi_scan(void) {
   return cyw_wifi_scan();
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
-  return cyw_wifi_connect(ssid, pass);
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  return cyw_wifi_connect(wifi->ssid, wifi->pass);
 }
 
 bool mg_wifi_disconnect(void) {
   return cyw_wifi_disconnect();
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
-  return cyw_wifi_ap_start(ssid, pass, channel);
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
+  return cyw_wifi_ap_start(wifi->apssid, wifi->appass, wifi->apchannel);
 }
 
 bool mg_wifi_ap_stop(void) {

src/drivers/cyw.h

@@ -22,35 +22,26 @@ struct mg_tcpip_driver_cyw_firmware {
 };
 
 struct mg_tcpip_driver_cyw_data {
+  struct mg_wifi_data wifi;
   void *bus;
   struct mg_tcpip_driver_cyw_firmware *fw;
-  char *ssid;
+  bool hs;  // use chip "high-speed" mode; otherwise SPI CPOL0 CPHA0 (DS 4.2.3 Table 6)
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
-  bool hs;          // use chip "high-speed" mode; otherwise SPI CPOL0 CPHA0 (DS 4.2.3 Table 6)
 };
 
-#if 0
+#define MG_TCPIP_DRIVER_INIT(mgr)                              \
-#define MG_TCPIP_DRIVER_INIT(mgr)                                 \
+  do {                                                         \
-  do {                                                            \
+    static struct mg_tcpip_driver_cyw_data driver_data_;       \
-    static struct mg_tcpip_driver_cyw_data driver_data_;          \
+    static struct mg_tcpip_if mif_;                            \
-    static struct mg_tcpip_if mif_;                               \
+    MG_SET_WIFI_CONFIG(&driver_data_);                         \
-    MG_SET_WIFI_CONFIG(&driver_data_);                            \
+    mif_.ip = MG_TCPIP_IP;                                     \
-    mif_.ip = MG_TCPIP_IP;                                        \
+    mif_.mask = MG_TCPIP_MASK;                                 \
-    mif_.mask = MG_TCPIP_MASK;                                    \
+    mif_.gw = MG_TCPIP_GW;                                     \
-    mif_.gw = MG_TCPIP_GW;                                        \
+    mif_.driver = &mg_tcpip_driver_cyw;                        \
-    mif_.driver = &mg_tcpip_driver_pico_w;                        \
+    mif_.driver_data = &driver_data_;                          \
-    mif_.driver_data = &driver_data_;                             \
+    mif_.recv_queue.size = 8192;                               \
-    mif_.recv_queue.size = 8192;                                  \
+    mif_.mac[0] = 2; /* MAC read from OTP at driver init */    \
-    mif_.mac[0] = 2; /* MAC read from OTP at driver init */       \
+    mg_tcpip_init(mgr, &mif_);                                 \
-    mg_tcpip_init(mgr, &mif_);                                    \
     MG_INFO(("Driver: cyw, MAC: %M", mg_print_mac, mif_.mac)); \
   } while (0)
-#endif
 
 #endif

src/drivers/imxrt.c

@@ -2,7 +2,8 @@
 
 #if MG_ENABLE_TCPIP && \
   (defined(MG_ENABLE_DRIVER_IMXRT10) && MG_ENABLE_DRIVER_IMXRT10) || \
-  (defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11)
+  (defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11) || \
+  (defined(MG_ENABLE_DRIVER_MCXE) && MG_ENABLE_DRIVER_MCXE)
 struct imxrt_enet {
   volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3],
       ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR,
@@ -31,9 +32,12 @@ struct imxrt_enet {
 #if defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11
 #define ENET ((struct imxrt_enet *) (uintptr_t) 0x40424000U)
 #define ETH_DESC_CNT 5     // Descriptors count
-#else
+#elif defined(MG_ENABLE_DRIVER_IMXRT10) && MG_ENABLE_DRIVER_IMXRT10
 #define ENET ((struct imxrt_enet *) (uintptr_t) 0x402D8000U)
 #define ETH_DESC_CNT 4     // Descriptors count
+#else // MG_ENABLE_DRIVER_MCXE
+#define ENET ((struct imxrt_enet *) (uintptr_t) 0x40079000U)
+#define ETH_DESC_CNT 4     // Descriptor count
 #endif
 
 #define ETH_PKT_SIZE 1536  // Max frame size, 64-bit aligned
@@ -44,15 +48,12 @@ struct enet_desc {
   uint32_t *buffer;  // Data ptr
 };
 
-// TODO(): handle these in a portable compiler-independent CMSIS-friendly way
-#define MG_64BYTE_ALIGNED __attribute__((aligned((64U))))
-
 // Descriptors: in non-cached area (TODO(scaprile)), (37.5.1.22.2 37.5.1.23.2)
 // Buffers: 64-byte aligned (37.3.14)
-static volatile struct enet_desc s_rxdesc[ETH_DESC_CNT] MG_64BYTE_ALIGNED;
+static volatile struct enet_desc s_rxdesc[ETH_DESC_CNT] MG_ETH_RAM MG_64BYTE_ALIGNED;
-static volatile struct enet_desc s_txdesc[ETH_DESC_CNT] MG_64BYTE_ALIGNED;
+static volatile struct enet_desc s_txdesc[ETH_DESC_CNT] MG_ETH_RAM MG_64BYTE_ALIGNED;
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BYTE_ALIGNED;
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_64BYTE_ALIGNED;
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BYTE_ALIGNED;
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_64BYTE_ALIGNED;
 static struct mg_tcpip_if *s_ifp;  // MIP interface
 
 static uint16_t enet_read_phy(uint8_t addr, uint8_t reg) {
@@ -189,9 +190,14 @@ static bool mg_tcpip_driver_imxrt_poll(struct mg_tcpip_if *ifp, bool s1) {
   return up;
 }
 
-void ENET_IRQHandler(void);
 static uint32_t s_rxno;
+#if !defined(MG_ENABLE_DRIVER_MCXE)
+void ENET_IRQHandler(void);
 void ENET_IRQHandler(void) {
+#else
+void ENET_Receive_IRQHandler(void);
+void ENET_Receive_IRQHandler(void) {
+#endif
   ENET->EIR = MG_BIT(25);  // Ack IRQ
   // Frame received, loop
   for (uint32_t i = 0; i < 10; i++) {  // read as they arrive but not forever

src/drivers/imxrt.h

@@ -2,7 +2,8 @@
 
 #if MG_ENABLE_TCPIP && \
   (defined(MG_ENABLE_DRIVER_IMXRT10) && MG_ENABLE_DRIVER_IMXRT10) || \
-  (defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11)
+  (defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11) || \
+  (defined(MG_ENABLE_DRIVER_MCXE) && MG_ENABLE_DRIVER_MCXE)
 
 struct mg_tcpip_driver_imxrt_data {
   // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),

src/drivers/nxp_wifi.c

@@ -0,0 +1,91 @@
+#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_NXP_WIFI) && \
+    MG_ENABLE_DRIVER_NXP_WIFI
+
+#include "drivers/nxp_wifi.h"
+
+bool __attribute__((weak)) netif_init(struct mg_tcpip_if *ifp) {
+  (void) ifp;
+  MG_ERROR(("Please link wifi/port/net contents"));
+  return false;
+}
+size_t __attribute__((weak))
+netif_tx(const void *bfr, size_t len, struct mg_tcpip_if *ifp) {
+  (void) bfr;
+  (void) len;
+  netif_init(ifp);
+  return 0;
+}
+bool __attribute__((weak)) netif_connect(struct mg_wifi_data *wifi) {
+  (void) wifi;
+  return netif_init(NULL);
+}
+bool __attribute__((weak))
+netif_poll(struct mg_tcpip_if *ifp, bool s1, mg_tcpip_event_handler_t evcb) {
+  (void) ifp;
+  (void) s1;
+  (void) evcb;
+  return false;
+}
+
+static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
+
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG &&
+      *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
+
+static bool nxp_wifi_init(struct mg_tcpip_if *ifp) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_nxp_wifi_data *) ifp->driver_data)->wifi;
+  s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
+  ifp->pfn = wifi_cb;
+  if (!netif_init(ifp)) return false;
+  if (wifi->apmode) {
+    return mg_wifi_ap_start(wifi);
+  } else if (wifi->ssid != NULL && wifi->pass != NULL) {
+    return mg_wifi_connect(wifi);
+  }
+  return true;
+}
+
+bool nxp_wifi_poll(struct mg_tcpip_if *ifp, bool s1) {
+  return netif_poll(ifp, s1, mg_tcpip_call);
+}
+
+struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi = {nxp_wifi_init, netif_tx,
+                                                   NULL, nxp_wifi_poll};
+
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
+  return netif_connect(wifi);
+}
+
+bool __attribute__((weak)) mg_wifi_scan(void) {
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_disconnect(void) {
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_ap_start(struct mg_wifi_data *wifi) {
+  (void) wifi;
+  return netif_init(NULL);
+}
+bool __attribute__((weak)) mg_wifi_ap_stop(void) {
+  return netif_init(NULL);
+}
+
+#endif

src/drivers/nxp_wifi.h

@@ -0,0 +1,28 @@
+#pragma once
+
+#if MG_ENABLE_TCPIP  && \
+    defined(MG_ENABLE_DRIVER_NXP_WIFI) && MG_ENABLE_DRIVER_NXP_WIFI
+
+
+struct mg_tcpip_driver_nxp_wifi_data {
+  struct mg_wifi_data wifi;
+};
+
+
+#define MG_TCPIP_DRIVER_INIT(mgr)                                   \
+  do {                                                              \
+    static struct mg_tcpip_driver_nxp_wifi_data driver_data_;       \
+    static struct mg_tcpip_if mif_;                                 \
+    MG_SET_WIFI_CONFIG(&driver_data_);                              \
+    mif_.ip = MG_TCPIP_IP;                                          \
+    mif_.mask = MG_TCPIP_MASK;                                      \
+    mif_.gw = MG_TCPIP_GW;                                          \
+    mif_.driver = &mg_tcpip_driver_nxp_wifi;                        \
+    mif_.driver_data = &driver_data_;                               \
+    mif_.recv_queue.size = 8192;                                    \
+    mif_.mac[0] = 2; /* MAC read from OTP at driver init */         \
+    mg_tcpip_init(mgr, &mif_);                                      \
+    MG_INFO(("Driver: nxp wifi, MAC: %M", mg_print_mac, mif_.mac)); \
+  } while (0)
+
+#endif

src/drivers/phy.c

@@ -53,7 +53,6 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
     default:
       return "unknown";
   }
-  (void) id2;
 }
 
 void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {

src/drivers/pico-w.c

@@ -6,23 +6,41 @@
 #include "pico/stdlib.h"
 
 static struct mg_tcpip_if *s_ifp;
+static uint32_t s_ip, s_mask;
+static bool s_aplink = false, s_scanning = false;
+static bool s_stalink = false, s_connecting = false;
+
+static void wifi_cb(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
+  struct mg_wifi_data *wifi =
+      &((struct mg_tcpip_driver_pico_w_data *) ifp->driver_data)->wifi;
+  if (wifi->apmode && ev == MG_TCPIP_EV_ST_CHG &&
+      *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
+    MG_DEBUG(("Access Point started"));
+    s_ip = ifp->ip, ifp->ip = wifi->apip;
+    s_mask = ifp->mask, ifp->mask = wifi->apmask;
+    ifp->enable_dhcp_client = false;
+    ifp->enable_dhcp_server = true;
+  }
+}
 
 static bool mg_tcpip_driver_pico_w_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
+  struct mg_wifi_data *wifi = &d->wifi;
   s_ifp = ifp;
+  s_ip = ifp->ip;
+  s_mask = ifp->mask;
+  ifp->pfn = wifi_cb;
   if (cyw43_arch_init() != 0)
     return false;  // initialize async_context and WiFi chip
-  if (d->apmode && d->apssid != NULL) {
+  if (wifi->apmode && wifi->apssid != NULL) {
-    MG_DEBUG(("Starting AP '%s' (%u)", d->apssid, d->apchannel));
+    if (!mg_wifi_ap_start(wifi)) return false;
-    if (!mg_wifi_ap_start(d->apssid, d->appass, d->apchannel)) return false;
     cyw43_wifi_get_mac(&cyw43_state, CYW43_ITF_STA, ifp->mac);  // same MAC
   } else {
     cyw43_arch_enable_sta_mode();
     cyw43_wifi_get_mac(&cyw43_state, CYW43_ITF_STA, ifp->mac);
-    if (d->ssid != NULL) {
+    if (wifi->ssid != NULL) {
-      MG_DEBUG(("Connecting to '%s'", d->ssid));
+      return mg_wifi_connect(wifi);
-      return mg_wifi_connect(d->ssid, d->pass);
     } else {
       cyw43_arch_disable_sta_mode();
     }
@@ -35,35 +53,33 @@ static size_t mg_tcpip_driver_pico_w_tx(const void *buf, size_t len,
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
   return cyw43_send_ethernet(&cyw43_state,
-                             d->apmode ? CYW43_ITF_AP : CYW43_ITF_STA, len, buf,
+                             d->wifi.apmode ? CYW43_ITF_AP : CYW43_ITF_STA, len,
-                             false) == 0
+                             buf, false) == 0
              ? len
              : 0;
 }
 
-static bool s_aplink = false, s_scanning = false;
-static bool s_stalink = false, s_connecting = false;
-
 static bool mg_tcpip_driver_pico_w_poll(struct mg_tcpip_if *ifp, bool s1) {
   cyw43_arch_poll();  // not necessary, except when IRQs are disabled (OTA)
   if (s_scanning && !cyw43_wifi_scan_active(&cyw43_state)) {
     MG_VERBOSE(("scan complete"));
     s_scanning = 0;
-    mg_tcpip_call(s_ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
+    mg_tcpip_call(ifp, MG_TCPIP_EV_WIFI_SCAN_END, NULL);
   }
   if (ifp->update_mac_hash_table) {
     // first call to _poll() is after _init(), so this is safe
-    cyw43_wifi_update_multicast_filter(&cyw43_state, (uint8_t *)mcast_addr, true);
+    cyw43_wifi_update_multicast_filter(&cyw43_state, (uint8_t *) mcast_addr,
+                                       true);
     ifp->update_mac_hash_table = false;
   }
   if (!s1) return false;
   struct mg_tcpip_driver_pico_w_data *d =
       (struct mg_tcpip_driver_pico_w_data *) ifp->driver_data;
-  if (d->apmode) return s_aplink;
+  if (d->wifi.apmode) return s_aplink;
   int sdkstate = cyw43_wifi_link_status(&cyw43_state, CYW43_ITF_STA);
   MG_VERBOSE(("conn: %c state: %d", s_connecting ? '1' : '0', sdkstate));
   if (sdkstate < 0 && s_connecting) {
-    mg_tcpip_call(s_ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, &sdkstate);
+    mg_tcpip_call(ifp, MG_TCPIP_EV_WIFI_CONNECT_ERR, &sdkstate);
     s_connecting = false;
   }
   return s_stalink;
@@ -94,7 +110,7 @@ void cyw43_cb_tcpip_set_link_up(cyw43_t *self, int itf) {
 }
 void cyw43_cb_tcpip_set_link_down(cyw43_t *self, int itf) {
   if (itf == CYW43_ITF_AP) {
-     s_aplink = false;
+    s_aplink = false;
   } else {
     s_stalink = false;
     // SDK calls this before we check status, don't clear s_connecting here
@@ -134,9 +150,15 @@ bool mg_wifi_scan(void) {
   return res;
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
+  s_ifp->ip = s_ip;
+  s_ifp->mask = s_mask;
+  if (s_ifp->ip == 0) s_ifp->enable_dhcp_client = true;
+  s_ifp->enable_dhcp_server = false;
   cyw43_arch_enable_sta_mode();
-  int res = cyw43_arch_wifi_connect_async(ssid, pass, CYW43_AUTH_WPA2_AES_PSK);
+  MG_DEBUG(("Connecting to '%s'", wifi->ssid));
+  int res = cyw43_arch_wifi_connect_async(wifi->ssid, wifi->pass,
+                                          CYW43_AUTH_WPA2_AES_PSK);
   MG_VERBOSE(("res: %d", res));
   if (res == 0) s_connecting = true;
   return (res == 0);
@@ -148,9 +170,11 @@ bool mg_wifi_disconnect(void) {
   return true;
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
-  cyw43_wifi_ap_set_channel(&cyw43_state, channel);
+  MG_DEBUG(("Starting AP '%s' (%u)", wifi->apssid, wifi->apchannel));
-  cyw43_arch_enable_ap_mode(ssid, pass, CYW43_AUTH_WPA2_AES_PSK);
+  cyw43_wifi_ap_set_channel(&cyw43_state, wifi->apchannel);
+  cyw43_arch_enable_ap_mode(wifi->apssid, wifi->appass,
+                            CYW43_AUTH_WPA2_AES_PSK);
   return true;
 }
 

src/drivers/pico-w.h

@@ -8,14 +8,7 @@
 #include "pico/unique_id.h"     // keep this include
 
 struct mg_tcpip_driver_pico_w_data {
-  char *ssid;
+  struct mg_wifi_data wifi;
-  char *pass;
-  char *apssid;
-  char *appass;
-  uint8_t security; // TBD
-  uint8_t apsecurity; // TBD
-  uint8_t apchannel;
-  bool apmode;      // start in AP mode; 'false' starts connection to 'ssid' if not NULL
 };
 
 #define MG_TCPIP_DRIVER_INIT(mgr)                                 \

src/drivers/ra.c

@@ -38,16 +38,12 @@ struct ra_edmac {
 #define ETH_PKT_SIZE 1536  // Max frame size, multiple of 32
 #define ETH_DESC_CNT 4     // Descriptors count
 
-// TODO(): handle these in a portable compiler-independent CMSIS-friendly way
-#define MG_16BYTE_ALIGNED __attribute__((aligned((16U))))
-#define MG_32BYTE_ALIGNED __attribute__((aligned((32U))))
-
 // Descriptors: 16-byte aligned
 // Buffers: 32-byte aligned (27.3.1)
-static volatile uint32_t s_rxdesc[ETH_DESC_CNT][4] MG_16BYTE_ALIGNED;
+static volatile uint32_t s_rxdesc[ETH_DESC_CNT][4] MG_ETH_RAM MG_16BYTE_ALIGNED;
-static volatile uint32_t s_txdesc[ETH_DESC_CNT][4] MG_16BYTE_ALIGNED;
+static volatile uint32_t s_txdesc[ETH_DESC_CNT][4] MG_ETH_RAM MG_16BYTE_ALIGNED;
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_32BYTE_ALIGNED;
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_32BYTE_ALIGNED;
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_32BYTE_ALIGNED;
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_32BYTE_ALIGNED;
 static struct mg_tcpip_if *s_ifp;  // MIP interface
 
 // fastest is 3 cycles (SUB + BNE) on a 3-stage pipeline or equivalent

src/drivers/rw612.c

@@ -26,17 +26,17 @@ struct ENET_Type {
       CHANNEL_TCSR[4], CHANNEL_TCCR[4];
 };
 
+#undef ENET
 #define ENET ((struct ENET_Type *) 0x40138000)
 
 #define ETH_PKT_SIZE 1536  // Max frame size
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 2           // Descriptor size (words)
 
-#define MG_8BYTE_ALIGNED __attribute__((aligned((8U))))
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_8BYTE_ALIGNED;
+static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
+static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
 static uint8_t s_txno;  // Current TX descriptor
 static uint8_t s_rxno;  // Current RX descriptor
 

src/drivers/stm32f.c

@@ -22,10 +22,10 @@ struct stm32f_eth {
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 4           // Descriptor size (words)
 
-static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS];      // RX descriptors
+static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM;      // RX descriptors
-static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS];      // TX descriptors
+static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM;      // TX descriptors
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];  // RX ethernet buffers
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM;  // RX ethernet buffers
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];  // TX ethernet buffers
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM;  // TX ethernet buffers
 static uint8_t s_txno;                               // Current TX descriptor
 static uint8_t s_rxno;                               // Current RX descriptor
 

src/drivers/stm32h.c

@@ -1,8 +1,9 @@
 #include "net_builtin.h"
 
-#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
+#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \
+                        MG_ENABLE_DRIVER_STM32N)
 // STM32H: vendor modded single-queue Synopsys v4.2
-// MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
+// STM32N, MCXNx4x: dual-queue Synopsys v5.2 with no hash table option
 // RT1170 ENET_QOS: quad-queue Synopsys v5.1
 struct synopsys_enet_qos {
   volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
@@ -41,17 +42,19 @@ struct synopsys_enet_qos {
                                              0x8000UL))
 #elif MG_ENABLE_DRIVER_MCXN
 #define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
+#elif MG_ENABLE_DRIVER_STM32N
+#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x48036000UL)
 #endif
 
 #define ETH_PKT_SIZE 1540  // Max frame size
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 4           // Descriptor size (words)
 
-static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS];  // RX descriptors
+static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS];  // TX descriptors
+static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];       // RX ethernet buffers
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];       // TX ethernet buffers
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static struct mg_tcpip_if *s_ifp;                         // MIP interface
+static struct mg_tcpip_if *s_ifp;         // MIP interface
 
 static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
   ETH->MACMDIOAR &= (0xF << 8);
@@ -77,12 +80,14 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
   uint8_t phy_conf = d == NULL ? MG_PHY_CLOCKS_MAC : d->phy_conf;
 
   // Init RX descriptors
+  memset((char *) s_rxdesc, 0, sizeof(s_rxdesc));  // manual init
   for (int i = 0; i < ETH_DESC_CNT; i++) {
     s_rxdesc[i][0] = (uint32_t) (uintptr_t) s_rxbuf[i];  // Point to data buffer
     s_rxdesc[i][3] = MG_BIT(31) | MG_BIT(30) | MG_BIT(24);  // OWN, IOC, BUF1V
   }
 
   // Init TX descriptors
+  memset((char *) s_txdesc, 0, sizeof(s_txdesc));  // manual init
   for (int i = 0; i < ETH_DESC_CNT; i++) {
     s_txdesc[i][0] = (uint32_t) (uintptr_t) s_txbuf[i];  // Buf pointer
   }
@@ -102,7 +107,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
   ETH->DMASBMR |= MG_BIT(12);  // AAL NOTE(scaprile): is this actually needed
   ETH->MACIER = 0;  // Do not enable additional irq sources (reset value)
   ETH->MACTFCR = MG_BIT(7);  // Disable zero-quanta pause
-#if !MG_ENABLE_DRIVER_MCXN
+#if MG_ENABLE_DRIVER_STM32H
   ETH->MACPFR = MG_BIT(10);  // Perfect filtering
 #endif
   struct mg_phy phy = {eth_read_phy, eth_write_phy};
@@ -171,7 +176,7 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
 }
 
 static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
-#if MG_ENABLE_DRIVER_MCXN
+#if MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
   ETH->MACPFR = MG_BIT(4);  // Pass Multicast (pass all multicast frames)
 #else
   // TODO(): read database, rebuild hash table
@@ -182,7 +187,7 @@ static void mg_tcpip_driver_stm32h_update_hash_table(struct mg_tcpip_if *ifp) {
   ETH->MACA1HR = (uint32_t) mcast_addr[5] << 8 | (uint32_t) mcast_addr[4];
   ETH->MACA1HR |= MG_BIT(31);  // AE
 #endif
-(void) ifp;
+  (void) ifp;
 }
 
 static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
@@ -216,9 +221,12 @@ static uint32_t s_rxno;
 #if MG_ENABLE_DRIVER_MCXN
 void ETHERNET_IRQHandler(void);
 void ETHERNET_IRQHandler(void) {
-#else
+#elif MG_ENABLE_DRIVER_STM32H
 void ETH_IRQHandler(void);
 void ETH_IRQHandler(void) {
+#else
+void ETH1_IRQHandler(void);
+void ETH1_IRQHandler(void) {
 #endif
   if (ETH->DMACSR & MG_BIT(6)) {           // Frame received, loop
     ETH->DMACSR = MG_BIT(15) | MG_BIT(6);  // Clear flag

src/drivers/stm32h.h

@@ -7,7 +7,10 @@
 #if !defined(MG_ENABLE_DRIVER_MCXN)
 #define MG_ENABLE_DRIVER_MCXN 0
 #endif
-#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN
+#if !defined(MG_ENABLE_DRIVER_STM32N)
+#define MG_ENABLE_DRIVER_STM32N 0
+#endif
+#if MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || MG_ENABLE_DRIVER_STM32N
 
 struct mg_tcpip_driver_stm32h_data {
   // MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
@@ -46,6 +49,18 @@ struct mg_tcpip_driver_stm32h_data {
 #define MG_ENABLE_ETH_IRQ()
 #endif
 
+#if MG_ENABLE_IPV6
+#define MG_IPV6_INIT(mif)                                         \
+  do {                                                            \
+    memcpy(mif.ip6ll, (uint8_t[16]) MG_TCPIP_IPV6_LINKLOCAL, 16);     \
+    memcpy(mif.ip6, (uint8_t[16]) MG_TCPIP_GLOBAL, 16);           \
+    memcpy(mif.gw6, (uint8_t[16]) MG_TCPIP_GW6, 16);              \
+    mif.prefix_len = MG_TCPIP_PREFIX_LEN;                        \
+  } while(0)
+#else
+#define MG_IPV6_INIT(mif)
+#endif
+
 #define MG_TCPIP_DRIVER_INIT(mgr)                                 \
   do {                                                            \
     static struct mg_tcpip_driver_stm32h_data driver_data_;       \
@@ -59,6 +74,7 @@ struct mg_tcpip_driver_stm32h_data {
     mif_.driver = &mg_tcpip_driver_stm32h;                        \
     mif_.driver_data = &driver_data_;                             \
     MG_SET_MAC_ADDRESS(mif_.mac);                                 \
+    MG_IPV6_INIT(mif_);                                           \
     mg_tcpip_init(mgr, &mif_);                                    \
     MG_ENABLE_ETH_IRQ();                                          \
     MG_INFO(("Driver: stm32h, MAC: %M", mg_print_mac, mif_.mac)); \

src/drivers/tm4c.c

@@ -111,11 +111,11 @@ static int guess_mdc_cr(void) {
   uint8_t crs[] = {2, 3, 0, 1};      // EMAC->MACMIIAR::CR values
   uint8_t div[] = {16, 26, 42, 62};  // Respective HCLK dividers
   uint32_t sysclk = get_sysclk();    // Guess system SYSCLK
-  int result = -1;                   // Invalid CR value
+  int i, result = -1;                // Invalid CR value
   if (sysclk < 25000000) {
     MG_ERROR(("SYSCLK too low"));
   } else {
-    for (int i = 0; i < 4; i++) {
+    for (i = 0; i < 4; i++) {
       if (sysclk / div[i] <= 2375000UL /* 2.5MHz - 5% */) {
         result = crs[i];
         break;
@@ -130,10 +130,11 @@ static int guess_mdc_cr(void) {
 static bool mg_tcpip_driver_tm4c_init(struct mg_tcpip_if *ifp) {
   struct mg_tcpip_driver_tm4c_data *d =
       (struct mg_tcpip_driver_tm4c_data *) ifp->driver_data;
+  int i;
   s_ifp = ifp;
 
   // Init RX descriptors
-  for (int i = 0; i < ETH_DESC_CNT; i++) {
+  for (i = 0; i < ETH_DESC_CNT; i++) {
     s_rxdesc[i][0] = MG_BIT(31);                         // Own
     s_rxdesc[i][1] = sizeof(s_rxbuf[i]) | MG_BIT(14);    // 2nd address chained
     s_rxdesc[i][2] = (uint32_t) (uintptr_t) s_rxbuf[i];  // Point to data buffer
@@ -143,7 +144,7 @@ static bool mg_tcpip_driver_tm4c_init(struct mg_tcpip_if *ifp) {
   }
 
   // Init TX descriptors
-  for (int i = 0; i < ETH_DESC_CNT; i++) {
+  for (i = 0; i < ETH_DESC_CNT; i++) {
     s_txdesc[i][2] = (uint32_t) (uintptr_t) s_txbuf[i];  // Buf pointer
     s_txdesc[i][3] =
         (uint32_t) (uintptr_t) s_txdesc[(i + 1) % ETH_DESC_CNT];  // Chain
@@ -204,7 +205,6 @@ static size_t mg_tcpip_driver_tm4c_tx(const void *buf, size_t len,
   EMAC->EMACDMARIS = MG_BIT(2) | MG_BIT(5);  // Clear any prior TU/UNF
   EMAC->EMACTXPOLLD = 0;                     // and resume
   return len;
-  (void) ifp;
 }
 
 static void mg_tcpip_driver_tm4c_update_hash_table(struct mg_tcpip_if *ifp) {
@@ -245,9 +245,10 @@ static bool mg_tcpip_driver_tm4c_poll(struct mg_tcpip_if *ifp, bool s1) {
 void EMAC0_IRQHandler(void);
 static uint32_t s_rxno;
 void EMAC0_IRQHandler(void) {
+  int i;
   if (EMAC->EMACDMARIS & MG_BIT(6)) {           // Frame received, loop
     EMAC->EMACDMARIS = MG_BIT(16) | MG_BIT(6);  // Clear flag
-    for (uint32_t i = 0; i < 10; i++) {  // read as they arrive but not forever
+    for (i = 0; i < 10; i++) {  // read as they arrive but not forever
       if (s_rxdesc[s_rxno][0] & MG_BIT(31)) break;  // exit when done
       if (((s_rxdesc[s_rxno][0] & (MG_BIT(8) | MG_BIT(9))) ==
            (MG_BIT(8) | MG_BIT(9))) &&

src/drivers/xmc.c

@@ -35,18 +35,12 @@ struct ETH_GLOBAL_TypeDef {
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 4           // Descriptor size (words)
 
-#ifndef ETH_RAM_SECTION
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM;
-// if no section is specified, then the data will be placed in the default
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM;
-// bss section
-#define ETH_RAM_SECTION
-#endif
-
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] ETH_RAM_SECTION;
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] ETH_RAM_SECTION;
 static uint32_t s_rxdesc[ETH_DESC_CNT]
-                        [ETH_DS] ETH_RAM_SECTION;  // RX descriptors
+                        [ETH_DS] MG_ETH_RAM;  // RX descriptors
 static uint32_t s_txdesc[ETH_DESC_CNT]
-                        [ETH_DS] ETH_RAM_SECTION;  // TX descriptors
+                        [ETH_DS] MG_ETH_RAM;  // TX descriptors
 static uint8_t s_txno;                             // Current TX descriptor
 static uint8_t s_rxno;                             // Current RX descriptor
 

src/drivers/xmc7.c

@@ -59,15 +59,12 @@ struct ETH_Type {
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 2           // Descriptor size (words)
 
-// TODO(): handle these in a portable compiler-independent CMSIS-friendly way
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM;
-#define MG_8BYTE_ALIGNED __attribute__((aligned((8U))))
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM;
-
+static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
+static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
+static uint8_t s_txno;  // Current TX descriptor
-static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
+static uint8_t s_rxno;  // Current RX descriptor
-static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_8BYTE_ALIGNED;
-static uint8_t s_txno MG_8BYTE_ALIGNED;  // Current TX descriptor
-static uint8_t s_rxno MG_8BYTE_ALIGNED;  // Current RX descriptor
 
 static struct mg_tcpip_if *s_ifp;  // MIP interface
 enum { MG_PHY_ADDR = 0, MG_PHYREG_BCR = 0, MG_PHYREG_BSR = 1 };

src/http.c

@@ -346,14 +346,14 @@ int mg_http_parse(const char *s, size_t len, struct mg_http_message *hm) {
 static void mg_http_vprintf_chunk(struct mg_connection *c, const char *fmt,
                                   va_list *ap) {
   size_t len = c->send.len;
-  mg_send(c, "        \r\n", 10);
+  if (!mg_send(c, "        \r\n", 10)) mg_error(c, "OOM");
   mg_vxprintf(mg_pfn_iobuf, &c->send, fmt, ap);
   if (c->send.len >= len + 10) {
     mg_snprintf((char *) c->send.buf + len, 9, "%08lx", c->send.len - len - 10);
     c->send.buf[len + 8] = '\r';
     if (c->send.len == len + 10) c->is_resp = 0;  // Last chunk, reset marker
   }
-  mg_send(c, "\r\n", 2);
+  if (!mg_send(c, "\r\n", 2)) mg_error(c, "OOM");
 }
 
 void mg_http_printf_chunk(struct mg_connection *c, const char *fmt, ...) {
@@ -365,8 +365,7 @@ void mg_http_printf_chunk(struct mg_connection *c, const char *fmt, ...) {
 
 void mg_http_write_chunk(struct mg_connection *c, const char *buf, size_t len) {
   mg_printf(c, "%lx\r\n", (unsigned long) len);
-  mg_send(c, buf, len);
+  if (!mg_send(c, buf, len) || !mg_send(c, "\r\n", 2)) mg_error(c, "OOM");
-  mg_send(c, "\r\n", 2);
   if (len == 0) c->is_resp = 0;
 }
 

src/http.h

@@ -40,7 +40,6 @@ int mg_http_parse(const char *s, size_t len, struct mg_http_message *);
 int mg_http_get_request_len(const unsigned char *buf, size_t buf_len);
 void mg_http_printf_chunk(struct mg_connection *cnn, const char *fmt, ...);
 void mg_http_write_chunk(struct mg_connection *c, const char *buf, size_t len);
-void mg_http_delete_chunk(struct mg_connection *c, struct mg_http_message *hm);
 struct mg_connection *mg_http_listen(struct mg_mgr *, const char *url,
                                      mg_event_handler_t fn, void *fn_data);
 struct mg_connection *mg_http_connect(struct mg_mgr *, const char *url,

src/iobuf.c

@@ -1,5 +1,5 @@
-#include "arch.h"
 #include "iobuf.h"
+#include "arch.h"
 #include "log.h"
 #include "util.h"
 
@@ -7,8 +7,8 @@ static size_t roundup(size_t size, size_t align) {
   return align == 0 ? size : (size + align - 1) / align * align;
 }
 
-int mg_iobuf_resize(struct mg_iobuf *io, size_t new_size) {
+bool mg_iobuf_resize(struct mg_iobuf *io, size_t new_size) {
-  int ok = 1;
+  bool ok = true;
   new_size = roundup(new_size, io->align);
   if (new_size == 0) {
     mg_bzero(io->buf, io->size);
@@ -25,15 +25,16 @@ int mg_iobuf_resize(struct mg_iobuf *io, size_t new_size) {
       mg_free(io->buf);
       io->buf = (unsigned char *) p;
       io->size = new_size;
+      io->len = len;
     } else {
-      ok = 0;
+      ok = false;
       MG_ERROR(("%lld->%lld", (uint64_t) io->size, (uint64_t) new_size));
     }
   }
   return ok;
 }
 
-int mg_iobuf_init(struct mg_iobuf *io, size_t size, size_t align) {
+bool mg_iobuf_init(struct mg_iobuf *io, size_t size, size_t align) {
   io->buf = NULL;
   io->align = align;
   io->size = io->len = 0;

src/iobuf.h

@@ -9,8 +9,8 @@ struct mg_iobuf {
   size_t align;        // Alignment during allocation
 };
 
-int mg_iobuf_init(struct mg_iobuf *, size_t, size_t);
+bool mg_iobuf_init(struct mg_iobuf *, size_t, size_t);
-int mg_iobuf_resize(struct mg_iobuf *, size_t);
+bool mg_iobuf_resize(struct mg_iobuf *, size_t);
 void mg_iobuf_free(struct mg_iobuf *);
 size_t mg_iobuf_add(struct mg_iobuf *, size_t, const void *, size_t);
 size_t mg_iobuf_del(struct mg_iobuf *, size_t ofs, size_t len);

src/mqtt.c

@@ -46,8 +46,8 @@ static const struct mg_mqtt_pmap s_prop_map[] = {
     {MQTT_PROP_SUBSCRIPTION_IDENTIFIER_AVAILABLE, MQTT_PROP_TYPE_BYTE},
     {MQTT_PROP_SHARED_SUBSCRIPTION_AVAILABLE, MQTT_PROP_TYPE_BYTE}};
 
-void mg_mqtt_send_header(struct mg_connection *c, uint8_t cmd, uint8_t flags,
+static bool mqtt_send_header(struct mg_connection *c, uint8_t cmd,
-                         uint32_t len) {
+                             uint8_t flags, uint32_t len) {
   uint8_t buf[1 + sizeof(len)], *vlen = &buf[1];
   buf[0] = (uint8_t) ((cmd << 4) | flags);
   do {
@@ -56,15 +56,20 @@ void mg_mqtt_send_header(struct mg_connection *c, uint8_t cmd, uint8_t flags,
     if (len > 0) *vlen |= 0x80;
     vlen++;
   } while (len > 0 && vlen < &buf[sizeof(buf)]);
-  mg_send(c, buf, (size_t) (vlen - buf));
+  return mg_send(c, buf, (size_t) (vlen - buf));
 }
 
-static void mg_send_u16(struct mg_connection *c, uint16_t value) {
+void mg_mqtt_send_header(struct mg_connection *c, uint8_t cmd, uint8_t flags,
-  mg_send(c, &value, sizeof(value));
+                         uint32_t len) {
+  if (!mqtt_send_header(c, cmd, flags, len)) mg_error(c, "OOM");
 }
 
-static void mg_send_u32(struct mg_connection *c, uint32_t value) {
+static bool mg_send_u16(struct mg_connection *c, uint16_t value) {
-  mg_send(c, &value, sizeof(value));
+  return mg_send(c, &value, sizeof(value));
+}
+
+static bool mg_send_u32(struct mg_connection *c, uint32_t value) {
+  return mg_send(c, &value, sizeof(value));
 }
 
 static uint8_t varint_size(size_t length) {
@@ -157,46 +162,50 @@ static size_t get_props_size(struct mg_mqtt_prop *props, size_t count) {
   return size;
 }
 
-static void mg_send_mqtt_properties(struct mg_connection *c,
+static bool mg_send_mqtt_properties(struct mg_connection *c,
                                     struct mg_mqtt_prop *props, size_t nprops) {
   size_t total_size = get_properties_length(props, nprops);
   uint8_t buf_v[4] = {0, 0, 0, 0};
   uint8_t buf[4] = {0, 0, 0, 0};
   size_t i, len = encode_varint(buf, total_size);
 
-  mg_send(c, buf, (size_t) len);
+  if (!mg_send(c, buf, (size_t) len)) return false;
   for (i = 0; i < nprops; i++) {
-    mg_send(c, &props[i].id, sizeof(props[i].id));
+    if (!mg_send(c, &props[i].id, sizeof(props[i].id))) return false;
     switch (mqtt_prop_type_by_id(props[i].id)) {
       case MQTT_PROP_TYPE_STRING_PAIR:
-        mg_send_u16(c, mg_htons((uint16_t) props[i].key.len));
+        if (!mg_send_u16(c, mg_htons((uint16_t) props[i].key.len)) ||
-        mg_send(c, props[i].key.buf, props[i].key.len);
+            !mg_send(c, props[i].key.buf, props[i].key.len) ||
-        mg_send_u16(c, mg_htons((uint16_t) props[i].val.len));
+            !mg_send_u16(c, mg_htons((uint16_t) props[i].val.len)) ||
-        mg_send(c, props[i].val.buf, props[i].val.len);
+            !mg_send(c, props[i].val.buf, props[i].val.len))
+          return false;
         break;
       case MQTT_PROP_TYPE_BYTE:
-        mg_send(c, &props[i].iv, sizeof(uint8_t));
+        if (!mg_send(c, &props[i].iv, sizeof(uint8_t))) return false;
         break;
       case MQTT_PROP_TYPE_SHORT:
-        mg_send_u16(c, mg_htons((uint16_t) props[i].iv));
+        if (!mg_send_u16(c, mg_htons((uint16_t) props[i].iv))) return false;
         break;
       case MQTT_PROP_TYPE_INT:
-        mg_send_u32(c, mg_htonl((uint32_t) props[i].iv));
+        if (!mg_send_u32(c, mg_htonl((uint32_t) props[i].iv))) return false;
         break;
       case MQTT_PROP_TYPE_STRING:
-        mg_send_u16(c, mg_htons((uint16_t) props[i].val.len));
+        if (!mg_send_u16(c, mg_htons((uint16_t) props[i].val.len)) ||
-        mg_send(c, props[i].val.buf, props[i].val.len);
+            !mg_send(c, props[i].val.buf, props[i].val.len))
+          return false;
         break;
       case MQTT_PROP_TYPE_BINARY_DATA:
-        mg_send_u16(c, mg_htons((uint16_t) props[i].val.len));
+        if (!mg_send_u16(c, mg_htons((uint16_t) props[i].val.len)) ||
-        mg_send(c, props[i].val.buf, props[i].val.len);
+            !mg_send(c, props[i].val.buf, props[i].val.len))
+          return false;
         break;
       case MQTT_PROP_TYPE_VARIABLE_INT:
         len = encode_varint(buf_v, props[i].iv);
-        mg_send(c, buf_v, (size_t) len);
+        if (!mg_send(c, buf_v, (size_t) len)) return false;
         break;
     }
   }
+  return true;
 }
 
 size_t mg_mqtt_next_prop(struct mg_mqtt_message *msg, struct mg_mqtt_prop *prop,
@@ -289,33 +298,41 @@ void mg_mqtt_login(struct mg_connection *c, const struct mg_mqtt_opts *opts) {
       total_len += get_props_size(opts->will_props, opts->num_will_props);
   }
 
-  mg_mqtt_send_header(c, MQTT_CMD_CONNECT, 0, (uint32_t) total_len);
-  mg_send(c, hdr, sizeof(hdr));
   // keepalive == 0 means "do not disconnect us!"
-  mg_send_u16(c, mg_htons((uint16_t) opts->keepalive));
+  if (!mqtt_send_header(c, MQTT_CMD_CONNECT, 0, (uint32_t) total_len) ||
+      !mg_send(c, hdr, sizeof(hdr)) ||
+      !mg_send_u16(c, mg_htons((uint16_t) opts->keepalive)))
+    goto fail;
 
-  if (c->is_mqtt5) mg_send_mqtt_properties(c, opts->props, opts->num_props);
+  if (c->is_mqtt5 && !mg_send_mqtt_properties(c, opts->props, opts->num_props))
+    goto fail;
 
-  mg_send_u16(c, mg_htons((uint16_t) cid.len));
+  if (!mg_send_u16(c, mg_htons((uint16_t) cid.len)) ||
-  mg_send(c, cid.buf, cid.len);
+      !mg_send(c, cid.buf, cid.len))
+    goto fail;
 
   if (hdr[7] & MQTT_HAS_WILL) {
-    if (c->is_mqtt5)
+    if (c->is_mqtt5 &&
-      mg_send_mqtt_properties(c, opts->will_props, opts->num_will_props);
+        !mg_send_mqtt_properties(c, opts->will_props, opts->num_will_props))
+      goto fail;
 
-    mg_send_u16(c, mg_htons((uint16_t) opts->topic.len));
+    if (!mg_send_u16(c, mg_htons((uint16_t) opts->topic.len)) ||
-    mg_send(c, opts->topic.buf, opts->topic.len);
+        !mg_send(c, opts->topic.buf, opts->topic.len) ||
-    mg_send_u16(c, mg_htons((uint16_t) opts->message.len));
+        !mg_send_u16(c, mg_htons((uint16_t) opts->message.len)) ||
-    mg_send(c, opts->message.buf, opts->message.len);
+        !mg_send(c, opts->message.buf, opts->message.len))
-  }
+      goto fail;
-  if (opts->user.len > 0) {
-    mg_send_u16(c, mg_htons((uint16_t) opts->user.len));
-    mg_send(c, opts->user.buf, opts->user.len);
-  }
-  if (opts->pass.len > 0) {
-    mg_send_u16(c, mg_htons((uint16_t) opts->pass.len));
-    mg_send(c, opts->pass.buf, opts->pass.len);
   }
+  if (opts->user.len > 0 &&
+      (!mg_send_u16(c, mg_htons((uint16_t) opts->user.len)) ||
+       !mg_send(c, opts->user.buf, opts->user.len)))
+    goto fail;
+  if (opts->pass.len > 0 &&
+      (!mg_send_u16(c, mg_htons((uint16_t) opts->pass.len)) ||
+       !mg_send(c, opts->pass.buf, opts->pass.len)))
+    goto fail;
+  return;
+fail:
+  mg_error(c, "OOM");
 }
 
 uint16_t mg_mqtt_pub(struct mg_connection *c, const struct mg_mqtt_opts *opts) {
@@ -330,20 +347,28 @@ uint16_t mg_mqtt_pub(struct mg_connection *c, const struct mg_mqtt_opts *opts) {
   if (c->is_mqtt5) len += get_props_size(opts->props, opts->num_props);
 
   if (opts->qos > 0 && id != 0) flags |= 1 << 3;
-  mg_mqtt_send_header(c, MQTT_CMD_PUBLISH, flags, (uint32_t) len);
+  if (!mqtt_send_header(c, MQTT_CMD_PUBLISH, flags, (uint32_t) len) ||
-  mg_send_u16(c, mg_htons((uint16_t) opts->topic.len));
+      !mg_send_u16(c, mg_htons((uint16_t) opts->topic.len)) ||
-  mg_send(c, opts->topic.buf, opts->topic.len);
+      !mg_send(c, opts->topic.buf, opts->topic.len))
+    goto fail;
   if (opts->qos > 0) {  // need to send 'id' field
     if (id == 0) {      // generate new one if not resending
       if (++c->mgr->mqtt_id == 0) ++c->mgr->mqtt_id;
       id = c->mgr->mqtt_id;
     }
-    mg_send_u16(c, mg_htons(id));
+    if (!mg_send_u16(c, mg_htons(id))) goto fail;
   }
 
-  if (c->is_mqtt5) mg_send_mqtt_properties(c, opts->props, opts->num_props);
+  if (c->is_mqtt5 && !mg_send_mqtt_properties(c, opts->props, opts->num_props))
+    goto fail;
 
-  if (opts->message.len > 0) mg_send(c, opts->message.buf, opts->message.len);
+  if (opts->message.len > 0 &&
+      !mg_send(c, opts->message.buf, opts->message.len))
+    goto fail;
+  return id;
+
+fail:
+  mg_error(c, "OOM");
   return id;
 }
 
@@ -352,14 +377,20 @@ void mg_mqtt_sub(struct mg_connection *c, const struct mg_mqtt_opts *opts) {
   size_t plen = c->is_mqtt5 ? get_props_size(opts->props, opts->num_props) : 0;
   size_t len = 2 + opts->topic.len + 2 + 1 + plen;
 
-  mg_mqtt_send_header(c, MQTT_CMD_SUBSCRIBE, 2, (uint32_t) len);
+  if (!mqtt_send_header(c, MQTT_CMD_SUBSCRIBE, 2, (uint32_t) len)) goto fail;
   if (++c->mgr->mqtt_id == 0) ++c->mgr->mqtt_id;
-  mg_send_u16(c, mg_htons(c->mgr->mqtt_id));
+  if (!mg_send_u16(c, mg_htons(c->mgr->mqtt_id))) goto fail;
-  if (c->is_mqtt5) mg_send_mqtt_properties(c, opts->props, opts->num_props);
 
-  mg_send_u16(c, mg_htons((uint16_t) opts->topic.len));
+  if (c->is_mqtt5 && !mg_send_mqtt_properties(c, opts->props, opts->num_props))
-  mg_send(c, opts->topic.buf, opts->topic.len);
+    goto fail;
-  mg_send(c, &qos_, sizeof(qos_));
+
+  if (!mg_send_u16(c, mg_htons((uint16_t) opts->topic.len)) ||
+      !mg_send(c, opts->topic.buf, opts->topic.len) ||
+      !mg_send(c, &qos_, sizeof(qos_)))
+    goto fail;
+  return;
+fail:
+  mg_error(c, "OOM");
 }
 
 int mg_mqtt_parse(const uint8_t *buf, size_t len, uint8_t version,
@@ -466,15 +497,16 @@ static void mqtt_cb(struct mg_connection *c, int ev, void *ev_data) {
               uint32_t remaining_len = sizeof(id);
               if (c->is_mqtt5) remaining_len += 2;  // 3.4.2
 
-              mg_mqtt_send_header(
+              if (!mqtt_send_header(c,
-                  c,
+                                    (uint8_t) (mm.qos == 2 ? MQTT_CMD_PUBREC
-                  (uint8_t) (mm.qos == 2 ? MQTT_CMD_PUBREC : MQTT_CMD_PUBACK),
+                                                           : MQTT_CMD_PUBACK),
-                  0, remaining_len);
+                                    0, remaining_len) ||
-              mg_send(c, &id, sizeof(id));
+                  !mg_send(c, &id, sizeof(id)))
+                goto fail;
 
               if (c->is_mqtt5) {
                 uint16_t zero = 0;
-                mg_send(c, &zero, sizeof(zero));
+                if (!mg_send(c, &zero, sizeof(zero))) goto fail;
               }
             }
             mg_call(c, MG_EV_MQTT_MSG, &mm);  // let the app handle qos stuff
@@ -483,15 +515,18 @@ static void mqtt_cb(struct mg_connection *c, int ev, void *ev_data) {
           case MQTT_CMD_PUBREC: {  // MQTT5: 3.5.2-1 TODO(): variable header rc
             uint16_t id = mg_ntohs(mm.id);
             uint32_t remaining_len = sizeof(id);  // MQTT5 3.6.2-1
-            mg_mqtt_send_header(c, MQTT_CMD_PUBREL, 2, remaining_len);
+            if (!mqtt_send_header(c, MQTT_CMD_PUBREL, 2,
-            mg_send(c, &id, sizeof(id));  // MQTT5 3.6.1-1, flags = 2
+                                  remaining_len)  // MQTT5 3.6.1-1, flags = 2
+                || !mg_send(c, &id, sizeof(id)))
+              goto fail;
             break;
           }
           case MQTT_CMD_PUBREL: {  // MQTT5: 3.6.2-1 TODO(): variable header rc
             uint16_t id = mg_ntohs(mm.id);
             uint32_t remaining_len = sizeof(id);  // MQTT5 3.7.2-1
-            mg_mqtt_send_header(c, MQTT_CMD_PUBCOMP, 0, remaining_len);
+            if (!mqtt_send_header(c, MQTT_CMD_PUBCOMP, 0, remaining_len) ||
-            mg_send(c, &id, sizeof(id));
+                !mg_send(c, &id, sizeof(id)))
+              goto fail;
             break;
           }
         }
@@ -503,6 +538,9 @@ static void mqtt_cb(struct mg_connection *c, int ev, void *ev_data) {
     }
   }
   (void) ev_data;
+  return;
+fail:
+  mg_error(c, "OOM");
 }
 
 void mg_mqtt_ping(struct mg_connection *nc) {
@@ -517,19 +555,24 @@ void mg_mqtt_disconnect(struct mg_connection *c,
                         const struct mg_mqtt_opts *opts) {
   size_t len = 0;
   if (c->is_mqtt5) len = 1 + get_props_size(opts->props, opts->num_props);
-  mg_mqtt_send_header(c, MQTT_CMD_DISCONNECT, 0, (uint32_t) len);
+  if (!mqtt_send_header(c, MQTT_CMD_DISCONNECT, 0, (uint32_t) len)) goto fail;
 
   if (c->is_mqtt5) {
     uint8_t zero = 0;
-    mg_send(c, &zero, sizeof(zero));  // reason code
+    if (!mg_send(c, &zero, sizeof(zero))  // reason code
-    mg_send_mqtt_properties(c, opts->props, opts->num_props);
+        || !mg_send_mqtt_properties(c, opts->props, opts->num_props))
+      goto fail;
   }
+  return;
+fail:
+  mg_error(c, "OOM");
 }
 
 struct mg_connection *mg_mqtt_connect(struct mg_mgr *mgr, const char *url,
                                       const struct mg_mqtt_opts *opts,
                                       mg_event_handler_t fn, void *fn_data) {
-  struct mg_connection *c = mg_connect_svc(mgr, url, fn, fn_data, mqtt_cb, NULL);
+  struct mg_connection *c =
+      mg_connect_svc(mgr, url, fn, fn_data, mqtt_cb, NULL);
   if (c != NULL) {
     struct mg_mqtt_opts empty;
     memset(&empty, 0, sizeof(empty));

src/net.c

@@ -9,8 +9,14 @@
 
 size_t mg_vprintf(struct mg_connection *c, const char *fmt, va_list *ap) {
   size_t old = c->send.len;
-  mg_vxprintf(mg_pfn_iobuf, &c->send, fmt, ap);
+  size_t expected = mg_vxprintf(mg_pfn_iobuf, &c->send, fmt, ap);
-  return c->send.len - old;
+  size_t actual = c->send.len - old;
+  if (actual != expected) {
+    mg_error(c, "OOM");
+    c->send.len = old;
+    actual = 0;
+  }
+  return actual;
 }
 
 size_t mg_printf(struct mg_connection *c, const char *fmt, ...) {

src/net.h

@@ -14,7 +14,11 @@ struct mg_dns {
 };
 
 struct mg_addr {
-  uint8_t ip[16];    // Holds IPv4 or IPv6 address, in network byte order
+  union {    // Holds IPv4 or IPv6 address, in network byte order
+    uint8_t ip[16];
+    uint32_t ip4;
+    uint64_t ip6[2];
+  };
   uint16_t port;     // TCP or UDP port in network byte order
   uint8_t scope_id;  // IPv6 scope ID
   bool is_ip6;       // True when address is IPv6 address

src/net_builtin.h

@@ -29,10 +29,10 @@ enum {
   MG_TCPIP_EV_WIFI_SCAN_END,    // Wi-Fi scan has finished        NULL
   MG_TCPIP_EV_WIFI_CONNECT_ERR, // Wi-Fi connect has failed       driver and chip specific
   MG_TCPIP_EV_DRIVER,           // Driver event                   driver specific
+  MG_TCPIP_EV_ST6_CHG,          // state6 change                  uint8_t * (&ifp->state6)
   MG_TCPIP_EV_USER              // Starting ID for user events
 };
 
-
 // Network interface
 struct mg_tcpip_if {
   uint8_t mac[6];                  // MAC address. Must be set to a valid MAC
@@ -48,12 +48,20 @@ struct mg_tcpip_if {
   bool update_mac_hash_table;      // Signal drivers to update MAC controller
   struct mg_tcpip_driver *driver;  // Low level driver
   void *driver_data;               // Driver-specific data
+  mg_tcpip_event_handler_t pfn;    // Driver-specific event handler function
   mg_tcpip_event_handler_t fn;     // User-specified event handler function
   struct mg_mgr *mgr;              // Mongoose event manager
   struct mg_queue recv_queue;      // Receive queue
-  char dhcp_name[12];              // Name reported to DHCP, "mip" if unset
+  char dhcp_name[MG_TCPIP_DHCPNAME_SIZE];  // Name for DHCP, "mip" if unset
-  uint16_t mtu;                    // Interface MTU
+  uint16_t mtu;                            // Interface MTU
 #define MG_TCPIP_MTU_DEFAULT 1500
+#if MG_ENABLE_IPV6
+  uint64_t ip6ll[2], ip6[2];       // IPv6 link-local and global addresses
+  uint8_t prefix_len;              // Prefix length
+  uint64_t gw6[2];                 // Default gateway
+  bool enable_slaac;               // Enable IPv6 address autoconfiguration
+  bool enable_dhcp6_client;        // Enable DCHPv6 client
+#endif
 
   // Internal state, user can use it but should not change it
   uint8_t gwmac[6];             // Router's MAC
@@ -66,14 +74,17 @@ struct mg_tcpip_if {
   volatile uint32_t nrecv;      // Number of received frames
   volatile uint32_t nsent;      // Number of transmitted frames
   volatile uint32_t nerr;       // Number of driver errors
-  uint8_t state;                // Current state
+  uint8_t state;                // Current link and IPv4 state
 #define MG_TCPIP_STATE_DOWN 0   // Interface is down
 #define MG_TCPIP_STATE_UP 1     // Interface is up
 #define MG_TCPIP_STATE_REQ 2    // Interface is up, DHCP REQUESTING state
 #define MG_TCPIP_STATE_IP 3     // Interface is up and has an IP assigned
 #define MG_TCPIP_STATE_READY 4  // Interface has fully come up, ready to work
+#if MG_ENABLE_IPV6
+  uint8_t gw6mac[6];             // IPv6 Router's MAC
+  uint8_t state6;                // Current IPv6 state
+#endif
 };
-
 void mg_tcpip_init(struct mg_mgr *, struct mg_tcpip_if *);
 void mg_tcpip_free(struct mg_tcpip_if *);
 void mg_tcpip_qwrite(void *buf, size_t len, struct mg_tcpip_if *ifp);
@@ -95,6 +106,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_ppp;
 extern struct mg_tcpip_driver mg_tcpip_driver_pico_w;
 extern struct mg_tcpip_driver mg_tcpip_driver_rw612;
 extern struct mg_tcpip_driver mg_tcpip_driver_cyw;
+extern struct mg_tcpip_driver mg_tcpip_driver_nxp_wifi;
 
 // Drivers that require SPI, can use this SPI abstraction
 struct mg_tcpip_spi {
@@ -105,4 +117,41 @@ struct mg_tcpip_spi {
 };
 
 
+// Alignment and memory section requirements
+#ifndef MG_8BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_8BYTE_ALIGNED __attribute__((aligned((8U))))
+#else
+#define MG_8BYTE_ALIGNED
+#endif // compiler
+#endif // 8BYTE_ALIGNED
+
+#ifndef MG_16BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_16BYTE_ALIGNED __attribute__((aligned((16U))))
+#else
+#define MG_16BYTE_ALIGNED
+#endif // compiler
+#endif // 16BYTE_ALIGNED
+
+#ifndef MG_32BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_32BYTE_ALIGNED __attribute__((aligned((32U))))
+#else
+#define MG_32BYTE_ALIGNED
+#endif // compiler
+#endif // 32BYTE_ALIGNED
+
+#ifndef MG_64BYTE_ALIGNED
+#if defined(__GNUC__)
+#define MG_64BYTE_ALIGNED __attribute__((aligned((64U))))
+#else
+#define MG_64BYTE_ALIGNED
+#endif // compiler
+#endif // 64BYTE_ALIGNED
+
+#ifndef MG_ETH_RAM
+#define MG_ETH_RAM
+#endif
+
 #endif

src/printf.c

@@ -2,24 +2,19 @@
 #include "fmt.h"
 #include "util.h"
 
-size_t mg_queue_vprintf(struct mg_queue *q, const char *fmt, va_list *ap) {
-  size_t len = mg_snprintf(NULL, 0, fmt, ap);
-  char *buf;
-  if (len == 0 || mg_queue_book(q, &buf, len + 1) < len + 1) {
-    len = 0;  // Nah. Not enough space
-  } else {
-    len = mg_vsnprintf((char *) buf, len + 1, fmt, ap);
-    mg_queue_add(q, len);
-  }
-  return len;
-}
-
 size_t mg_queue_printf(struct mg_queue *q, const char *fmt, ...) {
-  va_list ap;
+  char *buf;
   size_t len;
-  va_start(ap, fmt);
+  va_list ap1, ap2;
-  len = mg_queue_vprintf(q, fmt, &ap);
+  va_start(ap1, fmt);
-  va_end(ap);
+  len = mg_vsnprintf(NULL, 0, fmt, &ap1);
+  va_end(ap1);
+  if (len == 0 || mg_queue_book(q, &buf, len + 1) < len + 1)
+    return 0;  // Nah. Not enough space
+  va_start(ap2, fmt);
+  len = mg_vsnprintf(buf, len + 1, fmt, &ap2);
+  mg_queue_add(q, len);
+  va_end(ap2);
   return len;
 }
 

src/printf.h

@@ -9,7 +9,6 @@ size_t mg_vsnprintf(char *buf, size_t len, const char *fmt, va_list *ap);
 size_t mg_snprintf(char *, size_t, const char *fmt, ...);
 char *mg_vmprintf(const char *fmt, va_list *ap);
 char *mg_mprintf(const char *fmt, ...);
-size_t mg_queue_vprintf(struct mg_queue *, const char *fmt, va_list *);
 size_t mg_queue_printf(struct mg_queue *, const char *fmt, ...);
 
 // %M print helper functions

src/sock.c

@@ -141,7 +141,9 @@ bool mg_send(struct mg_connection *c, const void *buf, size_t len) {
     iolog(c, (char *) buf, n, false);
     return n > 0;
   } else {
-    return mg_iobuf_add(&c->send, c->send.len, buf, len);
+    return len == 0 || mg_iobuf_add(&c->send, c->send.len, buf, len) > 0;
+    // returning 0 means an OOM condition (iobuf couldn't resize), yet this is
+    // so far recoverable, let the caller decide
   }
 }
 
@@ -163,7 +165,7 @@ static void mg_set_non_blocking_mode(MG_SOCKET_TYPE fd) {
 #elif MG_ARCH == MG_ARCH_THREADX
   // NetxDuo fails to send large blocks of data to the non-blocking sockets
   (void) fd;
-  //fcntl(fd, F_SETFL, O_NONBLOCK);
+  // fcntl(fd, F_SETFL, O_NONBLOCK);
 #elif MG_ARCH == MG_ARCH_TIRTOS
   int val = 0;
   setsockopt(fd, SOL_SOCKET, SO_BLOCKING, &val, sizeof(val));
@@ -181,7 +183,7 @@ static void mg_set_non_blocking_mode(MG_SOCKET_TYPE fd) {
 void mg_multicast_add(struct mg_connection *c, char *ip);
 void mg_multicast_add(struct mg_connection *c, char *ip) {
 #if MG_ENABLE_RL
-#error UNSUPPORTED
+  MG_ERROR(("unsupported"));
 #elif MG_ENABLE_FREERTOS_TCP
   // TODO(): prvAllowIPPacketIPv4()
 #else
@@ -195,9 +197,10 @@ void mg_multicast_add(struct mg_connection *c, char *ip) {
   struct ip_mreq mreq;
   mreq.imr_multiaddr.s_addr = inet_addr(ip);
   mreq.imr_interface.s_addr = mg_htonl(INADDR_ANY);
-  setsockopt(FD(c), IPPROTO_IP, IP_ADD_MEMBERSHIP, (char *) &mreq, sizeof(mreq));
+  setsockopt(FD(c), IPPROTO_IP, IP_ADD_MEMBERSHIP, (char *) &mreq,
-#endif // !Zephyr
+             sizeof(mreq));
-#endif // !lwIP
+#endif  // !Zephyr
+#endif  // !lwIP
 #endif
 }
 
@@ -315,9 +318,9 @@ static void read_conn(struct mg_connection *c) {
       if (n == MG_IO_ERR || n == MG_IO_RESET) {  // Windows, see #3031
         if (c->rtls.len == 0 || m < 0) {
           // Close only when we have fully drained both rtls and TLS buffers
-          c->is_closing = 1;  // or there's nothing we can do about it.
+          c->is_closing = 1;         // or there's nothing we can do about it.
-          if (m < 0) m = MG_IO_ERR; // but return last record data, see #3104
+          if (m < 0) m = MG_IO_ERR;  // but return last record data, see #3104
-        } else { // see #2885
+        } else {                     // see #2885
           // TLS buffer is capped to max record size, even though, there can
           // be more than one record, give TLS a chance to process them.
         }
@@ -338,6 +341,7 @@ static void write_conn(struct mg_connection *c) {
   char *buf = (char *) c->send.buf;
   size_t len = c->send.len;
   long n = c->is_tls ? mg_tls_send(c, buf, len) : mg_io_send(c, buf, len);
+  // TODO(): mg_tls_send() may return 0 forever on steady OOM
   MG_DEBUG(("%lu %ld snd %ld/%ld rcv %ld/%ld n=%ld err=%d", c->id, c->fd,
             (long) c->send.len, (long) c->send.size, (long) c->recv.len,
             (long) c->recv.size, n, MG_SOCK_ERR(n)));
@@ -367,7 +371,7 @@ static void connect_conn(struct mg_connection *c) {
     mg_call(c, MG_EV_CONNECT, NULL);
     MG_EPOLL_MOD(c, 0);
     if (c->is_tls_hs) mg_tls_handshake(c);
-    if (!c->is_tls_hs) c->is_tls = 0; // user did not call mg_tls_init()
+    if (!c->is_tls_hs) c->is_tls = 0;  // user did not call mg_tls_init()
   } else {
     mg_error(c, "socket error");
   }
@@ -419,9 +423,9 @@ void mg_connect_resolved(struct mg_connection *c) {
     rc = connect(FD(c), &usa.sa, slen);  // Attempt to connect
     if (rc == 0) {                       // Success
       setlocaddr(FD(c), &c->loc);
-      mg_call(c, MG_EV_CONNECT, NULL);  // Send MG_EV_CONNECT to the user
+      mg_call(c, MG_EV_CONNECT, NULL);   // Send MG_EV_CONNECT to the user
-      if (!c->is_tls_hs) c->is_tls = 0; // user did not call mg_tls_init()
+      if (!c->is_tls_hs) c->is_tls = 0;  // user did not call mg_tls_init()
-    } else if (MG_SOCK_PENDING(rc)) {   // Need to wait for TCP handshake
+    } else if (MG_SOCK_PENDING(rc)) {    // Need to wait for TCP handshake
       MG_DEBUG(("%lu %ld -> %M pend", c->id, c->fd, mg_print_ip_port, &c->rem));
       c->is_connecting = 1;
     } else {
@@ -481,7 +485,7 @@ static void accept_conn(struct mg_mgr *mgr, struct mg_connection *lsn) {
               &c->rem, mg_print_ip_port, &c->loc));
     mg_call(c, MG_EV_OPEN, NULL);
     mg_call(c, MG_EV_ACCEPT, NULL);
-    if (!c->is_tls_hs) c->is_tls = 0; // user did not call mg_tls_init()
+    if (!c->is_tls_hs) c->is_tls = 0;  // user did not call mg_tls_init()
   }
 }
 

src/ssi.c

@@ -1,6 +1,6 @@
+#include "ssi.h"
 #include "log.h"
 #include "printf.h"
-#include "ssi.h"
 #include "util.h"
 
 #ifndef MG_MAX_SSI_DEPTH
@@ -31,31 +31,35 @@ static char *mg_ssi(const char *path, const char *root, int depth) {
           mg_snprintf(tmp, sizeof(tmp), "%.*s%s", (int) (p - path), path, arg);
           if (depth < MG_MAX_SSI_DEPTH &&
               (data = mg_ssi(tmp, root, depth + 1)) != NULL) {
-            mg_iobuf_add(&b, b.len, data, strlen(data));
+            size_t datalen = strlen(data);
+            size_t ret = mg_iobuf_add(&b, b.len, data, datalen);
             mg_free(data);
+            if (datalen > 0 && ret == 0) goto fail;
           } else {
             MG_ERROR(("%s: file=%s error or too deep", path, arg));
-          }
+          } // TODO(): or OOM at recursive call
         } else if (sscanf(buf, "<!--#include virtual=\"%[^\"]", arg) > 0) {
           char tmp[MG_PATH_MAX + MG_SSI_BUFSIZ + 10], *data;
           mg_snprintf(tmp, sizeof(tmp), "%s%s", root, arg);
           if (depth < MG_MAX_SSI_DEPTH &&
               (data = mg_ssi(tmp, root, depth + 1)) != NULL) {
-            mg_iobuf_add(&b, b.len, data, strlen(data));
+            size_t datalen = strlen(data);
+            size_t ret = mg_iobuf_add(&b, b.len, data, datalen);
             mg_free(data);
+            if (datalen > 0 && ret == 0) goto fail;
           } else {
             MG_ERROR(("%s: virtual=%s error or too deep", path, arg));
-          }
+          } // TODO(): or OOM at recursive call
         } else {
           // Unknown SSI tag
           MG_ERROR(("Unknown SSI tag: %.*s", (int) len, buf));
-          mg_iobuf_add(&b, b.len, buf, len);
+          if (len > 0 && mg_iobuf_add(&b, b.len, buf, len) == 0) goto fail;
         }
         intag = 0;
         len = 0;
       } else if (ch == '<') {
         intag = 1;
-        if (len > 0) mg_iobuf_add(&b, b.len, buf, len);
+        if (len > 0 && mg_iobuf_add(&b, b.len, buf, len) == 0) goto fail;
         len = 0;
         buf[len++] = (char) (ch & 0xff);
       } else if (intag) {
@@ -69,24 +73,33 @@ static char *mg_ssi(const char *path, const char *root, int depth) {
       } else {
         buf[len++] = (char) (ch & 0xff);
         if (len >= sizeof(buf)) {
-          mg_iobuf_add(&b, b.len, buf, len);
+          if (mg_iobuf_add(&b, b.len, buf, len) == 0) goto fail;
           len = 0;
         }
       }
     }
-    if (len > 0) mg_iobuf_add(&b, b.len, buf, len);
+    if (len > 0 && mg_iobuf_add(&b, b.len, buf, len) == 0) goto fail;
-    if (b.len > 0) mg_iobuf_add(&b, b.len, "", 1);  // nul-terminate
+    if (b.len > 0 && mg_iobuf_add(&b, b.len, "", 1) == 0)  // nul-terminate
+      goto fail;
     fclose(fp);
   }
   (void) depth;
   (void) root;
   return (char *) b.buf;
+
+fail:
+  fclose(fp);
+  return NULL;
 }
 
 void mg_http_serve_ssi(struct mg_connection *c, const char *root,
                        const char *fullpath) {
   const char *headers = "Content-Type: text/html; charset=utf-8\r\n";
   char *data = mg_ssi(fullpath, root, 0);
+  if (data == NULL) {
+    mg_error(c, "OOM");
+    return;
+  }
   mg_http_reply(c, 200, headers, "%s", data == NULL ? "" : data);
   mg_free(data);
 }

src/tls_builtin.c

@@ -42,6 +42,8 @@ enum mg_tls_hs_state {
 
   // Server state machine:
   MG_TLS_STATE_SERVER_START,       // Wait for ClientHello
+  MG_TLS_STATE_SERVER_WAIT_CERT,   // Wait for Certificate
+  MG_TLS_STATE_SERVER_WAIT_CV,     // Wait for CertificateVerify
   MG_TLS_STATE_SERVER_NEGOTIATED,  // Wait for Finish
   MG_TLS_STATE_SERVER_CONNECTED    // Done
 };
@@ -77,20 +79,22 @@ struct tls_data {
   uint8_t x25519_cli[32];  // client X25519 key between the handshake states
   uint8_t x25519_sec[32];  // x25519 secret between the handshake states
 
-  int skip_verification;   // perform checks on server certificate?
+  bool skip_verification;  // do not perform checks on server certificate
-  int cert_requested;      // client received a CertificateRequest?
+  bool cert_requested;     // client received a CertificateRequest
+  bool is_twoway;          // server is configured to authenticate clients
   struct mg_str cert_der;  // certificate in DER format
   struct mg_str ca_der;    // CA certificate
   uint8_t ec_key[32];      // EC private key
-  char hostname[254];      // server hostname (client extension)
+  char hostname[254];      // matching hostname
 
-  int is_ec_pubkey;          // EC or RSA?
+  bool is_ec_pubkey;         // EC or RSA
   uint8_t pubkey[512 + 16];  // server EC (64) or RSA (512+exp) public key to
                              // verify cert
   size_t pubkeysz;           // size of the server public key
   uint8_t sighash[32];       // calculated signature verification hash
 
-  struct tls_enc enc;
+  struct tls_enc enc;       // actual keys in use at this time
+  struct tls_enc app_keys;  // storage during two-way auth handshake
 };
 
 #define TLS_RECHDR_SIZE 5  // 1 byte type, 2 bytes version, 2 bytes length
@@ -395,7 +399,7 @@ static void mg_tls_generate_application_keys(struct mg_connection *c) {
 }
 
 // AES GCM encryption of the message + put encoded data into the write buffer
-static void mg_tls_encrypt(struct mg_connection *c, const uint8_t *msg,
+static bool mg_tls_encrypt(struct mg_connection *c, const uint8_t *msg,
                            size_t msgsz, uint8_t msgtype) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   struct mg_iobuf *wio = &tls->send;
@@ -415,6 +419,11 @@ static void mg_tls_encrypt(struct mg_connection *c, const uint8_t *msg,
   uint8_t *iv =
       c->is_client ? tls->enc.client_write_iv : tls->enc.server_write_iv;
 
+  if (msgsz > 16384) {
+    MG_ERROR(("msg longer than recordsz"));
+    return false;
+  }
+
 #if MG_ENABLE_CHACHA20
 #else
   mg_gcm_initialize();
@@ -426,8 +435,9 @@ static void mg_tls_encrypt(struct mg_connection *c, const uint8_t *msg,
   nonce[10] ^= (uint8_t) ((seq >> 8) & 255U);
   nonce[11] ^= (uint8_t) ((seq) & 255U);
 
-  mg_iobuf_add(wio, wio->len, hdr, sizeof(hdr));
+  if (mg_iobuf_add(wio, wio->len, hdr, sizeof(hdr)) == 0 ||
-  mg_iobuf_resize(wio, wio->len + encsz);
+      !mg_iobuf_resize(wio, wio->len + encsz))
+    return false;
   outmsg = wio->buf + wio->len;
   tag = wio->buf + wio->len + msgsz + 1;
   memmove(outmsg, msg, msgsz);
@@ -435,18 +445,14 @@ static void mg_tls_encrypt(struct mg_connection *c, const uint8_t *msg,
 #if MG_ENABLE_CHACHA20
   (void) tag;  // tag is only used in aes gcm
   {
-    size_t maxlen = MG_IO_SIZE > 16384 ? 16384 : MG_IO_SIZE;
+    size_t n;
-    uint8_t *enc = (uint8_t *) mg_calloc(1, maxlen + 256 + 1);
+    uint8_t *enc = (uint8_t *) mg_calloc(1, msgsz + 256 + 1);
-    if (enc == NULL) {
+    if (enc == NULL) return false;
-      mg_error(c, "TLS OOM");
+    n = mg_chacha20_poly1305_encrypt(enc, key, nonce, associated_data,
-      return;
+                                     sizeof(associated_data), outmsg,
-    } else {
+                                     msgsz + 1);
-      size_t n = mg_chacha20_poly1305_encrypt(enc, key, nonce, associated_data,
+    memmove(outmsg, enc, n);
-                                              sizeof(associated_data), outmsg,
+    mg_free(enc);
-                                              msgsz + 1);
-      memmove(outmsg, enc, n);
-      mg_free(enc);
-    }
   }
 #else
   mg_aes_gcm_encrypt(outmsg, outmsg, msgsz + 1, key, 16, nonce, sizeof(nonce),
@@ -454,6 +460,7 @@ static void mg_tls_encrypt(struct mg_connection *c, const uint8_t *msg,
 #endif
   c->is_client ? tls->enc.cseq++ : tls->enc.sseq++;
   wio->len += encsz;
+  return true;
 }
 
 // read an encrypted record, decrypt it in place
@@ -480,8 +487,7 @@ static int mg_tls_recv_record(struct mg_connection *c) {
     }
     if (rio->buf[0] == MG_TLS_APP_DATA) {
       break;
-    } else if (rio->buf[0] ==
+    } else if (rio->buf[0] == MG_TLS_CHANGE_CIPHER) {  // skip CCS
-               MG_TLS_CHANGE_CIPHER) {  // Skip ChangeCipher messages
       mg_tls_drop_record(c);
     } else if (rio->buf[0] == MG_TLS_ALERT) {  // Skip Alerts
       MG_INFO(("TLS ALERT packet received"));
@@ -513,6 +519,10 @@ static int mg_tls_recv_record(struct mg_connection *c) {
       return -1;
     }
     n = mg_chacha20_poly1305_decrypt(dec, key, nonce, msg, msgsz);
+    if (n == (size_t) -1) {
+      mg_error(c, "decryption error");
+      return -1;
+    }
     memmove(msg, dec, n);
     mg_free(dec);
   }
@@ -530,18 +540,18 @@ static int mg_tls_recv_record(struct mg_connection *c) {
 }
 
 static void mg_tls_calc_cert_verify_hash(struct mg_connection *c,
-                                         uint8_t hash[32], int is_client) {
+                                         uint8_t hash[32], bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
-  uint8_t server_context[34] = "TLS 1.3, server CertificateVerify";
-  uint8_t client_context[34] = "TLS 1.3, client CertificateVerify";
   uint8_t sig_content[130];
   mg_sha256_ctx sha256;
 
   memset(sig_content, 0x20, 64);
   if (is_client) {
-    memmove(sig_content + 64, client_context, sizeof(client_context));
+    uint8_t client_context[34] = "TLS 1.3, client CertificateVerify";
+    memcpy(sig_content + 64, client_context, sizeof(client_context));
   } else {
-    memmove(sig_content + 64, server_context, sizeof(server_context));
+    uint8_t server_context[34] = "TLS 1.3, server CertificateVerify";
+    memcpy(sig_content + 64, server_context, sizeof(server_context));
   }
 
   memmove(&sha256, &tls->sha256, sizeof(mg_sha256_ctx));
@@ -626,7 +636,7 @@ fail:
 #define PLACEHOLDER_32B PLACEHOLDER_16B, PLACEHOLDER_16B
 
 // put ServerHello record into wio buffer
-static void mg_tls_server_send_hello(struct mg_connection *c) {
+static bool mg_tls_server_send_hello(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   struct mg_iobuf *wio = &tls->send;
 
@@ -667,33 +677,58 @@ static void mg_tls_server_send_hello(struct mg_connection *c) {
   memmove(msg_server_hello + 84, x25519_pub, sizeof(x25519_pub));
 
   // server hello message
-  mg_iobuf_add(wio, wio->len, "\x16\x03\x03\x00\x7a", 5);
+  if (mg_iobuf_add(wio, wio->len, "\x16\x03\x03\x00\x7a", 5) == 0 ||
-  mg_iobuf_add(wio, wio->len, msg_server_hello, sizeof(msg_server_hello));
+      mg_iobuf_add(wio, wio->len, msg_server_hello, sizeof(msg_server_hello)) ==
+          0)
+    return false;
   mg_sha256_update(&tls->sha256, msg_server_hello, sizeof(msg_server_hello));
 
   // change cipher message
-  mg_iobuf_add(wio, wio->len, "\x14\x03\x03\x00\x01\x01", 6);
+  if (mg_iobuf_add(wio, wio->len, "\x14\x03\x03\x00\x01\x01", 6) == 0)
+    return false;
+  return true;
 }
 
-static void mg_tls_server_send_ext(struct mg_connection *c) {
+static bool mg_tls_server_send_ext(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   // server extensions
   uint8_t ext[6] = {0x08, 0, 0, 2, 0, 0};
   mg_sha256_update(&tls->sha256, ext, sizeof(ext));
-  mg_tls_encrypt(c, ext, sizeof(ext), MG_TLS_HANDSHAKE);
+  return mg_tls_encrypt(c, ext, sizeof(ext), MG_TLS_HANDSHAKE);
 }
 
-static void mg_tls_server_send_cert(struct mg_connection *c) {
+// signature algorithms we actually support:
+// rsa_pkcs1_sha256, rsa_pss_rsae_sha256 and ecdsa_secp256r1_sha256
+static const uint8_t secp256r1_sig_algs[12] = {
+    0x00, 0x0d, 0x00, 0x08, 0x00, 0x06, 0x04, 0x03, 0x08, 0x04, 0x04, 0x01
+};
+
+static bool mg_tls_server_send_cert_request(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
-  int send_ca = !c->is_client && tls->ca_der.len > 0;
+  uint8_t req[13 + sizeof(secp256r1_sig_algs)];
-  // server DER certificate + CA (optional)
+  req[0] = MG_TLS_CERTIFICATE_REQUEST;  // handshake header
+  MG_STORE_BE24(req + 1, 9 + sizeof(secp256r1_sig_algs));
+  req[4] = 0;                                              // context length
+  MG_STORE_BE16(req + 5, 6 + sizeof(secp256r1_sig_algs));  // extensions length
+  MG_STORE_BE16(req + 7, 13);  // "signature algorithms"
+  MG_STORE_BE16(req + 9, 2 + sizeof(secp256r1_sig_algs));  // length
+  MG_STORE_BE16(
+      req + 11,
+      sizeof(secp256r1_sig_algs));  // signature hash algorithms length
+  memcpy(req + 13, (uint8_t *) secp256r1_sig_algs, sizeof(secp256r1_sig_algs));
+  mg_sha256_update(&tls->sha256, req, sizeof(req));
+  return mg_tls_encrypt(c, req, sizeof(req), MG_TLS_HANDSHAKE);
+}
+
+static bool mg_tls_send_cert(struct mg_connection *c, bool is_client) {
+  struct tls_data *tls = (struct tls_data *) c->tls;
+  int send_ca = !is_client && tls->ca_der.len > 0;
+  // DER certificate + CA (server optional)
   size_t n = tls->cert_der.len + (send_ca ? tls->ca_der.len + 5 : 0);
   uint8_t *cert = (uint8_t *) mg_calloc(1, 13 + n);
-  if (cert == NULL) {
+  bool res;
-    mg_error(c, "tls cert oom");
+  if (cert == NULL) return false;
-    return;
+  cert[0] = MG_TLS_CERTIFICATE;  // handshake header
-  }
-  cert[0] = 0x0b;  // handshake header
   MG_STORE_BE24(cert + 1, n + 9);
   cert[4] = 0;                                 // request context
   MG_STORE_BE24(cert + 5, n + 5);              // 3 bytes: cert (s) length
@@ -710,8 +745,9 @@ static void mg_tls_server_send_cert(struct mg_connection *c) {
     MG_STORE_BE16(cert + 11 + n, 0);  // certificate extensions (none)
   }
   mg_sha256_update(&tls->sha256, cert, 13 + n);
-  mg_tls_encrypt(c, cert, 13 + n, MG_TLS_HANDSHAKE);
+  res = mg_tls_encrypt(c, cert, 13 + n, MG_TLS_HANDSHAKE);
   mg_free(cert);
+  return res;
 }
 
 // type adapter between uECC hash context and our sha256 implementation
@@ -736,7 +772,7 @@ static void finish_SHA256(const MG_UECC_HashContext *base,
   mg_sha256_final(hash_result, &c->ctx);
 }
 
-static void mg_tls_send_cert_verify(struct mg_connection *c, int is_client) {
+static bool mg_tls_send_cert_verify(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   // server certificate verify packet
   uint8_t verify[82] = {0x0f, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00};
@@ -770,10 +806,10 @@ static void mg_tls_send_cert_verify(struct mg_connection *c, int is_client) {
   verify[7] = (uint8_t) sigsz;
 
   mg_sha256_update(&tls->sha256, verify, verifysz);
-  mg_tls_encrypt(c, verify, verifysz, MG_TLS_HANDSHAKE);
+  return mg_tls_encrypt(c, verify, verifysz, MG_TLS_HANDSHAKE);
 }
 
-static void mg_tls_server_send_finish(struct mg_connection *c) {
+static bool mg_tls_server_send_finish(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   mg_sha256_ctx sha256;
   uint8_t hash[32];
@@ -781,8 +817,10 @@ static void mg_tls_server_send_finish(struct mg_connection *c) {
   memmove(&sha256, &tls->sha256, sizeof(mg_sha256_ctx));
   mg_sha256_final(hash, &sha256);
   mg_hmac_sha256(finish + 4, tls->enc.server_finished_key, 32, hash, 32);
-  mg_tls_encrypt(c, finish, sizeof(finish), MG_TLS_HANDSHAKE);
+  if (!mg_tls_encrypt(c, finish, sizeof(finish), MG_TLS_HANDSHAKE))
+    return false;
   mg_sha256_update(&tls->sha256, finish, sizeof(finish));
+  return true;
 }
 
 static int mg_tls_server_recv_finish(struct mg_connection *c) {
@@ -807,18 +845,15 @@ static int mg_tls_server_recv_finish(struct mg_connection *c) {
   return 0;
 }
 
-static void mg_tls_client_send_hello(struct mg_connection *c) {
+static bool mg_tls_client_send_hello(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   struct mg_iobuf *wio = &tls->send;
 
   uint8_t x25519_pub[X25519_BYTES];
 
-  // signature algorithms we actually support:
+  // - "signature algorithms we actually support", see above
-  // rsa_pkcs1_sha256, rsa_pss_rsae_sha256 and ecdsa_secp256r1_sha256
+  //   uint8_t secp256r1_sig_algs[]
-  uint8_t secp256r1_sig_algs[12] = {
+  // - all popular signature algorithms (if we don't care about verification)
-      0x00, 0x0d, 0x00, 0x08, 0x00, 0x06, 0x04, 0x03, 0x08, 0x04, 0x04, 0x01,
-  };
-  // all popular signature algorithms (if we don't care about verification)
   uint8_t all_sig_algs[34] = {
       0x00, 0x0d, 0x00, 0x1e, 0x00, 0x1c, 0x04, 0x03, 0x05, 0x03, 0x06, 0x03,
       0x08, 0x07, 0x08, 0x08, 0x08, 0x09, 0x08, 0x0a, 0x08, 0x0b, 0x08, 0x04,
@@ -862,7 +897,8 @@ static void mg_tls_client_send_hello(struct mg_connection *c) {
   const char *hostname = tls->hostname;
   size_t hostnamesz = strlen(tls->hostname);
   size_t hostname_extsz = hostnamesz ? hostnamesz + 9 : 0;
-  uint8_t *sig_alg = tls->skip_verification ? all_sig_algs : secp256r1_sig_algs;
+  uint8_t *sig_alg =
+      tls->skip_verification ? all_sig_algs : (uint8_t *) secp256r1_sig_algs;
   size_t sig_alg_sz = tls->skip_verification ? sizeof(all_sig_algs)
                                              : sizeof(secp256r1_sig_algs);
 
@@ -892,20 +928,27 @@ static void mg_tls_client_send_hello(struct mg_connection *c) {
   memmove(msg_client_hello + 94, x25519_pub, sizeof(x25519_pub));
 
   // client hello message
-  mg_iobuf_add(wio, wio->len, msg_client_hello, sizeof(msg_client_hello));
+  if (mg_iobuf_add(wio, wio->len, msg_client_hello, sizeof(msg_client_hello)) ==
+      0)
+    return false;
   mg_sha256_update(&tls->sha256, msg_client_hello + 5,
                    sizeof(msg_client_hello) - 5);
-  mg_iobuf_add(wio, wio->len, sig_alg, sig_alg_sz);
+  if (mg_iobuf_add(wio, wio->len, sig_alg, sig_alg_sz) == 0) return false;
   mg_sha256_update(&tls->sha256, sig_alg, sig_alg_sz);
   if (hostnamesz > 0) {
-    mg_iobuf_add(wio, wio->len, server_name_ext, sizeof(server_name_ext));
+    if (mg_iobuf_add(wio, wio->len, server_name_ext, sizeof(server_name_ext)) ==
-    mg_iobuf_add(wio, wio->len, hostname, hostnamesz);
+            0 ||
+        mg_iobuf_add(wio, wio->len, hostname, hostnamesz) == 0)
+      return false;
     mg_sha256_update(&tls->sha256, server_name_ext, sizeof(server_name_ext));
     mg_sha256_update(&tls->sha256, (uint8_t *) hostname, hostnamesz);
   }
 
   // change cipher message
-  mg_iobuf_add(wio, wio->len, (const char *) "\x14\x03\x03\x00\x01\x01", 6);
+  if (mg_iobuf_add(wio, wio->len, (const char *) "\x14\x03\x03\x00\x01\x01",
+                   6) == 0)
+    return false;
+  return true;
 }
 
 static int mg_tls_client_recv_hello(struct mg_connection *c) {
@@ -1154,7 +1197,8 @@ static int mg_tls_parse_cert_der(void *buf, size_t dersz,
 }
 
 static int mg_tls_verify_cert_san(const uint8_t *der, size_t dersz,
-                                  const char *server_name) {
+                                  const char *server_name,
+                                  struct mg_addr *server_ip) {
   struct mg_der_tlv root, field, name;
   if (mg_der_parse((uint8_t *) der, dersz, &root) < 0) {
     MG_ERROR(("failed to parse certificate"));
@@ -1169,12 +1213,16 @@ static int mg_tls_verify_cert_san(const uint8_t *der, size_t dersz,
     return -1;
   }
   while (mg_der_next(&field, &name) > 0) {
-    MG_DEBUG(("Found SAN: %.*s", name.len, name.value));
+    if (name.type == 0x87 && name.len == 4) { // this is an IPv4 address
-    if (mg_match(mg_str(server_name), mg_str_n((char *) name.value, name.len),
+      MG_DEBUG(("Found SAN, IP: %M", mg_print_ip4, name.value));
-                 NULL)) {
+      if (!server_ip->is_ip6 && *((uint32_t *) name.value) == server_ip->ip4)
-      // Found SAN that matches the host name
+        return 1;  // and matches the one we're connected to
-      return 1;
+    } else {  // this is a text SAN
-    }
+      MG_DEBUG(("Found SAN, (%u): %.*s", name.type, name.len, name.value));
+      if (mg_match(mg_str(server_name), mg_str_n((char *) name.value, name.len),
+                   NULL))
+        return 1;  // and matches the host name
+    }              // TODO(): add IPv6 comparison, more items ?
   }
   return -1;
 }
@@ -1237,7 +1285,7 @@ static int mg_tls_verify_cert_cn(struct mg_der_tlv *subj, const char *host) {
   return matched;
 }
 
-static int mg_tls_client_recv_cert(struct mg_connection *c) {
+static int mg_tls_recv_cert(struct mg_connection *c, bool is_client) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   unsigned char *recv_buf;
 
@@ -1255,7 +1303,8 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
   }
 
   if (recv_buf[0] != MG_TLS_CERTIFICATE) {
-    mg_error(c, "expected server certificate but got msg 0x%02x", recv_buf[0]);
+    mg_error(c, "expected %s certificate but got msg 0x%02x",
+             is_client ? "server" : "client", recv_buf[0]);
     return -1;
   }
 
@@ -1265,7 +1314,7 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
   }
 
   {
-    // Normally, there are 2-3 certs in a chain
+    // Normally, there are 2-3 certs in a chain (when is_client)
     struct mg_tls_cert certs[8];
     int certnum = 0;
     uint32_t full_cert_chain_len = MG_LOAD_BE24(recv_buf + 1);
@@ -1310,9 +1359,10 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
       }
 
       if (ci == certs) {
-        // First certificate in the chain is peer cert, check SAN and store
+        // First certificate in the chain is peer cert, check SAN if requested,
-        // public key for further CertVerify step
+        // and store public key for further CertVerify step
-        if (mg_tls_verify_cert_san(cert, certsz, tls->hostname) <= 0 &&
+        if (tls->hostname[0] != '\0' &&
+            mg_tls_verify_cert_san(cert, certsz, tls->hostname, &c->rem) <= 0 &&
             mg_tls_verify_cert_cn(&ci->subj, tls->hostname) <= 0) {
           mg_error(c, "failed to verify hostname");
           return -1;
@@ -1343,7 +1393,7 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
           !mg_tls_verify_cert_signature(&certs[certnum - 1], &ca)) {
         mg_error(c, "failed to verify CA");
         return -1;
-      } else {
+      } else if (is_client) {
         MG_VERBOSE(
             ("CA was not in the chain, but verification with builtin CA "
              "passed"));
@@ -1351,11 +1401,11 @@ static int mg_tls_client_recv_cert(struct mg_connection *c) {
     }
   }
   mg_tls_drop_message(c);
-  mg_tls_calc_cert_verify_hash(c, tls->sighash, 0);
+  mg_tls_calc_cert_verify_hash(c, tls->sighash, !is_client);
   return 0;
 }
 
-static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
+static int mg_tls_recv_cert_verify(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   unsigned char *recv_buf;
   if (mg_tls_recv_record(c) < 0) {
@@ -1363,8 +1413,8 @@ static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
   }
   recv_buf = &c->rtls.buf[tls->recv_offset];
   if (recv_buf[0] != MG_TLS_CERTIFICATE_VERIFY) {
-    mg_error(c, "expected server certificate verify but got msg 0x%02x",
+    mg_error(c, "expected %s certificate verify but got msg 0x%02x",
-             recv_buf[0]);
+             c->is_client ? "server" : "client", recv_buf[0]);
     return -1;
   }
   if (tls->recv_len < 8) {
@@ -1373,7 +1423,7 @@ static int mg_tls_client_recv_cert_verify(struct mg_connection *c) {
     return -1;
   }
 
-  // Ignore CertificateVerify is strict checks are not required
+  // Ignore CertificateVerify if strict checks are not required
   if (tls->skip_verification) {
     mg_tls_drop_message(c);
     return 0;
@@ -1473,7 +1523,7 @@ static int mg_tls_client_recv_finish(struct mg_connection *c) {
   return 0;
 }
 
-static void mg_tls_client_send_finish(struct mg_connection *c) {
+static bool mg_tls_client_send_finish(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   mg_sha256_ctx sha256;
   uint8_t hash[32];
@@ -1481,104 +1531,119 @@ static void mg_tls_client_send_finish(struct mg_connection *c) {
   memmove(&sha256, &tls->sha256, sizeof(mg_sha256_ctx));
   mg_sha256_final(hash, &sha256);
   mg_hmac_sha256(finish + 4, tls->enc.client_finished_key, 32, hash, 32);
-  mg_tls_encrypt(c, finish, sizeof(finish), MG_TLS_HANDSHAKE);
+  return mg_tls_encrypt(c, finish, sizeof(finish), MG_TLS_HANDSHAKE);
 }
 
-static void mg_tls_client_handshake(struct mg_connection *c) {
+static bool mg_tls_client_handshake(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   switch (tls->state) {
     case MG_TLS_STATE_CLIENT_START:
-      mg_tls_client_send_hello(c);
+      if (!mg_tls_client_send_hello(c)) return false;
       tls->state = MG_TLS_STATE_CLIENT_WAIT_SH;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_SH:
-      if (mg_tls_client_recv_hello(c) < 0) {
+      if (mg_tls_client_recv_hello(c) < 0) break;
-        break;
-      }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_EE;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_EE:
-      if (mg_tls_client_recv_ext(c) < 0) {
+      if (mg_tls_client_recv_ext(c) < 0) break;
-        break;
-      }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_CERT;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_CERT:
-      if (mg_tls_client_recv_cert(c) < 0) {
+      if (mg_tls_recv_cert(c, true) < 0) break;
-        break;
-      }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_CV;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_CV:
-      if (mg_tls_client_recv_cert_verify(c) < 0) {
+      if (mg_tls_recv_cert_verify(c) < 0) break;
-        break;
-      }
       tls->state = MG_TLS_STATE_CLIENT_WAIT_FINISH;
       // Fallthrough
     case MG_TLS_STATE_CLIENT_WAIT_FINISH:
-      if (mg_tls_client_recv_finish(c) < 0) {
+      if (mg_tls_client_recv_finish(c) < 0) break;
-        break;
+      if (tls->cert_requested && tls->cert_der.len > 0) {  // two-way auth
-      }
+        // generate application keys at this point, keep using handshake keys
-      if (tls->cert_requested) {
-        /* for mTLS we should generate application keys at this point
-         * but then restore handshake keys and continue with
-         * the rest of the handshake */
-        struct tls_enc app_keys;
         struct tls_enc hs_keys = tls->enc;
         mg_tls_generate_application_keys(c);
-        app_keys = tls->enc;
+        tls->app_keys = tls->enc;
         tls->enc = hs_keys;
-        mg_tls_server_send_cert(c);
+        if (!mg_tls_send_cert(c, true) || !mg_tls_send_cert_verify(c, true) ||
-        mg_tls_send_cert_verify(c, 1);
+            !mg_tls_client_send_finish(c))
-        mg_tls_client_send_finish(c);
+          return false;
-        tls->enc = app_keys;
+        tls->enc = tls->app_keys;
       } else {
-        mg_tls_client_send_finish(c);
+        if (!mg_tls_client_send_finish(c)) return false;
         mg_tls_generate_application_keys(c);
       }
       tls->state = MG_TLS_STATE_CLIENT_CONNECTED;
       c->is_tls_hs = 0;
       mg_call(c, MG_EV_TLS_HS, NULL);
       break;
-    default: mg_error(c, "unexpected client state: %d", tls->state); break;
+    default:
+      mg_error(c, "unexpected client state: %d", tls->state);
+      break;
   }
+  return true;
 }
 
-static void mg_tls_server_handshake(struct mg_connection *c) {
+static bool mg_tls_server_handshake(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   switch (tls->state) {
     case MG_TLS_STATE_SERVER_START:
-      if (mg_tls_server_recv_hello(c) < 0) {
+      if (mg_tls_server_recv_hello(c) < 0) break;
-        return;
+      if (!mg_tls_server_send_hello(c)) return false;
-      }
-      mg_tls_server_send_hello(c);
       mg_tls_generate_handshake_keys(c);
-      mg_tls_server_send_ext(c);
+      if (!mg_tls_server_send_ext(c)) return false;
-      mg_tls_server_send_cert(c);
+      if (tls->is_twoway && !mg_tls_server_send_cert_request(c)) return false;
-      mg_tls_send_cert_verify(c, 0);
+      if (!mg_tls_send_cert(c, false) || !mg_tls_send_cert_verify(c, false) || !mg_tls_server_send_finish(c)) return false;
-      mg_tls_server_send_finish(c);
+      if (tls->is_twoway) {
+        // generate application keys at this point, keep using handshake keys
+        struct tls_enc hs_keys = tls->enc;
+        mg_tls_generate_application_keys(c);
+        tls->app_keys = tls->enc;
+        tls->enc = hs_keys;
+        tls->state = MG_TLS_STATE_SERVER_WAIT_CERT;
+        break;
+      }
       tls->state = MG_TLS_STATE_SERVER_NEGOTIATED;
       // fallthrough
     case MG_TLS_STATE_SERVER_NEGOTIATED:
-      if (mg_tls_server_recv_finish(c) < 0) {
+      if (mg_tls_server_recv_finish(c) < 0) break;
-        return;
+      if (tls->is_twoway) {  // use previously generated keys
+        tls->enc = tls->app_keys;
+      } else {  // generate keys now
+        mg_tls_generate_application_keys(c);
       }
-      mg_tls_generate_application_keys(c);
       tls->state = MG_TLS_STATE_SERVER_CONNECTED;
       c->is_tls_hs = 0;
-      return;
+      break;
-    default: mg_error(c, "unexpected server state: %d", tls->state); break;
+    case MG_TLS_STATE_SERVER_WAIT_CERT:
+      if (mg_tls_recv_cert(c, false) < 0) break;
+      tls->state = MG_TLS_STATE_SERVER_WAIT_CV;
+      // Fallthrough
+    case MG_TLS_STATE_SERVER_WAIT_CV:
+      if (mg_tls_recv_cert_verify(c) < 0) break;
+      tls->state = MG_TLS_STATE_SERVER_NEGOTIATED;
+      break;
+    default:
+      mg_error(c, "unexpected server state: %d", tls->state);
+      break;
   }
+  return true;
 }
 
 void mg_tls_handshake(struct mg_connection *c) {
   struct tls_data *tls = (struct tls_data *) c->tls;
   long n;
+  bool res;
+  if (c->is_closing) return; // we don't clear rx buf, so ignore what's left
   if (c->is_client) {
     // will clear is_hs when sending last chunk
-    mg_tls_client_handshake(c);
+    res = mg_tls_client_handshake(c);
   } else {
-    mg_tls_server_handshake(c);
+    res = mg_tls_server_handshake(c);
+  }
+  if (!res) {
+    mg_error(c, "TLS OOM");
+    return;
   }
   while (tls->send.len > 0 &&
          (n = mg_io_send(c, tls->send.buf, tls->send.len)) > 0) {
@@ -1654,6 +1719,7 @@ void mg_tls_init(struct mg_connection *c, const struct mg_tls_opts *opts) {
       MG_ERROR(("Failed to load certificate"));
       return;
     }
+    if (!c->is_client) tls->is_twoway = true;  // server + CA: two-way auth
   }
 
   if (opts->cert.buf == NULL) {
@@ -1714,8 +1780,10 @@ long mg_tls_send(struct mg_connection *c, const void *buf, size_t len) {
   if (!was_throttled) {                      // encrypt new data
     if (len > MG_IO_SIZE) len = MG_IO_SIZE;
     if (len > 16384) len = 16384;
-    mg_tls_encrypt(c, (const uint8_t *) buf, len, MG_TLS_APP_DATA);
+    if (!mg_tls_encrypt(c, (const uint8_t *) buf, len, MG_TLS_APP_DATA))
-  }  // else, resend outstanding encrypted data in tls->send
+      return 0;  // returning 0 means an OOM condition (iobuf couldn't resize),
+                 // yet this is so far recoverable, let the caller decide
+  } // else, resend outstanding encrypted data in tls->send
   while (tls->send.len > 0 &&
          (n = mg_io_send(c, tls->send.buf, tls->send.len)) > 0) {
     mg_iobuf_del(&tls->send, 0, (size_t) n);

src/tls_mbed.c

@@ -58,6 +58,10 @@ void mg_tls_free(struct mg_connection *c) {
     mbedtls_ssl_config_free(&tls->conf);
 #ifdef MBEDTLS_SSL_SESSION_TICKETS
     mbedtls_ssl_ticket_free(&tls->ticket);
+#endif
+#if defined(MBEDTLS_VERSION_NUMBER) && MBEDTLS_VERSION_NUMBER >= 0x03000000 && \
+    defined(MBEDTLS_PSA_CRYPTO_C)
+    mbedtls_psa_crypto_free(); // https://github.com/Mbed-TLS/mbedtls/issues/9223#issuecomment-2144898336
 #endif
     mg_free(tls);
     c->tls = NULL;

src/tls_openssl.c

@@ -39,6 +39,7 @@ static STACK_OF(X509_INFO) * load_ca_certs(struct mg_str ca) {
 static bool add_ca_certs(SSL_CTX *ctx, STACK_OF(X509_INFO) * certs) {
   int i;
   X509_STORE *cert_store = SSL_CTX_get_cert_store(ctx);
+  if (cert_store == NULL) return false;
   for (i = 0; i < sk_X509_INFO_num(certs); i++) {
     X509_INFO *cert_info = sk_X509_INFO_value(certs, i);
     if (cert_info->x509 && !X509_STORE_add_cert(cert_store, cert_info->x509))

src/util.c

@@ -204,6 +204,10 @@ uint32_t mg_ntohl(uint32_t net) {
   return MG_LOAD_BE32(&net);
 }
 
+uint64_t mg_ntohll(uint64_t net) {
+  return MG_LOAD_BE64(&net);
+}
+
 void mg_delayms(unsigned int ms) {
   uint64_t to = mg_millis() + ms + 1;
   while (mg_millis() < to) (void) 0;

src/util.h

@@ -27,6 +27,16 @@ void mg_delayms(unsigned int ms);
 
 #define MG_IPV4(a, b, c, d) mg_htonl(MG_U32(a, b, c, d))
 
+#define MG_IPV6(a, b, c, d, e, f, g ,h) \
+  { (uint8_t)((a)>>8),(uint8_t)(a), \
+    (uint8_t)((b)>>8),(uint8_t)(b), \
+    (uint8_t)((c)>>8),(uint8_t)(c), \
+    (uint8_t)((d)>>8),(uint8_t)(d), \
+    (uint8_t)((e)>>8),(uint8_t)(e), \
+    (uint8_t)((f)>>8),(uint8_t)(f), \
+    (uint8_t)((g)>>8),(uint8_t)(g), \
+    (uint8_t)((h)>>8),(uint8_t)(h) }
+
 // For printing IPv4 addresses: printf("%d.%d.%d.%d\n", MG_IPADDR_PARTS(&ip))
 #define MG_U8P(ADDR) ((uint8_t *) (ADDR))
 #define MG_IPADDR_PARTS(ADDR) \
@@ -41,6 +51,14 @@ void mg_delayms(unsigned int ms);
   ((uint32_t) (((uint32_t) MG_U8P(p)[0] << 24U) | \
                ((uint32_t) MG_U8P(p)[1] << 16U) | \
                ((uint32_t) MG_U8P(p)[2] << 8U) | MG_U8P(p)[3]))
+#define MG_LOAD_BE64(p)                           \
+  ((uint64_t) (((uint64_t) MG_U8P(p)[0] << 56U) | \
+               ((uint64_t) MG_U8P(p)[1] << 48U) | \
+               ((uint64_t) MG_U8P(p)[2] << 40U) | \
+               ((uint64_t) MG_U8P(p)[3] << 32U) | \
+               ((uint64_t) MG_U8P(p)[4] << 24U) | \
+               ((uint64_t) MG_U8P(p)[5] << 16U) | \
+               ((uint64_t) MG_U8P(p)[6] << 8U) | MG_U8P(p)[7]))
 #define MG_STORE_BE16(p, n)           \
   do {                                \
     MG_U8P(p)[0] = ((n) >> 8U) & 255; \
@@ -59,11 +77,24 @@ void mg_delayms(unsigned int ms);
     MG_U8P(p)[2] = ((n) >> 8U) & 255;  \
     MG_U8P(p)[3] = (n) &255;           \
   } while (0)
+#define MG_STORE_BE64(p, n)            \
+  do {                                 \
+    MG_U8P(p)[0] = ((n) >> 56U) & 255; \
+    MG_U8P(p)[1] = ((n) >> 48U) & 255; \
+    MG_U8P(p)[2] = ((n) >> 40U) & 255; \
+    MG_U8P(p)[3] = ((n) >> 32U) & 255; \
+    MG_U8P(p)[4] = ((n) >> 24U) & 255; \
+    MG_U8P(p)[5] = ((n) >> 16U) & 255; \
+    MG_U8P(p)[6] = ((n) >> 8U) & 255;  \
+    MG_U8P(p)[7] = (n) &255;           \
+  } while (0)
 
 uint16_t mg_ntohs(uint16_t net);
 uint32_t mg_ntohl(uint32_t net);
+uint64_t mg_ntohll(uint64_t net);
 #define mg_htons(x) mg_ntohs(x)
 #define mg_htonl(x) mg_ntohl(x)
+#define mg_htonll(x) mg_ntohll(x)
 
 #define MG_REG(x) ((volatile uint32_t *) (x))[0]
 #define MG_BIT(x) (((uint32_t) 1U) << (x))

src/version.h

@@ -1 +1 @@
-#define MG_VERSION "7.19"
+#define MG_VERSION "7.20"

src/wifi.h

@@ -4,26 +4,35 @@
 #include "log.h"
 #include "str.h"
 
-struct mg_wifi_scan_bss_data {
+struct mg_wifi_data {
-    struct mg_str SSID;
+  char *ssid, *pass;      // STA mode, SSID to connect to
-    char *BSSID;
+  char *apssid, *appass;  // AP mode, our SSID
-    int16_t RSSI;
+  uint32_t apip, apmask;  // AP mode, our IP address and mask
-    uint8_t security;
+  uint8_t security;       // STA mode, TBD
-#define MG_WIFI_SECURITY_OPEN 0
+  uint8_t apsecurity;     // AP mode, TBD
-#define MG_WIFI_SECURITY_WEP  MG_BIT(0)
+  uint8_t apchannel;      // AP mode, channel to use
-#define MG_WIFI_SECURITY_WPA  MG_BIT(1)
+  bool apmode;  // start in AP mode; 'false' -> connect to 'ssid' != NULL
-#define MG_WIFI_SECURITY_WPA2 MG_BIT(2)
-#define MG_WIFI_SECURITY_WPA3 MG_BIT(3)
-    uint8_t channel;
-    unsigned band :2;
-#define MG_WIFI_BAND_2G 0
-#define MG_WIFI_BAND_5G 1
-    unsigned has_n :1;
 };
 
+struct mg_wifi_scan_bss_data {
+  struct mg_str SSID;
+  char *BSSID;
+  int16_t RSSI;
+  uint8_t security;
+#define MG_WIFI_SECURITY_OPEN 0
+#define MG_WIFI_SECURITY_WEP MG_BIT(0)
+#define MG_WIFI_SECURITY_WPA MG_BIT(1)
+#define MG_WIFI_SECURITY_WPA2 MG_BIT(2)
+#define MG_WIFI_SECURITY_WPA3 MG_BIT(3)
+  uint8_t channel;
+  unsigned band : 2;
+#define MG_WIFI_BAND_2G 0
+#define MG_WIFI_BAND_5G 1
+  unsigned has_n : 1;
+};
 
 bool mg_wifi_scan(void);
-bool mg_wifi_connect(char *ssid, char *pass);
+bool mg_wifi_connect(struct mg_wifi_data *);
 bool mg_wifi_disconnect(void);
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel);
+bool mg_wifi_ap_start(struct mg_wifi_data *);
 bool mg_wifi_ap_stop(void);

src/wifi_dummy.c

@@ -2,7 +2,8 @@
 
 #if (!defined(MG_ENABLE_DRIVER_PICO_W) || !MG_ENABLE_DRIVER_PICO_W) && \
     (!defined(MG_ENABLE_DRIVER_CYW) || !MG_ENABLE_DRIVER_CYW) && \
-    (!defined(MG_ENABLE_DRIVER_CYW_SDIO) || !MG_ENABLE_DRIVER_CYW_SDIO)
+    (!defined(MG_ENABLE_DRIVER_CYW_SDIO) || !MG_ENABLE_DRIVER_CYW_SDIO) && \
+    (!defined(MG_ENABLE_DRIVER_NXP_WIFI) || !MG_ENABLE_DRIVER_NXP_WIFI)
 
 
 bool mg_wifi_scan(void) {
@@ -10,9 +11,8 @@ bool mg_wifi_scan(void) {
   return false;
 }
 
-bool mg_wifi_connect(char *ssid, char *pass) {
+bool mg_wifi_connect(struct mg_wifi_data *wifi) {
-  (void) ssid;
+  (void) wifi;
-  (void) pass;
   return mg_wifi_scan();
 }
 
@@ -20,10 +20,8 @@ bool mg_wifi_disconnect(void) {
   return mg_wifi_scan();
 }
 
-bool mg_wifi_ap_start(char *ssid, char *pass, unsigned int channel) {
+bool mg_wifi_ap_start(struct mg_wifi_data *wifi) {
-  (void) ssid;
+  (void) wifi;
-  (void) pass;
-  (void) channel;
   return mg_wifi_scan();
 }
 

src/ws.c

@@ -55,7 +55,7 @@ static void ws_handshake(struct mg_connection *c, const struct mg_str *wskey,
     mg_printf(c, "Sec-WebSocket-Protocol: %.*s\r\n", (int) wsproto->len,
               wsproto->buf);
   }
-  mg_send(c, "\r\n", 2);
+  if (!mg_send(c, "\r\n", 2)) mg_error(c, "OOM");
 }
 
 static uint32_t be32(const uint8_t *p) {
@@ -292,6 +292,6 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) {
     memmove(p, p - header_len, len);             // Shift data
     memcpy(p - header_len, header, header_len);  // Prepend header
     mg_ws_mask(c, len);                          // Mask data
-  }
+  }  // returning 0 means an OOM condition (iobuf couldn't resize), yet this is
-  return c->send.len;
+  return c->send.len;  // so far recoverable, let the caller decide
 }

test/data/e5.crt

@@ -1,33 +0,0 @@
-- Make sure your PEM file starts with a dash -
-
-
-Issuer: C=US, O=Internet Security Research Group, CN=ISRG Root X1
-Not Before: Mar 13 00:00:00 2024 GMT
-Not After : Mar 12 23:59:59 2027 GMT
------BEGIN CERTIFICATE-----
-MIIEVzCCAj+gAwIBAgIRAIOPbGPOsTmMYgZigxXJ/d4wDQYJKoZIhvcNAQELBQAw
-TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh
-cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMjQwMzEzMDAwMDAw
-WhcNMjcwMzEyMjM1OTU5WjAyMQswCQYDVQQGEwJVUzEWMBQGA1UEChMNTGV0J3Mg
-RW5jcnlwdDELMAkGA1UEAxMCRTUwdjAQBgcqhkjOPQIBBgUrgQQAIgNiAAQNCzqK
-a2GOtu/cX1jnxkJFVKtj9mZhSAouWXW0gQI3ULc/FnncmOyhKJdyIBwsz9V8UiBO
-VHhbhBRrwJCuhezAUUE8Wod/Bk3U/mDR+mwt4X2VEIiiCFQPmRpM5uoKrNijgfgw
-gfUwDgYDVR0PAQH/BAQDAgGGMB0GA1UdJQQWMBQGCCsGAQUFBwMCBggrBgEFBQcD
-ATASBgNVHRMBAf8ECDAGAQH/AgEAMB0GA1UdDgQWBBSfK1/PPCFPnQS37SssxMZw
-i9LXDTAfBgNVHSMEGDAWgBR5tFnme7bl5AFzgAiIyBpY9umbbjAyBggrBgEFBQcB
-AQQmMCQwIgYIKwYBBQUHMAKGFmh0dHA6Ly94MS5pLmxlbmNyLm9yZy8wEwYDVR0g
-BAwwCjAIBgZngQwBAgEwJwYDVR0fBCAwHjAcoBqgGIYWaHR0cDovL3gxLmMubGVu
-Y3Iub3JnLzANBgkqhkiG9w0BAQsFAAOCAgEAH3KdNEVCQdqk0LKyuNImTKdRJY1C
-2uw2SJajuhqkyGPY8C+zzsufZ+mgnhnq1A2KVQOSykOEnUbx1cy637rBAihx97r+
-bcwbZM6sTDIaEriR/PLk6LKs9Be0uoVxgOKDcpG9svD33J+G9Lcfv1K9luDmSTgG
-6XNFIN5vfI5gs/lMPyojEMdIzK9blcl2/1vKxO8WGCcjvsQ1nJ/Pwt8LQZBfOFyV
-XP8ubAp/au3dc4EKWG9MO5zcx1qT9+NXRGdVWxGvmBFRAajciMfXME1ZuGmk3/GO
-koAM7ZkjZmleyokP1LGzmfJcUd9s7eeu1/9/eg5XlXd/55GtYjAM+C4DG5i7eaNq
-cm2F+yxYIPt6cbbtYVNJCGfHWqHEQ4FYStUyFnv8sjyqU8ypgZaNJ9aVcWSICLOI
-E1/Qv/7oKsnZCWJ926wU6RqG1OYPGOi1zuABhLw61cuPVDT28nQS/e6z95cJXq0e
-K1BcaJ6fJZsmbjRgD5p3mvEf5vdQM7MCEvU0tHbsx2I5mHHJoABHb8KVBgWp/lcX
-GWiWaeOyB7RP+OfDtvi2OsapxXiV7vNVs7fMlrRjY1joKaqmmycnBvAq14AEbtyL
-sVfOS66B8apkeFX2NY4XPEYV4ZSCe8VHPrdrERk2wILG3T/EGmSIkCYVUMSnjmJd
-VQD9F6Na/+zmXCc=
------END CERTIFICATE-----
-

test/data/e8.crt

@@ -0,0 +1,34 @@
+- Make sure your PEM file starts with a dash -
+
+
+ 1 s:C=US, O=Let's Encrypt, CN=E8
+   i:C=US, O=Internet Security Research Group, CN=ISRG Root X1
+   a:PKEY: id-ecPublicKey, 384 (bit); sigalg: RSA-SHA256
+   v:NotBefore: Mar 13 00:00:00 2024 GMT; NotAfter: Mar 12 23:59:59 2027 GMT
+-----BEGIN CERTIFICATE-----
+MIIEVjCCAj6gAwIBAgIQY5WTY8JOcIJxWRi/w9ftVjANBgkqhkiG9w0BAQsFADBP
+MQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJuZXQgU2VjdXJpdHkgUmVzZWFy
+Y2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBYMTAeFw0yNDAzMTMwMDAwMDBa
+Fw0yNzAzMTIyMzU5NTlaMDIxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBF
+bmNyeXB0MQswCQYDVQQDEwJFODB2MBAGByqGSM49AgEGBSuBBAAiA2IABNFl8l7c
+S7QMApzSsvru6WyrOq44ofTUOTIzxULUzDMMNMchIJBwXOhiLxxxs0LXeb5GDcHb
+R6EToMffgSZjO9SNHfY9gjMy9vQr5/WWOrQTZxh7az6NSNnq3u2ubT6HTKOB+DCB
+9TAOBgNVHQ8BAf8EBAMCAYYwHQYDVR0lBBYwFAYIKwYBBQUHAwIGCCsGAQUFBwMB
+MBIGA1UdEwEB/wQIMAYBAf8CAQAwHQYDVR0OBBYEFI8NE6L2Ln7RUGwzGDhdWY4j
+cpHKMB8GA1UdIwQYMBaAFHm0WeZ7tuXkAXOACIjIGlj26ZtuMDIGCCsGAQUFBwEB
+BCYwJDAiBggrBgEFBQcwAoYWaHR0cDovL3gxLmkubGVuY3Iub3JnLzATBgNVHSAE
+DDAKMAgGBmeBDAECATAnBgNVHR8EIDAeMBygGqAYhhZodHRwOi8veDEuYy5sZW5j
+ci5vcmcvMA0GCSqGSIb3DQEBCwUAA4ICAQBnE0hGINKsCYWi0Xx1ygxD5qihEjZ0
+RI3tTZz1wuATH3ZwYPIp97kWEayanD1j0cDhIYzy4CkDo2jB8D5t0a6zZWzlr98d
+AQFNh8uKJkIHdLShy+nUyeZxc5bNeMp1Lu0gSzE4McqfmNMvIpeiwWSYO9w82Ob8
+otvXcO2JUYi3svHIWRm3+707DUbL51XMcY2iZdlCq4Wa9nbuk3WTU4gr6LY8MzVA
+aDQG2+4U3eJ6qUF10bBnR1uuVyDYs9RhrwucRVnfuDj29CMLTsplM5f5wSV5hUpm
+Uwp/vV7M4w4aGunt74koX71n4EdagCsL/Yk5+mAQU0+tue0JOfAV/R6t1k+Xk9s2
+HMQFeoxppfzAVC04FdG9M+AC2JWxmFSt6BCuh3CEey3fE52Qrj9YM75rtvIjsm/1
+Hl+u//Wqxnu1ZQ4jpa+VpuZiGOlWrqSP9eogdOhCGisnyewWJwRQOqK16wiGyZeR
+xs/Bekw65vwSIaVkBruPiTfMOo0Zh4gVa8/qJgMbJbyrwwG97z/PRgmLKCDl8z3d
+tA0Z7qq7fta0Gl24uyuB05dqI5J1LvAzKuWdIjT1tP8qCoxSE/xpix8hX2dt3h+/
+jujUgFPFZ0EVZ0xSyBNRF3MboGZnYXFUxpNjTWPKpagDHJQmqrAcDmWJnMsFY3jS
+u1igv3OefnWjSQ==
+-----END CERTIFICATE-----
+

test/fuzz.c

@@ -111,31 +111,43 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) {
         uint8_t ip_protos[] = {1, 6, 17}; // ICMP, TCP, UDP
         struct ip *ip4 = (struct ip *) (eth + 1);
         ip4->ver = (ip4->ver & ~0xf0) | (4 << 4);
-        // send all handled ip protos, then 2 random ones
+        // send all handled IP protos, then 2 random ones
         if (j >= (sizeof(ip_protos) / sizeof(ip_protos[0]) + 2)) j = 0;
         if (j < (sizeof(ip_protos) / sizeof(ip_protos[0]))) ip4->proto = (ip_protos[j++]);
         if (ip4->proto == 1) { // ICMP
         } else if (ip4->proto == 6) { // TCP
-        } else if (ip4->proto == 17 && size > (sizeof(*eth) + sizeof(struct ip) + sizeof(struct udp))) { // UDP
+        } else if (ip4->proto == 17) { // UDP
-          static size_t k;
+          if (size > (sizeof(*eth) + sizeof(struct ip) + sizeof(struct udp))) {
-          uint16_t udp_ports[] = {67, 68}; // DHCP server and client
+            static size_t k;
-          struct udp *udp = (struct udp *) (ip4 + 1);
+            uint16_t udp_ports[] = {67, 68}; // DHCP server and client
-          // send all handled udp ports, then 2 random ones
+            struct udp *udp = (struct udp *) (ip4 + 1);
-          if (k >= (sizeof(udp_ports) / sizeof(udp_ports[0]) + 2)) k = 0;
+            // send all handled UDP ports, then 2 random ones
-          if (k < (sizeof(udp_ports) / sizeof(udp_ports[0]))) udp->dport = mg_htons(udp_ports[k++]);
+            if (k >= (sizeof(udp_ports) / sizeof(udp_ports[0]) + 2)) k = 0;
+            if (k < (sizeof(udp_ports) / sizeof(udp_ports[0]))) udp->dport = mg_htons(udp_ports[k++]);
+          }
         }
       } else if (eth->type == mg_htons(0x806)) {      // ARP
+
       } else if (eth->type == mg_htons(0x86dd) && size > (sizeof(*eth) + sizeof(struct ip6))) {     // IPv6
         static size_t j;
-        uint8_t ip6_protos[] = {6, 17}; // TCP, UDP
+        uint8_t ip6_protos[] = {6, 17, 58}; // TCP, UDP, ICMPv6
         struct ip6 *ip6 = (struct ip6 *) (eth + 1);
         ip6->ver = (ip6->ver & ~0xf0) | (6 << 4);
-        // send all handled ip6 "next headers", then 2 random ones
+        // send all handled IPv6 "next headers", then 2 random ones
         if (j >= (sizeof(ip6_protos) / sizeof(ip6_protos[0]) + 2)) j = 0;
-        if (j < (sizeof(ip6_protos) / sizeof(ip6_protos[0]))) ip6->proto = (ip6_protos[j++]);
+        if (j < (sizeof(ip6_protos) / sizeof(ip6_protos[0]))) ip6->next = (ip6_protos[j++]);
-        if (ip6->proto == 6) { // TCP
+        if (ip6->next == 6) { // TCP
-        } else if (ip6->proto == 17) { // UDP
+        } else if (ip6->next == 17) { // UDP
-        }    
+        } else if (ip6->next == 58) { // ICMPv6
+          if (size >= (sizeof(*eth) + sizeof(struct ip6) + sizeof(struct icmp6))) {
+            static size_t k;
+            uint8_t icmp6_types[] = {128, 134, 135, 136}; // Echo Request, RA, NS, NA
+            struct icmp6 *icmp6 = (struct icmp6 *) (ip6 + 1);
+            // send all handled ICMPv6 types, then 2 random ones
+            if (k >= (sizeof(icmp6_types) / sizeof(icmp6_types[0]) + 2)) k = 0;
+            if (k < (sizeof(icmp6_types) / sizeof(icmp6_types[0]))) icmp6->type = icmp6_types[k++];
+          }
+        }
       }
     }
 

test/fuzz_tls.c

@@ -18,10 +18,11 @@ int LLVMFuzzerTestOneInput(const uint8_t *, size_t);
 // Preprocessor magic, just add/remove functions here and leave the rest alone
 #define TABLE(_) \
 _(mg_tls_server_recv_hello) \
-//_(mg_tls_client_recv_hello) \
+_(mg_tls_server_recv_finish) \
-//_(mg_tls_client_recv_ext ) \
+_(mg_tls_client_recv_hello) \
-//_(mg_tls_client_recv_cert) \
+_(mg_tls_client_recv_finish) \
-//_(mg_tls_client_recv_cert_verify) \
+_(mg_tls_client_recv_ext) \
+_(mg_tls_recv_cert_verify) \
 // ... 
 
 struct f {
@@ -52,7 +53,7 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) {
     c = &c_[i];
     io = &c->rtls;
     if (i > 0) memcpy(c, &c_[0], sizeof(*c)); // copy from 1st one
-    if (i > 0) c->is_client = 1;  // from 1 on, client functions
+    if (i > 1) c->is_client = 1;  // from 2 on, client functions
     memset(&tls_[i], 0, sizeof(struct tls_data));
     if (io->size - io->len < size && !mg_iobuf_resize(io, io->len + size)) {
       mg_error(c, "oom");
@@ -64,10 +65,31 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) {
 #ifdef PRINT_FUNCNAME
     printf("CALLING %s\n", f_[i].name);
 #endif
-    f_[i].f(&c[i]);
+    f_[i].f(c);
     mg_iobuf_free(io);
   }
-  
+
+  // mg_tls_recv_cert() has an extra bool parameter 
+  c = &c_[0]; // reuse first one
+  c->tls = &tls_[0];
+  for (i = 0; i < 2; i++) {
+    struct mg_iobuf *io;
+    io = &c->rtls;
+    c->is_client = (i > 0);
+    memset(c->tls, 0, sizeof(struct tls_data));
+    if (io->size - io->len < size && !mg_iobuf_resize(io, io->len + size)) {
+      mg_error(c, "oom");
+      return 0; // drop it
+    }
+    memcpy(&io->buf[io->len], data, size);
+    io->len += size;
+#ifdef PRINT_FUNCNAME
+    printf("CALLING mg_tls_recv_cert\n");
+#endif
+    mg_tls_recv_cert(c, !c->is_client); // call server for client and client for server
+    mg_iobuf_free(io);
+  }
+
   return 0;
 }
 

test/health.awk

@@ -0,0 +1,11 @@
+#!/usr/bin/env -S gawk -f
+# gawk used to avoid "towc" errors seen on MacOS. env used to circumvent brew installing it wherever they like
+
+BEGIN {
+	FS="\t"
+	print "{"
+}
+/HEALTH_DASHBOARD/ { print $2 }
+END {
+	print "}"
+}

test/health.sh

@@ -0,0 +1,5 @@
+#!/bin/bash
+
+cd /data/downloads/health
+find . -mtime +28 -not -name 'index*.json' -delete
+find . -name "*.json" -not -name 'index*.json' | jq -R . | jq -s . > index.json

test/mip_tap_test.c

@@ -82,7 +82,12 @@ static const char *s_ca_cert =
 static char *host_ip;
 
 static int s_num_tests = 0;
+static bool s_error = false;
 
+#ifdef NO_ABORT
+static int s_abort = 0;
+#define ABORT() ++s_abort, s_error = true
+#else
 #ifdef NO_SLEEP_ABORT
 #define ABORT() abort()
 #else
@@ -90,6 +95,7 @@ static int s_num_tests = 0;
   sleep(2); /* 2s, GH print reason */ \
   abort();
 #endif
+#endif
 
 #define ASSERT(expr)                                            \
   do {                                                          \
@@ -101,6 +107,7 @@ static int s_num_tests = 0;
     }                                                           \
   } while (0)
 
+
 static struct mg_http_message gethm(const char *buf) {
   struct mg_http_message hm;
   memset(&hm, 0, sizeof(hm));
@@ -246,7 +253,7 @@ static int fetch(struct mg_mgr *mgr, char *buf, const char *url,
 static void test_http_client(struct mg_mgr *mgr) {
   char buf[FETCH_BUF_SIZE];
   int rc = 0;
-  const bool ipv6 = 0;
+  const bool ipv6 = MG_ENABLE_IPV6;
 #if MG_TLS
   if (ipv6) {
     rc = fetch(mgr, buf, "https://ipv6.google.com",
@@ -260,11 +267,12 @@ static void test_http_client(struct mg_mgr *mgr) {
   if (ipv6) {
     rc = fetch(mgr, buf, "http://ipv6.google.com",
                "GET / HTTP/1.0\r\nHost: ipv6.google.com\r\n\r\n");
+    ASSERT(rc == 200);  // OK
   } else {
     rc = fetch(mgr, buf, "http://cesanta.com",
                "GET /robots.txt HTTP/1.0\r\nHost: cesanta.com\r\n\r\n");
+    ASSERT(rc == 301);  // OK: Permanently moved (HTTP->HTTPS redirect)
   }
-  ASSERT(rc == 301);  // OK: Permanently moved (HTTP->HTTPS redirect)
 
 #endif
 }
@@ -405,6 +413,7 @@ static void test_http_server(struct mg_mgr *mgr) {
       mg_mprintf("./mip_curl.sh http://%M:12347", mg_print_ip4, &mgr->ifp->ip);
 #endif
   ASSERT(c != NULL);
+  ASSERT (mg_send(c, "NADA", 0)); // check mg_send allows len=0
   pthread_create(&thread_id, NULL, poll_thread,
                  mgr);  // simpler this way, no concurrency anyway
   MG_DEBUG(("CURL"));
@@ -531,22 +540,41 @@ int main(void) {
     usleep(10000);  // 10 ms
   }
 
+#define DASHBOARD(x)  printf("HEALTH_DASHBOARD\t\"%s\": %s,\n", x, s_error ? "false":"true");
+
   // RUN TESTS
   usleep(500000);  // 500 ms
+  s_error = false;
   test_http_client(&mgr);
-  usleep(500000);  // 500 ms
+  DASHBOARD("http_client");
-  test_http_server(&mgr);
-  usleep(500000);  // 500 ms
-  test_tls(&mgr);
-  usleep(500000);  // 500 ms
-  test_mqtt_connsubpub(&mgr);
-  usleep(500000);  // 500 ms
 
-  printf("SUCCESS. Total tests: %d\n", s_num_tests);
+  usleep(500000);  // 500 ms
+  s_error = false;
+  test_http_server(&mgr);
+  DASHBOARD("http_server");
+
+  usleep(500000);  // 500 ms
+  s_error = false;
+  test_tls(&mgr);
+  DASHBOARD("tls");
+
+  usleep(500000);  // 500 ms
+  s_error = false;
+  test_mqtt_connsubpub(&mgr);
+  DASHBOARD("mqtt");
 
   // Clear
+  s_error = false;
   mg_mgr_free(&mgr);
   ASSERT(mgr.conns == NULL);  // Deconstruction OK
   close(fd);
-  return 0;
+  printf("HEALTH_DASHBOARD\t\"cleanup\": %s\n", s_error ? "false":"true");
+ // last entry with no comma
+
+#ifdef NO_ABORT
+  if (s_abort != 0) return EXIT_FAILURE;
+#endif
+
+  printf("SUCCESS. Total tests: %d\n", s_num_tests);
+  return EXIT_SUCCESS;
 }

test/unit_test.c

@@ -4,7 +4,12 @@
 #include "math.h"
 
 static int s_num_tests = 0;
+static bool s_error = false;
 
+#ifdef NO_ABORT
+static int s_abort = 0;
+#define ABORT() ++s_abort, s_error = true
+#else
 #ifdef NO_SLEEP_ABORT
 #define ABORT() abort()
 #else
@@ -12,6 +17,7 @@ static int s_num_tests = 0;
   sleep(2); /* 2s, GH print reason */ \
   abort();
 #endif
+#endif
 
 #define ASSERT(expr)                                            \
   do {                                                          \
@@ -316,6 +322,8 @@ static void test_iobuf(void) {
   mg_iobuf_add(&io, io.len, "a", 1);
   ASSERT(io.buf != NULL && io.size == 20 && io.len == 11);
   ASSERT(memcmp(io.buf, "xhi!123456a", io.len) == 0);
+  mg_iobuf_resize(&io, 1);
+  ASSERT(io.buf != NULL && io.size == 10 && io.len == 10);
   mg_iobuf_free(&io);
 }
 
@@ -867,8 +875,10 @@ static int fetch(struct mg_mgr *mgr, char *buf, const char *url,
     if (strstr(url, "localhost") != NULL) {
       // Local connection, use self-signed certificates
       opts.ca = mg_unpacked("/certs/ca.crt");
-      // opts.cert = mg_str(s_tls_cert);
+      if (strstr(url, "23456") != NULL) { // hinted from caller
-      // opts.key = mg_str(s_tls_key);
+        opts.cert = mg_unpacked("/certs/client.crt");
+        opts.key = mg_unpacked("/certs/client.key");
+      }
     }
     mg_tls_init(c, &opts);
   }
@@ -1414,7 +1424,6 @@ static void test_tls(void) {
   struct mg_str bd;
   ASSERT(data.buf != NULL && data.len > 0);
   memset(&opts, 0, sizeof(opts));
-  // opts.ca = mg_str(s_tls_ca);
   opts.cert = mg_unpacked("/certs/server.crt");
   opts.key = mg_unpacked("/certs/server.key");
   mg_mgr_init(&mgr);
@@ -1463,6 +1472,20 @@ static void test_tls(void) {
       "is 1.3 only; re-enable when other stacks can be easily configured for "
       "1.3\n");
 #endif
+
+  // Repeat the simplest test with two-way authentication
+  opts.ca = mg_unpacked("/certs/ca.crt"); // configure the server for two-way
+  // make it fail: the client will not use 2-way
+  ASSERT(fetch(&mgr, buf, url, "GET /a.txt HTTP/1.0\n\n") != 200);
+  // make it work
+  mg_mgr_free(&mgr);
+  ASSERT(mgr.conns == NULL);
+  mg_mgr_init(&mgr);
+  url = "https://localhost:23456"; // port # hints the client to use two-way
+  c = mg_http_listen(&mgr, url, eh1, &opts);
+  ASSERT(c != NULL);
+  ASSERT(fetch(&mgr, buf, url, "GET /a.txt HTTP/1.0\n\n") == 200);
+  ASSERT(cmpbody(buf, "hello\n") == 0);
   mg_mgr_free(&mgr);
   ASSERT(mgr.conns == NULL);
 #endif
@@ -1515,7 +1538,7 @@ static void test_http_client(void) {
   opts.name = mg_url_host(url);
 #if MG_TLS == MG_TLS_BUILTIN
   // our TLS does not search for the proper CA in a bundle
-  opts.ca = mg_file_read(&mg_fs_posix, "data/e5.crt");
+  opts.ca = mg_file_read(&mg_fs_posix, "data/e8.crt");
 #endif
   c = mg_http_connect(&mgr, url, f3, &ok);
   ASSERT(c != NULL);
@@ -1525,7 +1548,7 @@ static void test_http_client(void) {
   ASSERT(ok == 200);
   mg_mgr_poll(&mgr, 1);
 
-  // Make host validationfail
+  // Make host validation fail
   c = mg_http_connect(&mgr, url, f3, &ok);
   ASSERT(c != NULL);
   opts.name = mg_str("dummy");  // Set some invalid hostname value
@@ -1535,6 +1558,16 @@ static void test_http_client(void) {
   MG_INFO(("OK: %d", ok));
   ASSERT(ok == 777);
   mg_mgr_poll(&mgr, 1);
+  // Skip host validation
+  c = mg_http_connect(&mgr, url, f3, &ok);
+  ASSERT(c != NULL);
+  opts.name = mg_str("");
+  mg_tls_init(c, &opts);
+  ok = 0;
+  for (i = 0; i < 500 && ok <= 0; i++) mg_mgr_poll(&mgr, 10);
+  MG_INFO(("OK: %d", ok));
+  ASSERT(ok == 200);
+  mg_mgr_poll(&mgr, 1);
   opts.name = mg_url_host(url);
 #if MG_TLS == MG_TLS_BUILTIN
   mg_free((void *) opts.ca.buf);
@@ -2232,6 +2265,16 @@ static void test_str(void) {
   ASSERT(sn("%s ", "a"));
   ASSERT(sn("%s %s", "a", "b"));
   ASSERT(sn("%2s %s", "a", "b"));
+  { // mg_queue_printf()
+	struct mg_queue q;
+	char buf[128];
+	uint32_t p = 0xffffffff;
+	size_t len;
+	mg_queue_init(&q, buf, sizeof(buf));
+	len = mg_queue_printf(&q, "A%p%p%pB", p, p, p);
+  ASSERT(len == 32);
+  ASSERT(memcmp(buf + 4, "A0xffffffff0xffffffff0xffffffffB", 32) == 0);
+  }
 
   // Non-standard formatting
   {
@@ -2574,6 +2617,8 @@ static void test_util(void) {
   const char *e;
   char buf[100], *s;
   struct mg_addr a;
+  uint64_t ipv3;
+  uint8_t d64[8] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef};
   uint32_t ipv4;
   uint16_t port;
   struct mg_str data;
@@ -2608,6 +2653,20 @@ static void test_util(void) {
          ((uint8_t *) &ipv4)[2] == 0x45);
   ASSERT(MG_LOAD_BE24(&ipv4) == 0xef2345);
 
+  memcpy(&ipv3, d64, sizeof(ipv3));
+#if defined(_MSC_VER) && _MSC_VER < 1700
+  // VC98 doesn't suppport LL suffix
+#else
+  ASSERT(ipv3 == mg_htonll(0x1234567890abcdefLL));
+  ASSERT(mg_ntohll(ipv3) == 0x1234567890abcdefLL);
+#endif
+  MG_STORE_BE64(&ipv3, 0x5678abcd12349ef0);
+  ASSERT(((uint8_t *) &ipv3)[0] == 0x56 && ((uint8_t *) &ipv3)[1] == 0x78 &&
+         ((uint8_t *) &ipv3)[2] == 0xab && ((uint8_t *) &ipv3)[3] == 0xcd &&
+         ((uint8_t *) &ipv3)[4] == 0x12 && ((uint8_t *) &ipv3)[5] == 0x34 &&
+         ((uint8_t *) &ipv3)[6] == 0x9e && ((uint8_t *) &ipv3)[7] == 0xf0);
+  ASSERT(MG_LOAD_BE64(&ipv3) == 0x5678abcd12349ef0);
+
   memset(a.ip, 0xa5, sizeof(a.ip));
   ASSERT(mg_aton(mg_str("1:2:3:4:5:6:7:8"), &a) == true);
   ASSERT(a.is_ip6 == true);
@@ -2918,6 +2977,14 @@ static void eZ(struct mg_connection *c, int ev, void *ev_data) {
   (void) ev_data;
 }
 
+static void eS(struct mg_connection *c, int ev, void *ev_data) {
+  if (ev == MG_EV_HTTP_MSG) {
+    ASSERT (mg_send(c, "NADA", 0));
+    mg_http_reply(c, 200, "", "abcd");
+  }
+  (void) ev_data;
+}
+
 // Do not delete chunks as they arrive
 static void eh4(struct mg_connection *c, int ev, void *ev_data) {
   uint32_t *crc = (uint32_t *) c->fn_data;
@@ -2953,6 +3020,9 @@ static void test_http_chunked_case(mg_event_handler_t s, mg_event_handler_t c,
 }
 
 static void test_http_chunked(void) {
+  // test mg_send allows calls with 0 length
+  test_http_chunked_case(eS, eh4, 1, "abcd");
+
   // Non-chunked encoding
   test_http_chunked_case(eY, eh4, 1, "abcd");  // Chunks not deleted
   test_http_chunked_case(eY, eh4, 2, "abcdabcd");
@@ -3176,7 +3246,7 @@ static void test_udp(void) {
 }
 
 static void test_check_ip_acl(void) {
-  struct mg_addr ip = {{1, 2, 3, 4}, 0, 0, false};  // 1.2.3.4
+  struct mg_addr ip = {{{1, 2, 3, 4}}, 0, 0, false};  // 1.2.3.4
   ASSERT(mg_check_ip_acl(mg_str(NULL), &ip) == 1);
   ASSERT(mg_check_ip_acl(mg_str(""), &ip) == 1);
   ASSERT(mg_check_ip_acl(mg_str("invalid"), &ip) == -1);
@@ -3953,54 +4023,124 @@ static void test_crypto(void) {
   test_rsa();
 }
 
+
+#define DASHBOARD(x)  printf("HEALTH_DASHBOARD\t\"%s\": %s,\n", x, s_error ? "false":"true");
+
 int main(void) {
   const char *debug_level = getenv("V");
   if (debug_level == NULL) debug_level = "3";
   mg_log_set(atoi(debug_level));
 
+  s_error = false;
   test_crypto();
+  DASHBOARD("crypto");
+
+  s_error = false;
   test_split();
-  test_json();
+  test_util();
-  test_queue();
-  test_rpc();
   test_str();
   test_match();
+  test_crc32();
+  DASHBOARD("misc");
+
+  s_error = false;
+  test_json();
+  DASHBOARD("json");
+
+  s_error = false;
+  test_queue();
+  DASHBOARD("queue");
+
+  s_error = false;
+  test_rpc();
+  DASHBOARD("rpc");
+
+  s_error = false;
+  test_check_ip_acl();
+  DASHBOARD("ip_acl");
+
+  s_error = false;
+  test_udp();
+  DASHBOARD("udp");
+
+  s_error = false;
   test_get_header_var();
+  test_http_get_var();
   test_http_parse();
   test_rewrites();
-  test_check_ip_acl();
-  test_udp();
-  test_packed();
-  test_crc32();
   test_multipart();
   test_invalid_listen_addr();
   test_http_chunked();
-  test_http_upload();
+  DASHBOARD("http_support");
-  test_http_stream_buffer();
+
-  test_util();
+  s_error = false;
+  test_packed();
+  DASHBOARD("packed_fs");
+
+  s_error = false;
   test_dns();
+  DASHBOARD("dns");
+
+  s_error = false;
   test_timer();
+  DASHBOARD("timers");
+
+  s_error = false;
   test_url();
+  DASHBOARD("url");
+
+  s_error = false;
   test_iobuf();
+  DASHBOARD("iobuf");
+
+  s_error = false;
   test_base64();
-  test_http_get_var();
+  DASHBOARD("base64");
+
+  s_error = false;
   test_tls();
+  DASHBOARD("tls");
+
+  s_error = false;
   test_ws();
   test_ws_fragmentation();
+  DASHBOARD("ws");
+
+  s_error = false;
+  test_http_upload();
+  test_http_stream_buffer();
   test_http_server();
   test_http_404();
   test_http_no_content_length();
   test_http_pipeline();
   test_http_range();
+  DASHBOARD("http_server");
+
 #ifndef LOCALHOST_ONLY
+  s_error = false;
   test_sntp();
+  DASHBOARD("sntp");
+
+  s_error = false;
   test_mqtt();  // sorry, MQTT_LOCALHOST is also skipped 
+  DASHBOARD("mqtt");
+
+  s_error = false;
   test_http_client();
+  DASHBOARD("http_client");
+
 #else
   (void) test_sntp, (void) test_mqtt, (void) test_http_client;
 #endif
+  s_error = false;
   test_poll();
-  printf("SUCCESS. Total tests: %d\n", s_num_tests);
+  printf("HEALTH_DASHBOARD\t\"poll\": %s\n", s_error ? "false":"true");
+ // last entry with no comma
 
+#ifdef NO_ABORT
+  if (s_abort != 0) return EXIT_FAILURE;
+#endif
+
+  printf("SUCCESS. Total tests: %d\n", s_num_tests);
   return EXIT_SUCCESS;
 }

tutorials/core/memory/o1heap/Makefile

@@ -0,0 +1,33 @@
+SOURCES = main.c mongoose.c       # Source code files
+CFLAGS = -W -Wall -Wextra -g -I.  # Build options
+
+# O(1) Heap
+SOURCES += o1heap/o1heap/o1heap.c
+CFLAGS += -Io1heap/o1heap
+
+# Mongoose build options. See https://mongoose.ws/documentation/#build-options
+CFLAGS_MONGOOSE += -DMG_ENABLE_CUSTOM_CALLOC
+
+ifeq ($(OS),Windows_NT)
+  # Windows settings. Assume MinGW compiler. To use VC: make CC=cl CFLAGS=/MD
+  PROG ?= example.exe                 # Use .exe suffix for the binary
+  CC = gcc                            # Use MinGW gcc compiler
+  CFLAGS += -lws2_32                  # Link against Winsock library
+  DELETE = cmd /C del /f /q /s        # Command prompt command to delete files
+else
+  # Mac, Linux
+  PROG ?= example
+  DELETE = rm -rf
+endif
+
+all: $(PROG)
+	$(RUN) ./$(PROG) $(ARGS)
+
+$(PROG): $(SOURCES)
+	$(CC) $(SOURCES) $(CFLAGS) $(CFLAGS_MONGOOSE) $(CFLAGS_EXTRA) -o $@
+
+o1heap/o1heap/o1heap.c:  # O(1) Heap sources
+	git clone --depth 1 -b 2.1.0 https://github.com/pavel-kirienko/o1heap.git
+
+clean:
+	$(DELETE) $(PROG) *.o *.obj *.exe *.dSYM

tutorials/core/memory/o1heap/main.c

@@ -0,0 +1,77 @@
+// Copyright (c) 2025 Cesanta Software Limited
+// All rights reserved
+
+#include "mongoose.h"
+#include "o1heap.h"
+
+#define POOL_SIZE (5 * MG_IO_SIZE)
+
+O1HeapInstance *s_mem;
+
+// memory allocation
+void *mg_calloc(size_t count, size_t size) {
+  size_t bytes = count * size;
+  void *ptr = o1heapAllocate(s_mem, bytes);
+  if (ptr != NULL) memset(ptr, 0, bytes);
+  if (ptr != NULL) MG_DEBUG(("%lu bytes @%p", bytes, ptr));
+  if (ptr == NULL) MG_ERROR(("Failed to allocate %lu bytes", bytes));
+  return ptr;
+}
+
+void mg_free(void *ptr) {
+  o1heapFree(s_mem, ptr);
+  if (ptr != NULL) MG_DEBUG(("block @%p", ptr));
+}
+
+// HTTP request callback
+static void fn(struct mg_connection *c, int ev, void *ev_data) {
+  if (ev == MG_EV_HTTP_MSG) {
+    struct mg_http_message *hm = (struct mg_http_message *) ev_data;
+    if (mg_match(hm->uri, mg_str("/hi"), NULL)) {
+      mg_http_reply(c, 200, "Host: foo.com\r\n", "hi\n");
+    } else if (mg_match(hm->uri, mg_str("/echo"), NULL)) {
+      mg_http_reply(c, 200, "", "%.*s", (int) hm->body.len, hm->body.buf);
+    } else if (mg_match(hm->uri, mg_str("/stats"), NULL)) {
+      struct mg_connection *t;
+      mg_printf(c, "HTTP/1.1 200 OK\r\nTransfer-Encoding: chunked\r\n\r\n");
+      mg_http_printf_chunk(c, "ID PROTO TYPE      LOCAL           REMOTE\n");
+      for (t = c->mgr->conns; t != NULL; t = t->next) {
+        mg_http_printf_chunk(c, "%-3lu %4s %s %M %M\n", t->id,
+                             t->is_udp ? "UDP" : "TCP",
+                             t->is_listening  ? "LISTENING"
+                             : t->is_accepted ? "ACCEPTED "
+                                              : "CONNECTED",
+                             mg_print_ip, &t->loc, mg_print_ip, &t->rem);
+      }
+      mg_http_printf_chunk(c, "");  // Don't forget the last empty chunk
+    } else {
+      struct mg_http_serve_opts opts;
+      memset(&opts, 0, sizeof(opts));
+      opts.root_dir = ".";
+      mg_http_serve_dir(c, ev_data, &opts);
+    }
+  }
+}
+
+int main(void) {
+  struct mg_mgr mgr;
+
+  void *pool = malloc(POOL_SIZE + O1HEAP_ALIGNMENT);
+  void *aligned = (void *) (((uintptr_t) pool) & ~(O1HEAP_ALIGNMENT - 1));
+  O1HeapDiagnostics d;
+  s_mem = o1heapInit(aligned, POOL_SIZE);
+  d = o1heapGetDiagnostics(s_mem);
+  MG_INFO(
+      ("Created aligned %lu-byte pool @%p, out of a %lu-byte allocated system "
+       "memory pool",
+       d.capacity, s_mem, POOL_SIZE));
+
+  mg_mgr_init(&mgr);        // Initialise event manager
+  mg_log_set(MG_LL_DEBUG);  // Set debug log level
+  mg_http_listen(&mgr, "http://localhost:8000", fn, NULL);  // Create listener
+  for (;;) {                                                // Event loop
+    mg_mgr_poll(&mgr, 1000);
+  }
+  mg_mgr_free(&mgr);
+  return 0;
+}

tutorials/core/memory/o1heap/mongoose.c

@@ -0,0 +1 @@
+../../../../mongoose.c

tutorials/core/memory/o1heap/mongoose.h

@@ -0,0 +1 @@
+../../../../mongoose.h

tutorials/http/device-dashboard/esp32/main/wifi.c

@@ -79,7 +79,7 @@ void wifi_init(const char *ssid, const char *pass) {
   snprintf((char *) c.sta.ssid, sizeof(c.sta.ssid), "%s", ssid);
   snprintf((char *) c.sta.password, sizeof(c.sta.password), "%s", pass);
   ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA));
-  ESP_ERROR_CHECK(esp_wifi_set_config(ESP_IF_WIFI_STA, &c));
+  ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &c));
   ESP_ERROR_CHECK(esp_wifi_start());
   MG_DEBUG(("wifi_init_sta finished."));
 

tutorials/http/uart-bridge/esp32/main/uart.c

@@ -1,4 +1,5 @@
 #include "main.h"
+#include "esp_idf_version.h"  // < 3.3 not supported, sadly
 
 int uart_close(int no) {
   return uart_driver_delete(no);
@@ -18,7 +19,11 @@ int uart_open(int no, int rx, int tx, int cts, int rts, int baud) {
   int e1 = uart_param_config(no, &uart_config);
   int e2 = uart_set_pin(no, tx, rx, rts, cts);
   int e3 =
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 2, 5)
+      uart_driver_install(no, UART_HW_FIFO_LEN(no) * 2, UART_HW_FIFO_LEN(no) * 2, 0, NULL, 0);
+#else
       uart_driver_install(no, UART_FIFO_LEN * 2, UART_FIFO_LEN * 2, 0, NULL, 0);
+#endif
   MG_INFO(("%d: %d/%d/%d, %d %d %d", no, rx, tx, baud, e1, e2, e3));
   if (e1 != ESP_OK || e2 != ESP_OK || e3 != ESP_OK) return -1;
   return no;

tutorials/http/uart-bridge/esp32/main/wifi.c

@@ -81,7 +81,7 @@ bool wifi_init(const char *ssid, const char *pass) {
   snprintf((char *) c.sta.ssid, sizeof(c.sta.ssid), "%s", ssid);
   snprintf((char *) c.sta.password, sizeof(c.sta.password), "%s", pass);
   ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA));
-  ESP_ERROR_CHECK(esp_wifi_set_config(ESP_IF_WIFI_STA, &c));
+  ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &c));
   ESP_ERROR_CHECK(esp_wifi_start());
   MG_DEBUG(("wifi_init_sta finished."));
 

tutorials/infineon/xmc47_relax-make-baremetal-builtin/Makefile

@@ -9,8 +9,8 @@ firmware.bin: wizard
 	make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/mongoose ; rm mongoose.[ch] ; ln -s ../../../../../mongoose.c ; ln -s ../../../../../mongoose.h
 

tutorials/infineon/xmc72_evk-make-baremetal-builtin/Makefile

@@ -9,8 +9,8 @@ firmware.bin: wizard
 	make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/mongoose ; rm mongoose.[ch] ; ln -s ../../../../../mongoose.c ; ln -s ../../../../../mongoose.h
 

tutorials/infineon/xmc_plt2go_4400-make-baremetal-builtin/Makefile

@@ -9,8 +9,8 @@ firmware.bin: wizard
 	make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/mongoose ; rm mongoose.[ch] ; ln -s ../../../../../mongoose.c ; ln -s ../../../../../mongoose.h
 

tutorials/nxp/frdm-mcxn947-make-baremetal-builtin/Makefile

@@ -9,8 +9,8 @@ firmware.bin: wizard
 	make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/mongoose ; rm mongoose.[ch] ; ln -s ../../../../../mongoose.c ; ln -s ../../../../../mongoose.h
 

tutorials/nxp/frdm-mcxn947-make-freertos-builtin/Makefile

@@ -9,8 +9,8 @@ firmware.bin: wizard
 	make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/mongoose ; rm mongoose.[ch] ; ln -s ../../../../../mongoose.c ; ln -s ../../../../../mongoose.h
 

tutorials/nxp/frdm-mcxn947-xpresso-baremetal-builtin/Makefile

@@ -17,8 +17,8 @@ firmware.axf: wizard
 	cp wizard/$(TARGET)/$$PROJNAME.axf firmware.axf
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/source ; rm mongoose.[ch] ; cp -rL ../../../../../mongoose.[ch] .
 

tutorials/nxp/frdm-mcxn947-xpresso-freertos-builtin/Makefile

@@ -17,8 +17,8 @@ firmware.axf: wizard
 	cp wizard/$(TARGET)/$$PROJNAME.axf firmware.axf
 
 wizard:
-	hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
+	hash=$$(curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
-	&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
+	&& curl -H 'Cookie: mongoose_wizard_uid=F2PPlAgQCqSthV1g' -s $(WIZARD_URL)/api/zip -o wizard.zip
 	unzip wizard.zip
 	cd wizard/source ; rm mongoose.[ch] ; cp -rL ../../../../../mongoose.[ch] .
 

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.cproject

@@ -0,0 +1,897 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.crt.advproject.config.exe.debug.252552941">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.252552941" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.252552941" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; # arm-none-eabi-objcopy -v -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+					<folderInfo id="com.crt.advproject.config.exe.debug.252552941." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.exe.debug.1082653760" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1289303214" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+							<builder buildPath="${workspace_loc:/frdmrw612_wifi_webconfig}/Debug" id="com.crt.advproject.builder.exe.debug.1379385878" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+							<tool id="com.crt.advproject.cpp.exe.debug.20078202" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
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+								<option id="com.crt.advproject.link.config.1922487468" name="Obsolete (Config)" superClass="com.crt.advproject.link.config"/>
+								<option id="com.crt.advproject.link.store.908213121" name="Obsolete (Store)" superClass="com.crt.advproject.link.store"/>
+								<option id="com.crt.advproject.link.securestate.1237011711" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate"/>
+								<option id="com.crt.advproject.link.sgstubs.placement.1953785846" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement"/>
+								<option id="com.crt.advproject.link.sgstubenable.1364235338" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable"/>
+								<option id="com.crt.advproject.link.nonsecureobject.38053095" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject"/>
+								<option id="com.crt.advproject.link.inimplib.1183785230" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
+								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.2025198933" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.crt.advproject.tool.debug.release.1082520937" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.release">
+								<option id="com.crt.advproject.miscellaneous.end_of_heap.1818360975" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
+								<option id="com.crt.advproject.miscellaneous.pvHeapStart.2144777792" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart"/>
+								<option id="com.crt.advproject.miscellaneous.pvHeapLimit.1762095255" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit"/>
+								<option id="com.crt.advproject.debugger.security.nonsecureimageenable.1515614492" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
+								<option id="com.crt.advproject.debugger.security.nonsecureimage.1090477179" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage"/>
+								<option id="com.crt.advproject.linkserver.debug.prevent.release.59864048" name="Prevent Debugging" superClass="com.crt.advproject.linkserver.debug.prevent.release"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="flash"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="linkscripts"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="wifi"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="frdmrw612_wifi_webconfig.null.470491832" name="frdmrw612_wifi_webconfig" projectType="com.crt.advproject.projecttype.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.438620977;com.crt.advproject.config.exe.release.438620977.;com.crt.advproject.gas.exe.release.1383944148;com.crt.advproject.assembler.input.681352778">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.252552941;com.crt.advproject.config.exe.debug.252552941.;com.crt.advproject.gcc.exe.debug.587026796;com.crt.advproject.compiler.input.1621627363">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.252552941;com.crt.advproject.config.exe.debug.252552941.;com.crt.advproject.gas.exe.debug.64345950;com.crt.advproject.assembler.input.67269995">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.438620977;com.crt.advproject.config.exe.release.438620977.;com.crt.advproject.gcc.exe.release.1059172906;com.crt.advproject.compiler.input.1119421287">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
+		<sdkName>SDK_2.x_FRDM-RW612</sdkName>
+		<sdkExample>frdmrw612_wifi_webconfig</sdkExample>
+		<sdkVersion>2.16.100</sdkVersion>
+		<sdkComponents>middleware.wifi.imu.RW612;middleware.wifi.wifidriver.RW612;platform.drivers.flexcomm_usart_freertos.RW612;component.osa_free_rtos.RW612;driver.conn_fwloader.RW612;component.mflash.frdmrw612.RW612;component.mflash_file.RW612;component.wireless_imu_adapter.RW612;utility.debug_console.RW612;platform.utilities.assert.RW612;middleware.lwip.apps.httpsrv.RW612;platform.drivers.clock.RW612;middleware.freertos-kernel.heap_3.RW612;middleware.wifi.RW612;middleware.lwip.RW612;middleware.edgefast_wifi_nxp.RW612;middleware.freertos-kernel.cm33_non_trustzone.RW612;platform.drivers.flash_config.frdmrw612.RW612;device.RW612_CMSIS.RW612;device.RW612_startup.RW612;platform.drivers.reset.RW612;platform.drivers.flexspi.RW612;platform.drivers.cache_cache64.RW612;platform.drivers.cns_io_mux.RW612;platform.drivers.lpc_gpio.RW612;platform.drivers.power.RW612;platform.drivers.ocotp.RW612;component.els_pkc.platform.rw61x_standalone_clib_gdet_sensor.RW612;platform.utilities.misc_utilities.RW612;middleware.wifi.common_files.RW612;platform.drivers.imu.RW612;middleware.wifi.osa.RW612;middleware.wifi.osa_free_rtos.RW612;platform.drivers.common.RW612;middleware.wifi.template.RW612;middleware.wifi.net.RW612;component.wifi_bt_module.tx_pwr_limits.RW612;middleware.wifi.net_free_rtos.RW612;middleware.lwip.apps.lwiperf.RW612;middleware.freertos-kernel.RW612;middleware.freertos-kernel.template.RW612;middleware.freertos-kernel.extension.RW612;platform.drivers.flexcomm.RW612;platform.drivers.flexcomm_usart.RW612;component.lists.RW612;component.osa_interface.RW612;component.mflash.common.RW612;platform.drivers.gdma.RW612;component.serial_manager.RW612;utility.str.RW612;component.serial_manager_uart.RW612;component.usart_adapter.RW612;middleware.lwip.template.RW612;middleware.lwip.sys_arch_dynamic.RW612;CMSIS_Include_core_cm.RW612;device.RW612_system.RW612;component.els_pkc.els_header_only.RW612;component.els_pkc.els_common.RW612;component.els_pkc.memory.RW612;component.els_pkc.standalone_gdet.RW612;component.els_pkc.platform.rw61x_inf_header_only.RW612;component.els_pkc.buffer.RW612;component.els_pkc.core.RW612;component.els_pkc.param_integrity.RW612;component.els_pkc.flow_protection.RW612;component.els_pkc.secure_counter.RW612;component.els_pkc.pre_processor.RW612;component.els_pkc.toolchain.RW612;component.els_pkc.data_integrity.RW612;frdmrw612_wifi_webconfig;</sdkComponents>
+		<boardId>frdmrw612</boardId>
+		<package>RW612ETA2I</package>
+		<core>cm33_nodsp</core>
+		<coreId>cm33_RW612</coreId>
+	</storageModule>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;
+&lt;TargetConfig&gt;
+&lt;Properties property_3="NXP" property_4="RW612" property_count="5" version="100300"/&gt;
+&lt;infoList vendor="NXP"&gt;
+&lt;info chip="RW612" name="RW612"&gt;
+&lt;chip&gt;
+&lt;name&gt;RW612&lt;/name&gt;
+&lt;family&gt;RW61X&lt;/family&gt;
+&lt;vendor&gt;NXP&lt;/vendor&gt;
+&lt;memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/&gt;
+&lt;memory id="RAM" size="1216" type="RAM"/&gt;
+&lt;memoryInstance derived_from="Flash" driver="RW61X_FlexSPI_A_SFDP_QSPI.cfx" edited="true" id="QSPI_FLASH" location="0x8000000" size="0x800000"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="SRAM" location="0x20000000" size="0x130000"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="MBOX1" location="0x41380000" size="0x488"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="TXQ1" location="0x41380488" size="0x1000"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="MBOX2" location="0x443c0000" size="0x488"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="TXQ23" location="0x443c0488" size="0x1080"/&gt;
+&lt;memoryInstance derived_from="RAM" edited="true" id="TXQ32" location="0x443c1508" size="0x1080"/&gt;
+&lt;/chip&gt;
+&lt;processor&gt;
+&lt;name gcc_name="cortex-m33-nodsp"&gt;Cortex-M33 (No DSP)&lt;/name&gt;
+&lt;family&gt;Cortex-M&lt;/family&gt;
+&lt;/processor&gt;
+&lt;/info&gt;
+&lt;/infoList&gt;
+&lt;/TargetConfig&gt;</projectStorage>
+	</storageModule>
+	<storageModule moduleId="openCmsis"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug"/>
+		<configuration configurationName="Release">
+			<resource resourceType="PROJECT" workspacePath="/frdm-rw612-xpresso-freertos-lwip"/>
+		</configuration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.default_mex

@@ -0,0 +1 @@
+frdm-rw612-xpresso-freertos-builtin.mex

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.project

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>frdm-rw612-xpresso-freertos-builtin</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+	</natures>
+</projectDescription>

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/language.settings.xml

@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.crt.advproject.config.exe.debug.252552941" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
+			<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="452102550212881743" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+		</extension>
+	</configuration>
+	<configuration id="com.crt.advproject.config.exe.release.438620977" name="Release">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+			<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="470729173164118281" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+		</extension>
+	</configuration>
+</project>

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.5
+ * @date     02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/mpu_armv8.h

@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/CMSIS/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug.ld

@@ -0,0 +1,453 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Generated linker script file for RW612
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v24.12 [Build 148] [2025-01-10] on Sep 10, 2025, 4:53:33 PM
+ */
+
+INCLUDE "frdm-rw612-xpresso-freertos-builtin_Debug_library.ld"
+INCLUDE "frdm-rw612-xpresso-freertos-builtin_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+     /* Offset .text by 0x1000 bytes, which whill be added by the image tool*/
+    .boot_hdr : ALIGN(4)
+    {
+        FILL(0xFF)
+        . = 0x400;
+        __FLASH_BASE = .;
+        KEEP(*(.flash_conf))
+        . = 0x1000;
+    } > QSPI_FLASH
+
+    /* MAIN TEXT SECTION */
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.) ;
+        KEEP(*(.isr_vector))
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data));
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2));
+        LONG(  SIZEOF(.data_RAM2));
+        LONG(LOADADDR(.data_RAM3));
+        LONG(    ADDR(.data_RAM3));
+        LONG(  SIZEOF(.data_RAM3));
+        LONG(LOADADDR(.data_RAM4));
+        LONG(    ADDR(.data_RAM4));
+        LONG(  SIZEOF(.data_RAM4));
+        LONG(LOADADDR(.data_RAM5));
+        LONG(    ADDR(.data_RAM5));
+        LONG(  SIZEOF(.data_RAM5));
+        LONG(LOADADDR(.data_RAM6));
+        LONG(    ADDR(.data_RAM6));
+        LONG(  SIZEOF(.data_RAM6));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        LONG(    ADDR(.bss_RAM3));
+        LONG(  SIZEOF(.bss_RAM3));
+        LONG(    ADDR(.bss_RAM4));
+        LONG(  SIZEOF(.bss_RAM4));
+        LONG(    ADDR(.bss_RAM5));
+        LONG(  SIZEOF(.bss_RAM5));
+        LONG(    ADDR(.bss_RAM6));
+        LONG(  SIZEOF(.bss_RAM6));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+
+        *(.after_vectors*)
+
+        *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)       KEEP(*freertos*/tasks.o(.rodata*)) /* FreeRTOS Debug Config */
+       *(.rodata)
+       *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o).rodata.*)
+       *(.constdata .constdata.*)
+       . = ALIGN(4);
+
+    } > QSPI_FLASH
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > QSPI_FLASH
+
+    .ARM.exidx : ALIGN(4)
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > QSPI_FLASH
+ 
+    _etext = .;
+        
+    /* DATA section for MBOX1 */
+
+    .data_RAM2 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM2 = .) ;
+        PROVIDE(__start_data_MBOX1 = .) ;
+        *(.ramfunc.$RAM2)
+        *(.ramfunc.$MBOX1)
+        *(.data.$RAM2)
+        *(.data.$MBOX1)
+        *(.data.$RAM2.*)
+        *(.data.$MBOX1.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM2 = .) ;
+        PROVIDE(__end_data_MBOX1 = .) ;
+     } > MBOX1 AT>QSPI_FLASH
+
+    /* DATA section for TXQ1 */
+
+    .data_RAM3 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM3 = .) ;
+        PROVIDE(__start_data_TXQ1 = .) ;
+        *(.ramfunc.$RAM3)
+        *(.ramfunc.$TXQ1)
+        *(.data.$RAM3)
+        *(.data.$TXQ1)
+        *(.data.$RAM3.*)
+        *(.data.$TXQ1.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM3 = .) ;
+        PROVIDE(__end_data_TXQ1 = .) ;
+     } > TXQ1 AT>QSPI_FLASH
+
+    /* DATA section for MBOX2 */
+
+    .data_RAM4 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM4 = .) ;
+        PROVIDE(__start_data_MBOX2 = .) ;
+        *(.ramfunc.$RAM4)
+        *(.ramfunc.$MBOX2)
+        *(.data.$RAM4)
+        *(.data.$MBOX2)
+        *(.data.$RAM4.*)
+        *(.data.$MBOX2.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM4 = .) ;
+        PROVIDE(__end_data_MBOX2 = .) ;
+     } > MBOX2 AT>QSPI_FLASH
+
+    /* DATA section for TXQ23 */
+
+    .data_RAM5 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM5 = .) ;
+        PROVIDE(__start_data_TXQ23 = .) ;
+        *(.ramfunc.$RAM5)
+        *(.ramfunc.$TXQ23)
+        *(.data.$RAM5)
+        *(.data.$TXQ23)
+        *(.data.$RAM5.*)
+        *(.data.$TXQ23.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM5 = .) ;
+        PROVIDE(__end_data_TXQ23 = .) ;
+     } > TXQ23 AT>QSPI_FLASH
+
+    /* DATA section for TXQ32 */
+
+    .data_RAM6 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM6 = .) ;
+        PROVIDE(__start_data_TXQ32 = .) ;
+        *(.ramfunc.$RAM6)
+        *(.ramfunc.$TXQ32)
+        *(.data.$RAM6)
+        *(.data.$TXQ32)
+        *(.data.$RAM6.*)
+        *(.data.$TXQ32.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM6 = .) ;
+        PROVIDE(__end_data_TXQ32 = .) ;
+     } > TXQ32 AT>QSPI_FLASH
+
+    /* MAIN DATA SECTION */
+    .uninit_RESERVED (NOLOAD) : ALIGN(4)
+    {
+        _start_uninit_RESERVED = .;
+        KEEP(*(.bss.$RESERVED*))
+       . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > SRAM AT> SRAM
+
+    /* Main DATA section (SRAM) */
+    .data : ALIGN(4)
+    {
+       FILL(0xff)
+       _data = . ;
+       PROVIDE(__start_data_RAM = .) ;
+       PROVIDE(__start_data_SRAM = .) ;
+       *(vtable)
+       *(.ramfunc*)
+       KEEP(*(CodeQuickAccess))
+       KEEP(*(DataQuickAccess))
+       *(RamFunction)
+       *mflash_drv.o(.text .text* .rodata .rodata*)
+       *fsl_flexspi.o(.text .text* .rodata .rodata*)
+       *(.data*)
+       . = ALIGN(4) ;
+       _edata = . ;
+       PROVIDE(__end_data_RAM = .) ;
+       PROVIDE(__end_data_SRAM = .) ;
+    } > SRAM AT>QSPI_FLASH
+
+    /* BSS section for MBOX1 */
+    .bss_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM2 = .) ;
+       PROVIDE(__start_bss_MBOX1 = .) ;
+       *(.bss.$RAM2)
+       *(.bss.$MBOX1)
+       *(.bss.$RAM2.*)
+       *(.bss.$MBOX1.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM2 = .) ;
+       PROVIDE(__end_bss_MBOX1 = .) ;
+    } > MBOX1 AT> MBOX1
+
+    /* BSS section for TXQ1 */
+    .bss_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM3 = .) ;
+       PROVIDE(__start_bss_TXQ1 = .) ;
+       *(.bss.$RAM3)
+       *(.bss.$TXQ1)
+       *(.bss.$RAM3.*)
+       *(.bss.$TXQ1.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM3 = .) ;
+       PROVIDE(__end_bss_TXQ1 = .) ;
+    } > TXQ1 AT> TXQ1
+
+    /* BSS section for MBOX2 */
+    .bss_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM4 = .) ;
+       PROVIDE(__start_bss_MBOX2 = .) ;
+       *(.bss.$RAM4)
+       *(.bss.$MBOX2)
+       *(.bss.$RAM4.*)
+       *(.bss.$MBOX2.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM4 = .) ;
+       PROVIDE(__end_bss_MBOX2 = .) ;
+    } > MBOX2 AT> MBOX2
+
+    /* BSS section for TXQ23 */
+    .bss_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM5 = .) ;
+       PROVIDE(__start_bss_TXQ23 = .) ;
+       *(.bss.$RAM5)
+       *(.bss.$TXQ23)
+       *(.bss.$RAM5.*)
+       *(.bss.$TXQ23.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM5 = .) ;
+       PROVIDE(__end_bss_TXQ23 = .) ;
+    } > TXQ23 AT> TXQ23
+
+    /* BSS section for TXQ32 */
+    .bss_RAM6 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM6 = .) ;
+       PROVIDE(__start_bss_TXQ32 = .) ;
+       *(.bss.$RAM6)
+       *(.bss.$TXQ32)
+       *(.bss.$RAM6.*)
+       *(.bss.$TXQ32.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM6 = .) ;
+       PROVIDE(__end_bss_TXQ32 = .) ;
+    } > TXQ32 AT> TXQ32
+
+    /* MAIN BSS SECTION */
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        _bss = .;
+        PROVIDE(__start_bss_RAM = .) ;
+        PROVIDE(__start_bss_SRAM = .) ;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(__end_bss_RAM = .) ;
+        PROVIDE(__end_bss_SRAM = .) ;
+        PROVIDE(end = .);
+    } > SRAM AT> SRAM
+
+    /* NOINIT section for MBOX1 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM2 = .) ;
+       PROVIDE(__start_noinit_MBOX1 = .) ;
+       *(.noinit.$RAM2)
+       *(.noinit.$MBOX1)
+       *(.noinit.$RAM2.*)
+       *(.noinit.$MBOX1.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM2 = .) ;
+       PROVIDE(__end_noinit_MBOX1 = .) ;
+    } > MBOX1 AT> MBOX1
+
+    /* NOINIT section for TXQ1 */
+    .noinit_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM3 = .) ;
+       PROVIDE(__start_noinit_TXQ1 = .) ;
+       *(.noinit.$RAM3)
+       *(.noinit.$TXQ1)
+       *(.noinit.$RAM3.*)
+       *(.noinit.$TXQ1.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM3 = .) ;
+       PROVIDE(__end_noinit_TXQ1 = .) ;
+    } > TXQ1 AT> TXQ1
+
+    /* NOINIT section for MBOX2 */
+    .noinit_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM4 = .) ;
+       PROVIDE(__start_noinit_MBOX2 = .) ;
+       *(.noinit.$RAM4)
+       *(.noinit.$MBOX2)
+       *(.noinit.$RAM4.*)
+       *(.noinit.$MBOX2.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM4 = .) ;
+       PROVIDE(__end_noinit_MBOX2 = .) ;
+    } > MBOX2 AT> MBOX2
+
+    /* NOINIT section for TXQ23 */
+    .noinit_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM5 = .) ;
+       PROVIDE(__start_noinit_TXQ23 = .) ;
+       *(.noinit.$RAM5)
+       *(.noinit.$TXQ23)
+       *(.noinit.$RAM5.*)
+       *(.noinit.$TXQ23.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM5 = .) ;
+       PROVIDE(__end_noinit_TXQ23 = .) ;
+    } > TXQ23 AT> TXQ23
+
+    /* NOINIT section for TXQ32 */
+    .noinit_RAM6 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM6 = .) ;
+       PROVIDE(__start_noinit_TXQ32 = .) ;
+       *(.noinit.$RAM6)
+       *(.noinit.$TXQ32)
+       *(.noinit.$RAM6.*)
+       *(.noinit.$TXQ32.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM6 = .) ;
+       PROVIDE(__end_noinit_TXQ32 = .) ;
+    } > TXQ32 AT> TXQ32
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        PROVIDE(__start_noinit_RAM = .) ;
+        PROVIDE(__start_noinit_SRAM = .) ;
+        *(.noinit*)
+        . = ALIGN(4) ;
+        _end_noinit = .;
+        PROVIDE(__end_noinit_RAM = .) ;
+        PROVIDE(__end_noinit_SRAM = .) ;
+    } > SRAM AT> SRAM
+
+    .smu_cpu13_mbox (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu13_mbox)
+        KEEP (*(.smu_cpu13_mbox))
+        . = ALIGN(4);
+    } > MBOX1 AT> MBOX1
+
+    .smu_cpu31_txq (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu31_txq)
+        KEEP (*(.smu_cpu31_txq))
+        . = ALIGN(4);
+    } > TXQ1 AT> TXQ1
+
+    .smu_cpu23_mbox (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu23_mbox)
+        KEEP (*(.smu_cpu23_mbox))
+        . = ALIGN(4);
+    } > MBOX2 AT> MBOX2
+
+    .smu_cpu32_txq (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.smu_cpu32_txq)
+        KEEP (*(.smu_cpu32_txq))
+        . = ALIGN(4);
+    } > TXQ32 AT> TXQ32
+
+    /* Reserve and place Heap within memory map */
+    _HeapSize = 0x20000;
+    .heap (NOLOAD) :  ALIGN(4)
+    {
+        _pvHeapStart = .;
+        . += _HeapSize;
+        . = ALIGN(4);
+        _pvHeapLimit = .;
+    } > SRAM
+
+     _StackSize = 0x800;
+     /* Reserve space in memory for Stack */
+    .heap2stackfill (NOLOAD) :
+    {
+        . += _StackSize;
+    } > SRAM
+    /* Locate actual Stack in memory map */
+    .stack ORIGIN(SRAM) + LENGTH(SRAM) - _StackSize - 0 (NOLOAD) :  ALIGN(4)
+    {
+        _vStackBase = .;
+        . = ALIGN(4);
+        _vStackTop = . + _StackSize;
+    } > SRAM
+
+    /* Provide basic symbols giving location and size of main text
+     * block, including initial values of RW data sections. Note that
+     * these will need extending to give a complete picture with
+     * complex images (e.g multiple Flash banks).
+     */
+    _image_start = LOADADDR(.text);
+    _image_end = LOADADDR(.data) + SIZEOF(.data);
+    _image_size = _image_end - _image_start;
+}

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_library.ld

@@ -0,0 +1,17 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Generated linker script file for RW612
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v24.12 [Build 148] [2025-01-10] on Sep 10, 2025, 4:53:33 PM
+ */
+
+GROUP (
+  "libgcc.a"
+  "libc_nano.a"
+  "libm.a"
+  "libcr_newlib_nohost.a"
+)

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/Debug/frdm-rw612-xpresso-freertos-builtin_Debug_memory.ld

@@ -0,0 +1,52 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2013-2025 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Generated linker script file for RW612
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v24.12 [Build 148] [2025-01-10] on Sep 10, 2025, 4:53:33 PM
+ */
+
+MEMORY
+{
+  /* Define each memory region */
+  QSPI_FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */  
+  SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x130000 /* 1216K bytes (alias RAM) */  
+  MBOX1 (rwx) : ORIGIN = 0x41380000, LENGTH = 0x488 /* 1160 bytes (alias RAM2) */  
+  TXQ1 (rwx) : ORIGIN = 0x41380488, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */  
+  MBOX2 (rwx) : ORIGIN = 0x443c0000, LENGTH = 0x488 /* 1160 bytes (alias RAM4) */  
+  TXQ23 (rwx) : ORIGIN = 0x443c0488, LENGTH = 0x1080 /* 4224 bytes (alias RAM5) */  
+  TXQ32 (rwx) : ORIGIN = 0x443c1508, LENGTH = 0x1080 /* 4224 bytes (alias RAM6) */  
+}
+
+  /* Define a symbol for the top of each memory region */
+  __base_QSPI_FLASH = 0x8000000  ; /* QSPI_FLASH */  
+  __base_Flash = 0x8000000 ; /* Flash */  
+  __top_QSPI_FLASH = 0x8000000 + 0x800000 ; /* 8M bytes */  
+  __top_Flash = 0x8000000 + 0x800000 ; /* 8M bytes */  
+  __base_SRAM = 0x20000000  ; /* SRAM */  
+  __base_RAM = 0x20000000 ; /* RAM */  
+  __top_SRAM = 0x20000000 + 0x130000 ; /* 1216K bytes */  
+  __top_RAM = 0x20000000 + 0x130000 ; /* 1216K bytes */  
+  __base_MBOX1 = 0x41380000  ; /* MBOX1 */  
+  __base_RAM2 = 0x41380000 ; /* RAM2 */  
+  __top_MBOX1 = 0x41380000 + 0x488 ; /* 1160 bytes */  
+  __top_RAM2 = 0x41380000 + 0x488 ; /* 1160 bytes */  
+  __base_TXQ1 = 0x41380488  ; /* TXQ1 */  
+  __base_RAM3 = 0x41380488 ; /* RAM3 */  
+  __top_TXQ1 = 0x41380488 + 0x1000 ; /* 4K bytes */  
+  __top_RAM3 = 0x41380488 + 0x1000 ; /* 4K bytes */  
+  __base_MBOX2 = 0x443c0000  ; /* MBOX2 */  
+  __base_RAM4 = 0x443c0000 ; /* RAM4 */  
+  __top_MBOX2 = 0x443c0000 + 0x488 ; /* 1160 bytes */  
+  __top_RAM4 = 0x443c0000 + 0x488 ; /* 1160 bytes */  
+  __base_TXQ23 = 0x443c0488  ; /* TXQ23 */  
+  __base_RAM5 = 0x443c0488 ; /* RAM5 */  
+  __top_TXQ23 = 0x443c0488 + 0x1080 ; /* 4224 bytes */  
+  __top_RAM5 = 0x443c0488 + 0x1080 ; /* 4224 bytes */  
+  __base_TXQ32 = 0x443c1508  ; /* TXQ32 */  
+  __base_RAM6 = 0x443c1508 ; /* RAM6 */  
+  __top_TXQ32 = 0x443c1508 + 0x1080 ; /* 4224 bytes */  
+  __top_RAM6 = 0x443c1508 + 0x1080 ; /* 4224 bytes */  

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/README.md

@@ -0,0 +1,4 @@
+This example assumes your FRDM-RW612 board already has the Wi-Fi submodule firmware already burned to flash. This seems to be the case for new boards.
+
+In case this is not so, please follow indications in NXP's "frdmrw612_wifi_webconfig" example, components/conn_fwloader/readme.txt
+

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.c

@@ -0,0 +1,437 @@
+/*
+ * Copyright 2021-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_clock.h"
+#include "board.h"
+#include "fsl_flexspi.h"
+#include "fsl_cache.h"
+#include "fsl_io_mux.h"
+#include "fsl_power.h"
+#include "fsl_ocotp.h"
+#include "mcuxClEls.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    uint32_t uartClkSrcFreq = 0;
+
+    /* attach FRG0 clock to FLEXCOMM3 (debug console) */
+    CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+    uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+static status_t flexspi_hyper_ram_run_seq(FLEXSPI_Type *base, uint32_t seqIndex)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+
+    /* Write data */
+    flashXfer.deviceAddress = 0U;
+    flashXfer.port          = kFLEXSPI_PortB1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = seqIndex;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    return status;
+}
+
+/* Initialize psram. */
+status_t BOARD_InitPsRam(void)
+{
+    flexspi_device_config_t psramConfig = {
+        .flexspiRootClk       = 106666667, /* 106MHZ SPI serial clock */
+        .isSck2Enabled        = false,
+        .flashSize            = 0x2000,    /* 64Mb/KByte */
+        .addressShift         = false,
+        .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
+        .CSInterval           = 0,
+        .CSHoldTime           = 3,
+        .CSSetupTime          = 3,
+        .dataValidTime        = 1,
+        .columnspace          = 0,
+        .enableWordAddress    = false,
+        .AWRSeqIndex          = 12,
+        .AWRSeqNumber         = 1,
+        .ARDSeqIndex          = 11,
+        .ARDSeqNumber         = 1,
+        .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+        .AHBWriteWaitInterval = 0,
+        .enableWriteMask      = true,
+    };
+
+    uint32_t psramLUT[16] = {
+        /* Read Data */
+        [0] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24),
+        [1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD,
+                              0x04),
+
+        /* Write Data */
+        [4] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24),
+        [5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* Reset Enable */
+        [8] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x66, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* Reset */
+        [12] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x99, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+    };
+
+    flexspi_config_t config;
+#if BOARD_ENABLE_PSRAM_CACHE
+    cache64_config_t cacheCfg;
+#endif
+    status_t status         = kStatus_Success;
+
+    if (!BOARD_IS_XIP()) /* FlexSPI not initialized */
+    {
+        CLOCK_EnableClock(kCLOCK_Flexspi);
+        RESET_ClearPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+        BOARD_SetFlexspiClock(FLEXSPI, 5U, 3U); /* 320M / 3 */
+
+        /* Get FLEXSPI default settings and configure the flexspi. */
+        FLEXSPI_GetDefaultConfig(&config);
+
+        /* Init FLEXSPI. */
+        config.rxSampleClock      = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
+        config.rxSampleClockPortB = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
+        config.rxSampleClockDiff  = false;
+        /*Set AHB buffer size for reading data through AHB bus. */
+        config.ahbConfig.enableAHBPrefetch    = true;
+        config.ahbConfig.enableAHBBufferable  = true;
+        config.ahbConfig.enableAHBCachable    = true;
+        config.ahbConfig.enableReadAddressOpt = true;
+        for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
+        {
+            config.ahbConfig.buffer[i].bufferSize = 0;
+        }
+        /* FlexSPI has total 1KB RX buffer.
+         * Set DMA0 master to use AHB Rx Buffer0.
+         */
+        config.ahbConfig.buffer[0].masterIndex    = 10;  /* GDMA */
+        config.ahbConfig.buffer[0].bufferSize     = 512; /* Allocate 512B bytes for DMA0 */
+        config.ahbConfig.buffer[0].enablePrefetch = true;
+        config.ahbConfig.buffer[0].priority       = 0;
+        /* All other masters use last buffer with 512B bytes. */
+        config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 512;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+        config.enableCombination = false;
+#endif
+        FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
+    }
+
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &psramConfig, kFLEXSPI_PortB1);
+
+    /* Update bottom LUT table (44-59). */
+    FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 44U, psramLUT, ARRAY_SIZE(psramLUT));
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
+
+    do
+    {
+        /* Reset PSRAM */
+        status = flexspi_hyper_ram_run_seq(BOARD_FLEXSPI_PSRAM, 13U);
+        if (status == kStatus_Success)
+        {
+            status = flexspi_hyper_ram_run_seq(BOARD_FLEXSPI_PSRAM, 14U);
+        }
+        if (status != kStatus_Success)
+        {
+            status = kStatus_Fail;
+            break;
+        }
+
+#if BOARD_ENABLE_PSRAM_CACHE
+        CACHE64_GetDefaultConfig(&cacheCfg);
+        /* Suppose:
+           Flash on PC bus starting from 0x08000000, controlled by cache 0.
+           PSRAM on PS bus starting from 0x28000000, controlled by cache 1.
+         */
+        CACHE64_Init(CACHE64_POLSEL1, &cacheCfg);
+        CACHE64_EnableWriteBuffer(CACHE64_CTRL1, true);
+        CACHE64_EnableCache(CACHE64_CTRL1);
+#endif
+    } while (false);
+
+    return status;
+}
+
+void BOARD_InitSleepPinConfig(void)
+{
+    int32_t i;
+
+    /* Set all non-AON pins output low level in sleep mode. */
+    for (i = 0; i < 22; i++)
+    {
+        IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+    }
+    for (i = 28; i < 64; i++)
+    {
+        IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+    }
+
+    /* Set RF_CNTL 0-3 output low level in sleep mode. */
+    for (i = 0; i < 4; i++)
+    {
+        IO_MUX_SetRfPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+    }
+}
+
+void BOARD_DeinitFlash(FLEXSPI_Type *base)
+{
+    /* Enable FLEXSPI clock again */
+    CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK;
+
+    /* Enable FLEXSPI module */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    /* Wait until FLEXSPI is not busy */
+    while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
+    {
+    }
+    /* Disable module during the reset procedure */
+    base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+}
+
+void BOARD_InitFlash(FLEXSPI_Type *base)
+{
+    uint32_t status;
+    uint32_t lastStatus;
+    uint32_t retry;
+
+    /* Loopback from DQS pad can maximize RD board flash speed. */
+    if ((base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) != FLEXSPI_MCR0_RXCLKSRC(1))
+    {
+        base->MCR0 = (base->MCR0 & ~FLEXSPI_MCR0_RXCLKSRC_MASK) | FLEXSPI_MCR0_RXCLKSRC(1);
+    }
+    /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is
+     * recommended. */
+    base->DLLCR[0] = 0x1U;
+
+    /* Enable FLEXSPI module */
+    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+    while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
+    {
+    }
+
+    /* Need to wait DLL locked if DLL enabled */
+    if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
+    {
+        lastStatus = base->STS2;
+        retry      = BOARD_FLEXSPI_DLL_LOCK_RETRY;
+        /* Wait slave delay line locked and slave reference delay line locked. */
+        do
+        {
+            status = base->STS2;
+            if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
+                (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK))
+            {
+                /* Locked */
+                retry = 100;
+                break;
+            }
+            else if (status == lastStatus)
+            {
+                /* Same delay cell number in calibration */
+                retry--;
+            }
+            else
+            {
+                retry      = BOARD_FLEXSPI_DLL_LOCK_RETRY;
+                lastStatus = status;
+            }
+        } while (retry > 0);
+        /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+        for (; retry > 0U; retry--)
+        {
+            __NOP();
+        }
+    }
+}
+
+/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
+void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
+{
+    if ((CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src)) ||
+        ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1)))
+    {
+        /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the
+         FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock
+         frequency. */
+        BOARD_DeinitFlash(base);
+
+        /* Disable clock before changing clock source */
+        CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK;
+        /* Update flexspi clock. */
+        CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
+        CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
+        CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
+        while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
+        {
+        }
+        /* Enable FLEXSPI clock again */
+        CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK;
+
+        BOARD_InitFlash(base);
+    }
+}
+
+static bool LoadGdetCfg(power_gdet_data_t *data)
+{
+    bool retval = true;
+
+    /* If T3 256M clock is disabled, GDET cannot work. */
+    if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_T3PLL_MCI_256M_CG_MASK) != 0U)
+    {
+        retval = false;
+    }
+    else
+    {
+        /* GDET clock has been characterzed to 64MHz */
+        CLKCTL0->ELS_GDET_CLK_SEL = CLKCTL0_ELS_GDET_CLK_SEL_SEL(2);
+    }
+
+    if (retval)
+    {
+        /* LOAD command */
+        MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GlitchDetector_LoadConfig_Async((uint8_t *)data));
+        if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GlitchDetector_LoadConfig_Async) != token) ||
+            (MCUXCLELS_STATUS_OK_WAIT != result))
+        {
+            retval = false;
+        }
+        MCUX_CSSL_FP_FUNCTION_CALL_END();
+    }
+
+    if (retval)
+    {
+        /* Wait for the mcuxClEls_GlitchDetector_LoadConfig_Async operation to complete. */
+        MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR));
+        if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
+        {
+            retval = false;
+        }
+        MCUX_CSSL_FP_FUNCTION_CALL_END();
+    }
+
+    return retval;
+}
+
+static void ConfigSvcSensor(void)
+{
+    uint64_t svc;
+    uint32_t pack;
+    status_t status;
+    power_gdet_data_t gdetData = {0U};
+    uint32_t rev = SOCCTRL->CHIP_INFO & SOCCIU_CHIP_INFO_REV_NUM_MASK;
+
+    status = OCOTP_ReadSVC(&svc);
+    if (status == kStatus_Success)
+    { /* CES */
+        status = OCOTP_ReadPackage(&pack);
+        if (status == kStatus_Success)
+        {
+            /*
+               A2 CES: Use SVC voltage.
+               A1 CES: Keep boot voltage 1.11V.
+             */
+            POWER_InitVoltage((rev == 2U) ? ((uint32_t)svc >> 16) : 0U, pack);
+        }
+
+        /* SVC GDET config */
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(149, &gdetData.CFG[0]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(150, &gdetData.CFG[1]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(151, &gdetData.CFG[2]) : status;
+        /* A2 CES load fuse 155 for trim calculation. A1 CES directly use the default trim value in fuse 152. */
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead((rev == 2U) ? 155 : 152, &gdetData.CFG[3]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(153, &gdetData.CFG[4]) : status;
+        status = (status == kStatus_Success) ? OCOTP_OtpFuseRead(154, &gdetData.CFG[5]) : status;
+        assert(status == kStatus_Success);
+
+        /* Must configure GDET load function for POWER_EnableGDetVSensors(). */
+        Power_InitLoadGdetCfg(LoadGdetCfg, &gdetData, pack);
+    }
+    else
+    {
+        /* A1/A2 non-CES */
+        SystemCoreClockUpdate();
+
+        /* LPBG trim */
+        BUCK11->BUCK_CTRL_EIGHTEEN_REG = 0x6U;
+        /* Change buck level */
+        PMU->PMIP_BUCK_LVL = PMU_PMIP_BUCK_LVL_SLEEP_BUCK18_SEL(0x60U) |  /* 1.8V */
+                             PMU_PMIP_BUCK_LVL_SLEEP_BUCK11_SEL(0x22U) |  /* 0.8V */
+                             PMU_PMIP_BUCK_LVL_NORMAL_BUCK18_SEL(0x60U) | /* 1.8V */
+                             PMU_PMIP_BUCK_LVL_NORMAL_BUCK11_SEL(0x54U);  /* 1.05V */
+        /* Delay 600us */
+        SDK_DelayAtLeastUs(600, SystemCoreClock);
+    }
+}
+
+/* This function is used to configure static voltage compansation and sensors, and in XIP case, change FlexSPI clock
+   to a stable source before clock tree(Such as PLL and Main clock) update */
+void BOARD_ClockPreConfig(void)
+{
+    OCOTP_OtpInit();
+    ConfigSvcSensor();
+    OCOTP_OtpDeinit();
+
+    if (BOARD_IS_XIP())
+    {
+        /* Move FLEXSPI clock source to T3 256m / 4 to avoid instruction/data fetch issue in XIP when
+         * updating PLL and main clock.
+         */
+        BOARD_SetFlexspiClock(FLEXSPI, 6U, 4U);
+    }
+    else
+    {
+        RESET_ClearPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+        BOARD_DeinitFlash(FLEXSPI);
+        CLOCK_AttachClk(kNONE_to_FLEXSPI_CLK);
+        CLOCK_DisableClock(kCLOCK_Flexspi);
+        RESET_SetPeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
+    }
+}
+
+/* Update FlexSPI clock source and set flash to full speed */
+void BOARD_ClockPostConfig(void)
+{
+    if (BOARD_IS_XIP())
+    {
+        /* Call function BOARD_SetFlexspiClock() to set clock source to aux0_pll_clk. */
+        BOARD_SetFlexspiClock(FLEXSPI, 2U, 2U);
+    }
+    else
+    {
+    }
+}

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/board.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright 2021-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "FRDM-RW612"
+
+/*! @brief Macro to judge XIP */
+#define BOARD_IS_XIP()                                                                                          \
+    ((((uint32_t)BOARD_InitDebugConsole >= 0x08000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x10000000U)) || \
+     (((uint32_t)BOARD_InitDebugConsole >= 0x18000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U)))
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE     kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) FLEXCOMM3
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART          USART3
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexCommClkFreq(3)
+#define BOARD_DEBUG_UART_FRG_CLK \
+    (&(const clock_frg_clk_config_t){3, kCLOCK_FrgPllDiv, 255, 0}) /*!< Select FRG3 mux as frg_pll */
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRG_to_FLEXCOMM3
+#define BOARD_DEBUG_UART_RST        kFC3_RST_SHIFT_RSTn
+#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_Flexcomm3
+#define BOARD_UART_IRQ_HANDLER      FLEXCOMM3_IRQHandler
+#define BOARD_UART_IRQ              FLEXCOMM3_IRQn
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_FLEXSPI_PSRAM FLEXSPI
+#ifndef BOARD_ENABLE_PSRAM_CACHE
+#define BOARD_ENABLE_PSRAM_CACHE 1
+#endif
+
+/* Board I2C for codec */
+#define BOARD_CODEC_I2C_BASEADDR   I2C2
+#define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetFlexCommClkFreq(2U)
+#define BOARD_CODEC_I2C_INSTANCE   2
+#define BOARD_CODEC_I2C_SDA_PORT   0
+#define BOARD_CODEC_I2C_SCL_PORT   0
+#define BOARD_CODEC_I2C_SDA_PIN    16
+#define BOARD_CODEC_I2C_SCL_PIN    17
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  0U
+#define LOGIC_LED_OFF 1U
+
+/* A fake led on GPIO header */
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 0U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 0U
+#endif
+
+#define LED_BLUE_INIT(output)                                                            \
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */
+#define LED_BLUE_ON()                                           \
+    GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
+#define LED_BLUE_OFF()                                            \
+    GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                   1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
+#define LED_BLUE_TOGGLE()                                          \
+    GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                    1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
+
+/* Board SW PIN */
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#define BOARD_SW2_GPIO_PORT 0U
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 11U
+#endif
+
+#define BOARD_ENET0_PHY_ADDRESS (0x02U)
+
+/*! @brief The USIM SMARTCARD PHY configuration. */
+#define BOARD_SMARTCARD_MODULE                (USIM)      /*!< SMARTCARD communicational module instance */
+#define BOARD_SMARTCARD_MODULE_IRQ            (USIM_IRQn) /*!< SMARTCARD communicational module IRQ handler */
+#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetUsimClkFreq())
+#define BOARD_SMARTCARD_CLOCK_VALUE           (4000000U)  /*!< SMARTCARD clock frequency (4Mhz) */
+#define BOARD_SMARTCARD_IRQ_PORT              (0)
+#define BOARD_SMARTCARD_IRQ_PIN               (19)
+#define BOARD_SMARTCARD_TS_TIMER_IRQ          (CTIMER0_IRQn)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+status_t BOARD_InitPsRam(void);
+void BOARD_InitSleepPinConfig(void);
+void BOARD_ClockPreConfig(void);
+void BOARD_ClockPostConfig(void);
+AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider));
+AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitFlash(FLEXSPI_Type *base));
+AT_QUICKACCESS_SECTION_CODE(void BOARD_InitFlash(FLEXSPI_Type *base));
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.c

@@ -0,0 +1,277 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up all selectors to provide selected clocks.
+ *
+ * 3. Set up all dividers.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v14.0
+processor: RW612
+package_id: RW612ETA2I
+mcu_data: ksdk2_0
+processor_version: 0.16.9
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: audio_pll_clk.outFreq, value: 4246732800/345600007 MHz}
+- {id: aux0_pll_clk.outFreq, value: 260 MHz}
+- {id: avpll_ch1_clkout.outFreq, value: 4246732800/345600007 MHz}
+- {id: avpll_ch2_clkout.outFreq, value: 1415577600/22118401 MHz}
+- {id: cau_slp_clk.outFreq, value: 4 MHz}
+- {id: clk_32k.outFreq, value: 32 kHz}
+- {id: clk_pmu_sys.outFreq, value: 52 MHz}
+- {id: els_128m_clk.outFreq, value: 128 MHz}
+- {id: els_256m_clk.outFreq, value: 256 MHz}
+- {id: els_64m_clk.outFreq, value: 64 MHz}
+- {id: ffro_clk_div4.outFreq, value: 640/53 MHz}
+- {id: hclk.outFreq, value: 260 MHz}
+- {id: lposc_clk_i.outFreq, value: 1 MHz}
+- {id: main_clk.outFreq, value: 260 MHz}
+- {id: main_pll_clk.outFreq, value: 260 MHz}
+- {id: otp_fuse_32m_clk.outFreq, value: 32 MHz}
+- {id: refclk_phy.outFreq, value: 40 MHz}
+- {id: sfro_clk_i.outFreq, value: 16 MHz}
+- {id: systick_fclk.outFreq, value: 260 MHz}
+- {id: t3pll_mci_256m.outFreq, value: 256 MHz}
+- {id: t3pll_mci_48_60m_irc.outFreq, value: 2560/53 MHz}
+- {id: tcpu_mci_clk.outFreq, value: 260 MHz}
+- {id: tddr_mci_flexspi_clk.outFreq, value: 320 MHz}
+settings:
+- {id: CLKCTL0.MAINCLKSELB.sel, value: CLKCTL0.MAINPLLCLKDIV}
+- {id: CLKCTL0.MAINPLLCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL0.PMUFCLKDIV.scale, value: '5', locked: true}
+- {id: CLKCTL0.SYSCPUAHBCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL0.SYSTICKFCLKSEL.sel, value: CLKCTL0.SYSTICKFCLKDIV}
+- {id: CLKCTL0.WDT0FCLKSEL.sel, value: NO_CLOCK}
+- {id: CLKCTL1.FRGPLLCLKDIV.scale, value: '13', locked: true}
+- {id: CLKCTL1.OSEVENTFCLKSEL.sel, value: NO_CLOCK}
+- {id: REFCLK_SYS_Config, value: Disabled}
+- {id: SYSCTL2.CH1_M.scale, value: '2621440', locked: true}
+- {id: SYSCTL2.CH1_OFFSET_DIV.scale, value: '345600007', locked: true}
+- {id: SYSCTL2.CH2_M.scale, value: '2621440', locked: true}
+- {id: SYSCTL2.CH2_OFFSET_DIV.scale, value: '66355203', locked: true}
+- {id: SYSCTL2.T3_FBDIV.scale, value: '64', locked: true}
+- {id: SYSCTL2.T3_REFDIV.scale, value: '1', locked: true}
+- {id: T3PLL_MCI_213P3M_Config, value: Disabled}
+- {id: T3PLL_MCI_FLEXSPI_Config, value: Disabled}
+- {id: TCPU_MCI_FLEXSPI_CLK_Config, value: Disabled}
+- {id: TDDR_MCI_ENET_CLK_Config, value: Disabled}
+sources:
+- {id: CAU.XTAL_OSC.outFreq, value: 40 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN =
+    {
+        .ch1Freq = kCLOCK_AvPllChFreq12p288m,     /* AVPLL channel frequency 12.288 MHz */
+        .ch2Freq = kCLOCK_AvPllChFreq64m,         /* AVPLL channel frequency 64 MHz */
+        .enableCali = true,                       /* AVPLL calibration is enabled */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Disable GDET and VSensors */
+    POWER_DisableGDetVSensors();
+    /* Enable CAU sleep clock for PMU */
+    if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U)
+    {
+        /* Enable the CAU sleep clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkCauSlp);
+    }
+    if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U)
+    {
+        /* Enable the REFCLK_SYS clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkSys);
+    }
+    /* Initialize T3 PLL and enable outputs that are not clock gated. */
+    CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m);
+    /* Enable FFRO - T3 PLL 48/60 MHz IRC clock output */
+    CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk);
+    /* Enable T3 PLL 256 MHz clock output */
+    CLOCK_EnableClock(kCLOCK_T3PllMci256mClk);
+    BOARD_ClockPreConfig();
+    /* Set core clock to safe system oscillator clock for initialization of other sources. */
+    CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK);
+    CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);
+    /* Initialize TCPU PLL and enable outputs that are not clock gated. */
+    CLOCK_InitTcpuRefClk(3120000000UL, kCLOCK_TcpuFlexspiDiv10);
+    /* Enable TCPU PLL MCI clock output */
+    CLOCK_EnableClock(kCLOCK_TcpuMciClk);
+    /* Initialize TDDR PLL and enable outputs that are not clock gated. */
+    CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10);
+    /* Enable TDDR PLL FlexSPI clock output */
+    CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk);
+    /* Initialize AVPLL and enable both channels. */
+    CLOCK_InitAvPll(&avpllConfig_BOARD_BootClockRUN);
+    /* Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kRC32K_to_CLK32K);                 /* Switch CLK32K to RC32K */
+    /*!< Please note SYSTICK_CLK source is used only if the SysTick SYST_CSR register CLKSOURCE bit is set to 0. */
+    CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK);                 /* Switch SYSTICK_CLK to SYSTICK_DIV */
+    /* Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U);         /* Set .AUDIOPLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);         /* Set .FRGPLLCLKDIV divider to value 13 */
+    CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);         /* Set .MAINPLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);         /* Set .AUX0PLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);         /* Set .SYSTICKFCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U);         /* Set .PMUFCLKDIV divider to value 5 */
+    /* Select the main clock source for the main system clock (MAINCLKSELA and MAINCLKSELB). */
+    CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
+    BOARD_ClockPostConfig();
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_HCLK;
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockLPR
+outputs:
+- {id: aux0_pll_clk.outFreq, value: 260 MHz}
+- {id: clk_32k.outFreq, value: 32 kHz}
+- {id: clk_pmu_sys.outFreq, value: 52 MHz}
+- {id: els_128m_clk.outFreq, value: 128 MHz}
+- {id: els_256m_clk.outFreq, value: 256 MHz}
+- {id: els_64m_clk.outFreq, value: 64 MHz}
+- {id: hclk.outFreq, value: 260 MHz}
+- {id: main_clk.outFreq, value: 260 MHz}
+- {id: main_pll_clk.outFreq, value: 260 MHz}
+- {id: otp_fuse_32m_clk.outFreq, value: 32 MHz}
+- {id: refclk_phy.outFreq, value: 40 MHz}
+- {id: refclk_sys.outFreq, value: 40 MHz}
+- {id: sfro_clk_i.outFreq, value: 16 MHz}
+- {id: systick_fclk.outFreq, value: 260 MHz}
+- {id: t3pll_mci_256m.outFreq, value: 256 MHz}
+- {id: tcpu_mci_clk.outFreq, value: 260 MHz}
+settings:
+- {id: AVPLL_Init_Config, value: Disabled}
+- {id: CAU_SLP_CLK_Config, value: Disabled}
+- {id: CLKCTL0.MAINCLKSELB.sel, value: CLKCTL0.MAINPLLCLKDIV}
+- {id: CLKCTL0.MAINPLLCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL0.SYSOSCBYPASS_SEL.sel, value: NO_CLOCK}
+- {id: CLKCTL0.SYSTICKFCLKSEL.sel, value: CLKCTL0.SYSTICKFCLKDIV}
+- {id: CLKCTL1.CLKOUTSEL1.sel, value: CLKCTL1.CLKOUTSEL0}
+- {id: CLKCTL1.CLKOUTSEL2.sel, value: CLKCTL1.CLKOUTSEL1}
+- {id: CLKCTL1.FRGPLLCLKDIV.scale, value: '13', locked: true}
+- {id: SYSCTL2.T3_FBDIV.scale, value: '64'}
+- {id: SYSCTL2.TCPU_FBDIV.scale, value: '78', locked: true}
+- {id: SYSCTL2.TCPU_MCI_FLEXSPI_CLK_DIV.scale, value: '10', locked: true}
+- {id: SYSCTL2.TCPU_REFDIV.scale, value: '1', locked: true}
+- {id: T3PLL_MCI_213P3M_Config, value: Disabled}
+- {id: T3PLL_MCI_48_60M_IRC_Config, value: Disabled}
+- {id: T3PLL_MCI_FLEXSPI_Config, value: Disabled}
+- {id: TCPU_MCI_FLEXSPI_CLK_Config, value: Disabled}
+- {id: TDDR_MCI_ENET_CLK_Config, value: Disabled}
+- {id: TDDR_MCI_FLEXSPI_CLK_Config, value: Disabled}
+- {id: TDDR_PLL_Init_Config, value: Disabled}
+sources:
+- {id: CAU.XTAL_OSC.outFreq, value: 40 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockLPR(void)
+{
+    /* Disable GDET and VSensors */
+    POWER_DisableGDetVSensors();
+    /* Enable CAU sleep clock for PMU */
+    if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U)
+    {
+        /* Enable the CAU sleep clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkCauSlp);
+    }
+    if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U)
+    {
+        /* Enable the REFCLK_SYS clock. */
+        CLOCK_EnableClock(kCLOCK_RefClkSys);
+    }
+    /* Initialize T3 PLL and enable outputs that are not clock gated. */
+    CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m);
+    /* Enable T3 PLL 256 MHz clock output */
+    CLOCK_EnableClock(kCLOCK_T3PllMci256mClk);
+    BOARD_ClockPreConfig();
+    /* Set core clock to safe system oscillator clock for initialization of other sources. */
+    CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK);
+    CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);
+    /* Initialize TCPU PLL and enable outputs that are not clock gated. */
+    CLOCK_InitTcpuRefClk(3120000000UL, kCLOCK_TcpuFlexspiDiv10);
+    /* Enable TCPU PLL MCI clock output */
+    CLOCK_EnableClock(kCLOCK_TcpuMciClk);
+    /* Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kRC32K_to_CLK32K);                 /* Switch CLK32K to RC32K */
+    /*!< Please note SYSTICK_CLK source is used only if the SysTick SYST_CSR register CLKSOURCE bit is set to 0. */
+    CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK);                 /* Switch SYSTICK_CLK to SYSTICK_DIV */
+    /* Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);         /* Set .FRGPLLCLKDIV divider to value 13 */
+    CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);         /* Set .MAINPLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);         /* Set .AUX0PLLCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);         /* Set .SYSTICKFCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U);         /* Set .PMUFCLKDIV divider to value 5 */
+    /* Select the main clock source for the main system clock (MAINCLKSELA and MAINCLKSELB). */
+    CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
+    /* Deinitialization of the AVPLL. */
+    CLOCK_DeinitAvPll();
+    /* Deinitialize TDDR PLL. */
+    CLOCK_DeinitTddrRefClk();
+    BOARD_ClockPostConfig();
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKLPR_HCLK;
+}
+

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/clock_config.h

@@ -0,0 +1,198 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AUDIO_PLL_CLK              12287999UL     /* Clock consumers of audio_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_AUX0_PLL_CLK               260000000UL    /* Clock consumers of aux0_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_AUX1_PLL_CLK               0UL            /* Clock consumers of aux1_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_AVPLL_CH1_CLKOUT           12287999UL     /* Clock consumers of avpll_ch1_clkout output : N/A */
+#define BOARD_BOOTCLOCKRUN_AVPLL_CH2_CLKOUT           63999997UL     /* Clock consumers of avpll_ch2_clkout output : N/A */
+#define BOARD_BOOTCLOCKRUN_CAU_SLP_CLK                4000000UL      /* Clock consumers of cau_slp_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_32K                    32000UL        /* Clock consumers of clk_32k output : RTC */
+#define BOARD_BOOTCLOCKRUN_CLK_OUT                    0UL            /* Clock consumers of clk_out output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_PMU_SYS                52000000UL     /* Clock consumers of clk_pmu_sys output : PMU */
+#define BOARD_BOOTCLOCKRUN_CTIMER0_FCLK               0UL            /* Clock consumers of ctimer0_fclk output : CTIMER0 */
+#define BOARD_BOOTCLOCKRUN_CTIMER1_FCLK               0UL            /* Clock consumers of ctimer1_fclk output : CTIMER1 */
+#define BOARD_BOOTCLOCKRUN_CTIMER2_FCLK               0UL            /* Clock consumers of ctimer2_fclk output : CTIMER2 */
+#define BOARD_BOOTCLOCKRUN_CTIMER3_FCLK               0UL            /* Clock consumers of ctimer3_fclk output : CTIMER3 */
+#define BOARD_BOOTCLOCKRUN_DMIC_FCLK                  0UL            /* Clock consumers of dmic_fclk output : DMIC0 */
+#define BOARD_BOOTCLOCKRUN_ELS_128M_CLK               128000000UL    /* Clock consumers of els_128m_clk output : ELS */
+#define BOARD_BOOTCLOCKRUN_ELS_256M_CLK               256000000UL    /* Clock consumers of els_256m_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_ELS_64M_CLK                64000000UL     /* Clock consumers of els_64m_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_ELS_FCLK                   0UL            /* Clock consumers of els_fclk output : ELS */
+#define BOARD_BOOTCLOCKRUN_FFRO_CLK_DIV4              12075471UL     /* Clock consumers of ffro_clk_div4 output : N/A */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM0_FCLK             0UL            /* Clock consumers of flexcomm0_fclk output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM14_FCLK            0UL            /* Clock consumers of flexcomm14_fclk output : FLEXCOMM14 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM1_FCLK             0UL            /* Clock consumers of flexcomm1_fclk output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM2_FCLK             0UL            /* Clock consumers of flexcomm2_fclk output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM3_FCLK             0UL            /* Clock consumers of flexcomm3_fclk output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_FCLK               0UL            /* Clock consumers of flexspi_fclk output : FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_GAU_FCLK                   0UL            /* Clock consumers of gau_fclk output : GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1 */
+#define BOARD_BOOTCLOCKRUN_HCLK                       260000000UL    /* Clock consumers of hclk output : AHB_SECURE_CTRL, APU0, APU1, BLEAPU, BLECTRL, BUCK11, BUCK18, CACHE64_CTRL0, CACHE64_CTRL1, CACHE64_POLSEL0, CACHE64_POLSEL1, CAU, CDOG, CLKCTL0, CLKCTL1, CRC, CTIMER0, CTIMER1, CTIMER2, CTIMER3, DMA0, DMA1, DMIC0, ELS, ENET, FLEXCOMM0, FLEXCOMM1, FLEXCOMM14, FLEXCOMM2, FLEXCOMM3, FLEXSPI, FREQME, GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1, GDMA, GPIO, INPUTMUX, ITRC, LCDIC, MCI_IO_MUX, MRT0, MRT1, OCOTP, OSTIMER, PINT, PKC, PMU, POWERQUAD, PUF, ROMCP, RSTCTL0, RSTCTL1, RTC, SCT0, SDU_FBR_CARD, SDU_FN0_CARD, SDU_FN_CARD, SECGPIO, SENSOR_CTRL, SOCCTRL, SOC_OTP_CTRL, SYSCTL0, SYSCTL1, SYSCTL2, SysTick, TRNG, USBOTG, USIM, UTICK, WLAPU, WLCTRL, WWDT0 */
+#define BOARD_BOOTCLOCKRUN_LCD_FCLK                   0UL            /* Clock consumers of lcd_fclk output : LCDIC */
+#define BOARD_BOOTCLOCKRUN_LPOSC_CLK_I                1000000UL      /* Clock consumers of lposc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKRUN_MAIN_CLK                   260000000UL    /* Clock consumers of main_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_MAIN_PLL_CLK               260000000UL    /* Clock consumers of main_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_MCLK_OUT                   0UL            /* Clock consumers of mclk_out output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSEVENT_FCLK               0UL            /* Clock consumers of osevent_fclk output : OSTIMER */
+#define BOARD_BOOTCLOCKRUN_OTP_FUSE_32M_CLK           32000000UL     /* Clock consumers of otp_fuse_32m_clk output : OCOTP */
+#define BOARD_BOOTCLOCKRUN_REFCLK_PHY                 40000000UL     /* Clock consumers of refclk_phy output : USBOTG */
+#define BOARD_BOOTCLOCKRUN_REFCLK_SYS                 0UL            /* Clock consumers of refclk_sys output : N/A */
+#define BOARD_BOOTCLOCKRUN_SCT_FCLK                   0UL            /* Clock consumers of sct_fclk output : SCT0 */
+#define BOARD_BOOTCLOCKRUN_SFRO_CLK_I                 16000000UL     /* Clock consumers of sfro_clk_i output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYSOSC_CLK_I               0UL            /* Clock consumers of sysosc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYSTICK_FCLK               260000000UL    /* Clock consumers of systick_fclk output : SysTick */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_213P3M           0UL            /* Clock consumers of t3pll_mci_213p3m output : N/A */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_256M             256000000UL    /* Clock consumers of t3pll_mci_256m output : N/A */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_48_60M_IRC       48301886UL     /* Clock consumers of t3pll_mci_48_60m_irc output : N/A */
+#define BOARD_BOOTCLOCKRUN_T3PLL_MCI_FLEXSPI_CLK      0UL            /* Clock consumers of t3pll_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_TCPU_MCI_CLK               260000000UL    /* Clock consumers of tcpu_mci_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_TCPU_MCI_FLEXSPI_CLK       0UL            /* Clock consumers of tcpu_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_TDDR_MCI_ENET_CLK          0UL            /* Clock consumers of tddr_mci_enet_clk output : ENET */
+#define BOARD_BOOTCLOCKRUN_TDDR_MCI_FLEXSPI_CLK       320000000UL    /* Clock consumers of tddr_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKRUN_USIM_FCLK                  0UL            /* Clock consumers of usim_fclk output : USIM */
+#define BOARD_BOOTCLOCKRUN_UTICK_FCLK                 0UL            /* Clock consumers of utick_fclk output : UTICK */
+#define BOARD_BOOTCLOCKRUN_WDT0_FCLK                  0UL            /* Clock consumers of wdt0_fclk output : WWDT0 */
+
+/*! @brief AVPLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN;
+/*! @brief Clock pre-initialization function.
+ */
+extern void BOARD_ClockPreConfig(void);
+/*! @brief Clock post-initialization function.
+ */
+extern void BOARD_ClockPostConfig(void);
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKLPR_AUDIO_PLL_CLK              0UL            /* Clock consumers of audio_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_AUX0_PLL_CLK               260000000UL    /* Clock consumers of aux0_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_AUX1_PLL_CLK               0UL            /* Clock consumers of aux1_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_AVPLL_CH1_CLKOUT           0UL            /* Clock consumers of avpll_ch1_clkout output : N/A */
+#define BOARD_BOOTCLOCKLPR_AVPLL_CH2_CLKOUT           0UL            /* Clock consumers of avpll_ch2_clkout output : N/A */
+#define BOARD_BOOTCLOCKLPR_CAU_SLP_CLK                0UL            /* Clock consumers of cau_slp_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_CLK_32K                    32000UL        /* Clock consumers of clk_32k output : RTC */
+#define BOARD_BOOTCLOCKLPR_CLK_OUT                    0UL            /* Clock consumers of clk_out output : N/A */
+#define BOARD_BOOTCLOCKLPR_CLK_PMU_SYS                52000000UL     /* Clock consumers of clk_pmu_sys output : PMU */
+#define BOARD_BOOTCLOCKLPR_CTIMER0_FCLK               0UL            /* Clock consumers of ctimer0_fclk output : CTIMER0 */
+#define BOARD_BOOTCLOCKLPR_CTIMER1_FCLK               0UL            /* Clock consumers of ctimer1_fclk output : CTIMER1 */
+#define BOARD_BOOTCLOCKLPR_CTIMER2_FCLK               0UL            /* Clock consumers of ctimer2_fclk output : CTIMER2 */
+#define BOARD_BOOTCLOCKLPR_CTIMER3_FCLK               0UL            /* Clock consumers of ctimer3_fclk output : CTIMER3 */
+#define BOARD_BOOTCLOCKLPR_DMIC_FCLK                  0UL            /* Clock consumers of dmic_fclk output : DMIC0 */
+#define BOARD_BOOTCLOCKLPR_ELS_128M_CLK               128000000UL    /* Clock consumers of els_128m_clk output : ELS */
+#define BOARD_BOOTCLOCKLPR_ELS_256M_CLK               256000000UL    /* Clock consumers of els_256m_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_ELS_64M_CLK                64000000UL     /* Clock consumers of els_64m_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_ELS_FCLK                   0UL            /* Clock consumers of els_fclk output : ELS */
+#define BOARD_BOOTCLOCKLPR_FFRO_CLK_DIV4              0UL            /* Clock consumers of ffro_clk_div4 output : N/A */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM0_FCLK             0UL            /* Clock consumers of flexcomm0_fclk output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM14_FCLK            0UL            /* Clock consumers of flexcomm14_fclk output : FLEXCOMM14 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM1_FCLK             0UL            /* Clock consumers of flexcomm1_fclk output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM2_FCLK             0UL            /* Clock consumers of flexcomm2_fclk output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKLPR_FLEXCOMM3_FCLK             0UL            /* Clock consumers of flexcomm3_fclk output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKLPR_FLEXSPI_FCLK               0UL            /* Clock consumers of flexspi_fclk output : FLEXSPI */
+#define BOARD_BOOTCLOCKLPR_GAU_FCLK                   0UL            /* Clock consumers of gau_fclk output : GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1 */
+#define BOARD_BOOTCLOCKLPR_HCLK                       260000000UL    /* Clock consumers of hclk output : AHB_SECURE_CTRL, APU0, APU1, BLEAPU, BLECTRL, BUCK11, BUCK18, CACHE64_CTRL0, CACHE64_CTRL1, CACHE64_POLSEL0, CACHE64_POLSEL1, CAU, CDOG, CLKCTL0, CLKCTL1, CRC, CTIMER0, CTIMER1, CTIMER2, CTIMER3, DMA0, DMA1, DMIC0, ELS, ENET, FLEXCOMM0, FLEXCOMM1, FLEXCOMM14, FLEXCOMM2, FLEXCOMM3, FLEXSPI, FREQME, GAU_ACOMP, GAU_BG, GAU_DAC0, GAU_GPADC0, GAU_GPADC1, GDMA, GPIO, INPUTMUX, ITRC, LCDIC, MCI_IO_MUX, MRT0, MRT1, OCOTP, OSTIMER, PINT, PKC, PMU, POWERQUAD, PUF, ROMCP, RSTCTL0, RSTCTL1, RTC, SCT0, SDU_FBR_CARD, SDU_FN0_CARD, SDU_FN_CARD, SECGPIO, SENSOR_CTRL, SOCCTRL, SOC_OTP_CTRL, SYSCTL0, SYSCTL1, SYSCTL2, SysTick, TRNG, USBOTG, USIM, UTICK, WLAPU, WLCTRL, WWDT0 */
+#define BOARD_BOOTCLOCKLPR_LCD_FCLK                   0UL            /* Clock consumers of lcd_fclk output : LCDIC */
+#define BOARD_BOOTCLOCKLPR_LPOSC_CLK_I                0UL            /* Clock consumers of lposc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKLPR_MAIN_CLK                   260000000UL    /* Clock consumers of main_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_MAIN_PLL_CLK               260000000UL    /* Clock consumers of main_pll_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_MCLK_OUT                   0UL            /* Clock consumers of mclk_out output : N/A */
+#define BOARD_BOOTCLOCKLPR_OSEVENT_FCLK               0UL            /* Clock consumers of osevent_fclk output : OSTIMER */
+#define BOARD_BOOTCLOCKLPR_OTP_FUSE_32M_CLK           32000000UL     /* Clock consumers of otp_fuse_32m_clk output : OCOTP */
+#define BOARD_BOOTCLOCKLPR_REFCLK_PHY                 40000000UL     /* Clock consumers of refclk_phy output : USBOTG */
+#define BOARD_BOOTCLOCKLPR_REFCLK_SYS                 40000000UL     /* Clock consumers of refclk_sys output : N/A */
+#define BOARD_BOOTCLOCKLPR_SCT_FCLK                   0UL            /* Clock consumers of sct_fclk output : SCT0 */
+#define BOARD_BOOTCLOCKLPR_SFRO_CLK_I                 16000000UL     /* Clock consumers of sfro_clk_i output : N/A */
+#define BOARD_BOOTCLOCKLPR_SYSOSC_CLK_I               0UL            /* Clock consumers of sysosc_clk_i output : N/A */
+#define BOARD_BOOTCLOCKLPR_SYSTICK_FCLK               260000000UL    /* Clock consumers of systick_fclk output : SysTick */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_213P3M           0UL            /* Clock consumers of t3pll_mci_213p3m output : N/A */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_256M             256000000UL    /* Clock consumers of t3pll_mci_256m output : N/A */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_48_60M_IRC       0UL            /* Clock consumers of t3pll_mci_48_60m_irc output : N/A */
+#define BOARD_BOOTCLOCKLPR_T3PLL_MCI_FLEXSPI_CLK      0UL            /* Clock consumers of t3pll_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_TCPU_MCI_CLK               260000000UL    /* Clock consumers of tcpu_mci_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_TCPU_MCI_FLEXSPI_CLK       0UL            /* Clock consumers of tcpu_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_TDDR_MCI_ENET_CLK          0UL            /* Clock consumers of tddr_mci_enet_clk output : ENET */
+#define BOARD_BOOTCLOCKLPR_TDDR_MCI_FLEXSPI_CLK       0UL            /* Clock consumers of tddr_mci_flexspi_clk output : N/A */
+#define BOARD_BOOTCLOCKLPR_USIM_FCLK                  0UL            /* Clock consumers of usim_fclk output : USIM */
+#define BOARD_BOOTCLOCKLPR_UTICK_FCLK                 0UL            /* Clock consumers of utick_fclk output : UTICK */
+#define BOARD_BOOTCLOCKLPR_WDT0_FCLK                  0UL            /* Clock consumers of wdt0_fclk output : WWDT0 */
+
+/*******************************************************************************
+ * API for BOARD_BootClockLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2021 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "pin_mux.h"
+#include "fsl_io_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {                                /*!< Function assigned for the core: Cortex-M33[cm33] */
+    IO_MUX_SetPinMux(IO_MUX_FC3_USART_DATA);
+    IO_MUX_SetPinMux(IO_MUX_GPIO11);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/board/pin_mux.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright 2021 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);                                 /*!< Function assigned for the core: Cortex-M4[cm4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/fsl_loader.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2020-2021,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef TFM_PARTITION_LOADER_SERVICE
+#include "fsl_loader_utils.h"
+
+//! @addtogroup sbloader
+//! @{
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+////////////////////////////////////////////////////////////////////////////
+//! @brief fw download
+////////////////////////////////////////////////////////////////////////////
+status_t sb3_fw_download(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr)
+{
+    return sb3_fw_download_impl(loadTarget,flag,sourceAddr);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief fw reset
+////////////////////////////////////////////////////////////////////////////
+status_t sb3_fw_reset(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr)
+{
+    return sb3_fw_reset_impl(loadTarget, flag, sourceAddr);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief power on device
+////////////////////////////////////////////////////////////////////////////
+void power_on_device(LOAD_Target_Type loadTarget)
+{
+    power_on_device_impl(loadTarget);
+}
+
+////////////////////////////////////////////////////////////////////////////
+//! @brief power off device
+////////////////////////////////////////////////////////////////////////////
+void power_off_device(LOAD_Target_Type loadTarget)
+{
+    power_off_device_impl(loadTarget);
+}
+//! @}
+////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////
+#endif /* TFM_PARTITION_LOADER_SERVICE */

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/api_tree_root.h

@@ -0,0 +1,166 @@
+/*
+ * Copyright 2016-2019, 2021,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef __API_TREE_ROOT_H__
+#define __API_TREE_ROOT_H__
+
+#include "fsl_loader_utils.h"
+#include "nboot_rom_api_table.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+// Load and set user appplication boot options stored in specific register
+#define LOAD_USER_APP_BOOT_OPTIONS()        (SYSCON_USER_APP_BOOT_OPTIONS)
+#define CLEAR_USER_APP_BOOT_OPTIONS()       (SYSCON_USER_APP_BOOT_OPTIONS = 0u)
+#define SET_USER_APP_BOOT_OPTIONS(value)    (SYSCON_USER_APP_BOOT_OPTIONS = value)
+
+//! @brief Boot parameters of the user application
+//!  WORD    OFFSET      FIELD                              DESCRIPTION
+//!          [31:24]     TAG                                Must be '0xEB'
+//!          [23:20]     Boot mode                          0:Master boot mode; 1: ISP boot
+//!          [19:16]     Boot interface                     0:USART 1:I2C 2:SPI 3:USB HID 4:QSPI 5:USB DFU
+//!          [15:12]     Boot instance(Channel)             0 or 1; For SD or MMC,this is to select the instance
+//!                                                         For FLEXSPI boot, this select the Channel A or Channel B
+//!          [11:08]     Redundant boot image index         Redundant boot image index for FlexSPI NOR flash
+//!          [07:00]     Reserved
+//!
+//!  TAG[31:24]	    BOOT MODE[23:20]    INTERFACE[19:16]    INSTANCE[15:12]     RBII    Reserved[07:00]     COMBINATION     BOOT ACTION
+//!  0xEB  	        0                   0	                X	                X       X	                0xEB00XXXX	    MASTR BOOT: USART
+//!	                0	                1	                X	                X       X	                0xEB01XXXX	    MASTR BOOT: I2C
+//!	                0	                2	                X	                X       X	                0xEB02XXXX	    MASTR BOOT: SPI
+//!	                0	                3	                X	                X       X	                0xEB03XXXX	    MASTR BOOT: USB HID
+//!	                0	                4	                X	                0       X	                0xEB0400XX	    MASTR BOOT: FlexSPI Channel A:boot image index 0
+//!	                0	                4	                X	                1       X	                0xEB0401XX	    MASTR BOOT: FlexSPI Channel A:boot image index 1
+//!	                0                   4	                X	                0       X	                0xEB0410XX	    MASTR BOOT: FlexSPI Channel B:boot image index 0
+//!	                0	                4	                X	                1       X	                0xEB0411XX	    MASTR BOOT: FlexSPI Channel B:boot image index 1
+//!	                0	                5	                X	                X       X	                0xEB05XXXX	    MASTR BOOT: USB DFU
+//!	                1	                0	                X	                X       X	                0xEB10XXXX	    ISP BOOT: USART
+//!	                1	                1	                X	                X       X	                0xEB11XXXX	    ISP BOOT: I2C
+//!	                1	                2	                X	                X       X	                0xEB12XXXX	    ISP BOOT: SPI
+//!
+
+typedef struct _fsl_user_app_boot_invoke_option
+{
+    union
+    {
+        struct
+        {
+            uint32_t reserved           : 8;
+            uint32_t boot_image_index   : 4;
+            uint32_t instance           : 4;
+            uint32_t boot_interface     : 4;
+            uint32_t mode               : 4;
+            uint32_t tag                : 8;
+        } B;
+        uint32_t U;
+    } option;
+} fsl_user_app_boot_invoke_option_t;
+
+//! @brief Boot interface can be selected by user application
+//! @note  For USB-HID QSPI USB-DFU SD MMC, these interfaces are invalid for ISP boot
+enum
+{
+    kUserAppBootPeripheral_UART     = 0u,
+    kUserAppBootPeripheral_I2C      = 1u,
+    kUserAppBootPeripheral_SPI      = 2u,
+    kUserAppBootPeripheral_USB_HID  = 3u,
+    kUserAppBootPeripheral_FLEXSPI  = 4u,
+    kUserAppBootPeripheral_DFU      = 5u
+};
+
+//! @brief Boot mode can be selected by user application
+//! @note  For master boot, valid boot insterfaces for user application are USART I2C SPI USB-HID USB-DFU SD MMC
+//!        For ISP boot, valid boot interfaces for user application are USART I2C SPI
+enum
+{
+    kUserAppBootMode_MasterBoot = 0,
+    kUserAppBootMode_IspBoot    = 1,
+};
+
+
+//!@brief OTP driver API Interface for A0
+typedef struct
+{
+    uint32_t version;
+    status_t (*init)(uint32_t src_clk_freq);
+    status_t (*deinit)(void);
+    status_t (*fuse_read)(uint32_t addr, uint32_t *data);
+    status_t (*fuse_program)(uint32_t addr, uint32_t data, bool lock);
+    status_t (*reload)(void);
+    status_t (*crc_check)(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
+    status_t (*crc_calc)(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
+    status_t (*crc_check_sw)(uint32_t *src, uint32_t numberOfWords, uint32_t crc_fuse_idx);
+} ocotp_driver_v0_t;
+
+//!@brief OTP driver API Interface for A1/A2
+typedef struct
+{
+    uint32_t version;
+    status_t (*init)(uint32_t src_clk_freq);
+    status_t (*deinit)(void);
+    status_t (*fuse_read)(uint32_t addr, uint32_t *data, uint32_t argChk);
+    status_t (*fuse_program)(uint32_t addr, uint32_t data, bool lock);
+    status_t (*reload)(void);
+    status_t (*crc_check)(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
+    status_t (*crc_calc)(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
+    status_t (*crc_check_sw)(uint32_t *src, uint32_t numberOfWords, uint32_t crc_fuse_idx);
+} ocotp_driver_v1_t;
+
+//! @brief Root of the bootloader API tree for A0.
+//!
+//! An instance of this struct resides in read-only memory in the bootloader. It
+//! provides a user application access to APIs exported by the bootloader.
+//!
+//! @note The order of existing fields must not be changed.
+//!
+//! @ingroup context
+typedef struct BootloaderTree_v0
+{
+    void (*runBootloader)(void *arg);                               //!< Function to start the bootloader executing.
+    fsl_standard_version_t                      version;                //!< Bootloader version number.
+    const char                              *copyright;             //!< Copyright string.
+    const uint32_t                          reservedBootloader2;
+    const nboot_interface_v0_t              *nbootDriver;           //!< Image authentication API.
+    const uint32_t                          reservedBootloader3;
+    const ocotp_driver_v0_t                 *otpDriver;             //!< OTP driver API.
+    const fsl_iap_api_interface_t               *iapApiDriver;
+} bootloader_tree_v0_t;
+
+//! @brief Root of the bootloader API tree for A1/A2.
+//!
+//! An instance of this struct resides in read-only memory in the bootloader. It
+//! provides a user application access to APIs exported by the bootloader.
+//!
+//! @note The order of existing fields must not be changed.
+//!
+//! @ingroup context
+typedef struct BootloaderTree_v1
+{
+    void (*runBootloader)(void *arg);                               //!< Function to start the bootloader executing.
+    fsl_standard_version_t                      version;                //!< Bootloader version number.
+    const char                              *copyright;             //!< Copyright string.
+    const uint32_t                          reservedBootloader2;
+    const nboot_interface_v1_t              *nbootDriver;           //!< Image authentication API.
+    const uint32_t                          reservedBootloader3;
+    const ocotp_driver_v1_t                 *otpDriver;             //!< OTP driver API.
+    const fsl_iap_api_interface_t               *iapApiDriver;
+} bootloader_tree_v1_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // __API_TREE_ROOT_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2016, 2022,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_LOADER_H__
+#define __FSL_LOADER_H__
+
+#include <stdint.h>
+#include "fsl_common.h"
+
+typedef enum
+{
+    LOAD_WIFI_FIRMWARE = 1,
+    LOAD_BLE_FIRMWARE,
+    LOAD_15D4_FIRMWARE,
+#ifdef CONFIG_FW_VDLLV2
+    LOAD_WIFI_VDLL_FIRMWARE,
+#endif
+    LOAD_WIFI_FW_MONOLITHIC = 0x81,
+    LOAD_BLE_FW_MONOLITHIC  = 0x82,
+    LOAD_15D4_FW_MONOLITHIC = 0x83,
+    LOAD_TYPE_MAX,
+} LOAD_Target_Type;
+
+void power_on_device(LOAD_Target_Type loadTarget);
+void power_off_device(LOAD_Target_Type loadTarget);
+
+status_t sb3_fw_download(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+status_t sb3_fw_reset(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+
+//! @}
+
+#endif

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/fsl_loader_utils.h

@@ -0,0 +1,670 @@
+/*
+ * Copyright 2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_LOADER_UTILS_H__
+#define __FSL_LOADER_UTILS_H__
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_loader.h"
+#include "fusemap.h"
+#include "fsl_ocotp.h"
+#include "fsl_os_abstraction.h"
+
+//! @addtogroup sbloader
+//! @{
+/*! @brief Status group numbers. */
+#define kStatusGroup_SBLoader                  (101U)
+#define NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES  (48u)
+#define NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES (48u)
+#define NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES  (48u)
+#define NBOOT_EC_COORDINATE_MAX_SIZE           NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES
+#define NBOOT_ROOT_CERT_COUNT                  (4u)
+#define NBOOT_SB3_CHUNK_SIZE_IN_BYTES          (256u)
+#define NBOOT_KEYINFO_WORDLEN                  (23u)
+#define NXPCLHASH_WA_SIZE_MAX                  (128u + 64u)
+#define NBOOT_CONTEXT_BYTELEN                  (192u + NXPCLHASH_WA_SIZE_MAX)
+#define NBOOT_CONTEXT_WORDLEN                  (NBOOT_CONTEXT_BYTELEN / sizeof(uint32_t))
+#define NXPCLCSS_HASH_RTF_OUTPUT_SIZE          ((size_t)32U)
+
+#define SECURE_TERM_PART_LOCK        (0x6ac3c36au)
+#define SECURE_TERM_PART_OPEN        (0xc36ac36au)
+#define SECURE_TERM_SECURE_PART_OPEN (0xc36a6ac3u)
+#define SECURE_TERM_FA_PART_OPEN     (0xc3c36a6au)
+#define SECURE_OEM_FA_PART_OPEN      (0xc3c3a6a6u)
+
+#define LOADER_RAW_BINARY_FORMAT      (0x72617762U)
+#ifdef CONFIG_FW_VDLLV2
+#define LOADER_VDLL_RAW_BINARY_FORMAT (0x76646c6cU)
+#endif
+
+/*! @brief partition table constants. */
+#define WIFI_IMAGE_SIZE_MAX (0xa0000U)
+#define BLE_IMAGE_SIZE_MAX  (0x50000U)
+#define Z154_IMAGE_SIZE_MAX (0x50000U)
+#ifndef WIFI_IMAGE_A_OFFSET
+#define WIFI_IMAGE_A_OFFSET (0x08400000U)
+#endif
+#define WIFI_IMAGE_B_OFFSET (WIFI_IMAGE_A_OFFSET + WIFI_IMAGE_SIZE_MAX) // 0x4a0000
+#define BLE_IMAGE_A_OFFSET  (WIFI_IMAGE_B_OFFSET + WIFI_IMAGE_SIZE_MAX) // 0x540000
+#define BLE_IMAGE_B_OFFSET  (BLE_IMAGE_A_OFFSET + BLE_IMAGE_SIZE_MAX)   // 0x590000
+#define Z154_IMAGE_A_OFFSET (BLE_IMAGE_B_OFFSET + BLE_IMAGE_SIZE_MAX)   // 0x5e0000
+#define Z154_IMAGE_B_OFFSET (Z154_IMAGE_A_OFFSET + Z154_IMAGE_SIZE_MAX) // 0x630000
+
+/** Type for nboot status codes */
+typedef uint32_t fsl_nboot_status_t;
+
+/**
+ * \defgroup nbootStatusValues  This type defines status return values used by NBOOT functions that are not easily
+ * disturbed by Fault Attacks
+ * @{
+ */
+#define kStatus_NBOOT_Success                ((fsl_nboot_status_t)0x5A5A5A5Au) /*!< Operation completed successfully. */
+#define kStatus_NBOOT_Fail                   ((fsl_nboot_status_t)0x5A5AA5A5u) /*!< Operation failed. */
+#define kStatus_NBOOT_InvalidArgument        ((fsl_nboot_status_t)0x5A5AA5F0u) /*!< Invalid argument passed to the function. */
+#define kStatus_NBOOT_RequestTimeout         ((fsl_nboot_status_t)0x5A5AA5E1u) /*!< Operation timed out. */
+#define kStatus_NBOOT_KeyNotLoaded           ((fsl_nboot_status_t)0x5A5AA5E2u) /*!< The requested key is not loaded. */
+#define kStatus_NBOOT_AuthFail               ((fsl_nboot_status_t)0x5A5AA5E4u) /*!< Authentication failed. */
+#define kStatus_NBOOT_OperationNotAvaialable ((fsl_nboot_status_t)0x5A5AA5E5u) /*!< Operation not available on this HW. */
+#define kStatus_NBOOT_KeyNotAvailable        ((fsl_nboot_status_t)0x5A5AA5E6u) /*!< Key is not avaialble. */
+#define kStatus_NBOOT_IvCounterOverflow      ((fsl_nboot_status_t)0x5A5AA5E7u) /*!< Overflow of IV counter (PRINCE/IPED). */
+#define kStatus_NBOOT_SelftestFail           ((fsl_nboot_status_t)0x5A5AA5E8u) /*!< FIPS self-test failure. */
+#define kStatus_NBOOT_InvalidDataFormat      ((fsl_nboot_status_t)0x5A5AA5E9u) /*!< Invalid data format for example antipole */
+#define kStatus_NBOOT_IskCertUserDataTooBig \
+    ((fsl_nboot_status_t)0x5A5AA5EAu) /*!< Size of User data in ISK certificate is greater than 96 bytes */
+#define kStatus_NBOOT_IskCertSignatureOffsetTooSmall \
+    ((fsl_nboot_status_t)0x5A5AA5EBu) /*!< Signature offset in ISK certificate is smaller than expected */
+#define kStatus_NBOOT_MemcpyFail ((fsl_nboot_status_t)0x5A5A845A) /*!< Unexpected error detected during nboot_memcpy() */
+
+/*! @brief sb3.1 maigc number. */
+#define TAG_SB_V3 (0x33766273U) // "sbv3"
+
+/*!
+ * @brief NBOOT type for the root key revocation
+ *
+ * This type defines the NBOOT root key revocation
+ *
+ */
+#define kNBOOT_RootKey_Enabled (0xAAu)
+#define kNBOOT_RootKey_Revoked (0xBBu)
+
+/*! @brief The size of the root of trust key table hash. */
+#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12U)
+#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4U)
+
+/*! @brief The size of PKC Blob. */
+#define NBOOT_PCK_BLOB_SIZE_IN_WORD (12U)
+#define NBOOT_PCK_BLOB_SIZE_IN_BYTE (NBOOT_PCK_BLOB_SIZE_IN_WORD * 4U)
+
+/*!
+ * @brief NBOOT type specifying the elliptic curve to be used
+ *
+ * This type defines the elliptic curve type and length
+ *
+ */
+#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01u)
+#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02u)
+
+/*!
+ * @brief NBOOT type for the root key usage
+ *
+ * This type defines the NBOOT root key usage
+ *
+ */
+#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0u)
+#define kNBOOT_RootKeyUsage_Unused                              (0x7u)
+
+//! @brief SB loader status codes.
+enum _sbloader_status
+{
+    kStatusRomLdrSectionOverrun  = MAKE_STATUS(kStatusGroup_SBLoader, 0),
+    kStatusRomLdrSignature       = MAKE_STATUS(kStatusGroup_SBLoader, 1),
+    kStatusRomLdrSectionLength   = MAKE_STATUS(kStatusGroup_SBLoader, 2),
+    kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3),
+    kStatusRomLdrEOFReached      = MAKE_STATUS(kStatusGroup_SBLoader, 4),
+    kStatusRomLdrChecksum        = MAKE_STATUS(kStatusGroup_SBLoader, 5),
+    kStatusRomLdrCrc32Error      = MAKE_STATUS(kStatusGroup_SBLoader, 6),
+    kStatusRomLdrUnknownCommand  = MAKE_STATUS(kStatusGroup_SBLoader, 7),
+    kStatusRomLdrIdNotFound      = MAKE_STATUS(kStatusGroup_SBLoader, 8),
+    kStatusRomLdrDataUnderrun    = MAKE_STATUS(kStatusGroup_SBLoader, 9),
+    kStatusRomLdrJumpReturned    = MAKE_STATUS(kStatusGroup_SBLoader, 10),
+    kStatusRomLdrCallFailed      = MAKE_STATUS(kStatusGroup_SBLoader, 11),
+    kStatusRomLdrKeyNotFound     = MAKE_STATUS(kStatusGroup_SBLoader, 12),
+    kStatusRomLdrSecureOnly      = MAKE_STATUS(kStatusGroup_SBLoader, 13),
+    kStatusRomLdrResetReturned   = MAKE_STATUS(kStatusGroup_SBLoader, 14),
+
+    kStatusRomLdrRollbackBlocked        = MAKE_STATUS(kStatusGroup_SBLoader, 15),
+    kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16),
+    kStatusRomLdrUnexpectedCommand      = MAKE_STATUS(kStatusGroup_SBLoader, 17),
+    kStatusRomLdrBadSBKEK               = MAKE_STATUS(kStatusGroup_SBLoader, 18),
+    kStatusRomLdrPendingJumpCommand     = MAKE_STATUS(kStatusGroup_SBLoader, 19),
+};
+
+/*!
+ * @brief Boolean type for the NBOOT functions
+ *
+ * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks
+ *
+ */
+typedef enum _fsl_nboot_bool
+{
+    kNBOOT_TRUE                = 0x3C5AC33Cu, /*!< Value for TRUE.  */
+    kNBOOT_TRUE256             = 0x3C5AC35Au, /*!< Value for TRUE when P256 was used to sign the image.  */
+    kNBOOT_TRUE384             = 0x3C5AC3A5u, /*!< Value for TRUE when P384 was used to sign the image.  */
+    kNBOOT_FALSE               = 0x5AA55AA5u, /*!< Value for FALSE. */
+    kNBOOT_OperationAllowed    = 0x3c5a33ccU,
+    kNBOOT_OperationDisallowed = 0x5aa5cc33U,
+} fsl_nboot_bool_t;
+
+/** Type for nboot protected status codes */
+typedef uint64_t fsl_nboot_status_protected_t;
+
+/*!
+ * @brief NBOOT type for a timestamp
+ *
+ * This type defines the NBOOT timestamp
+ *
+ */
+typedef uint32_t fsl_nboot_timestamp_t[2];
+typedef uint32_t fsl_nboot_root_key_revocation_t;
+typedef uint32_t fsl_nboot_root_key_usage_t;
+typedef uint32_t fsl_nboot_root_key_type_and_length_t;
+typedef uint32_t fsl_nboot_soc_lifecycle_t;
+
+/*!
+ * @brief NBOOT type for the root of trust parameters
+ *
+ * This type defines the NBOOT root of trust parameters
+ *
+ */
+#define kNBOOT_SocRkh_Size_Words_P384 (12u)
+#define kNBOOT_SocRkh_Size_Words_P256 (8u)
+typedef struct _fsl_nboot_rot_auth_parms
+{
+    /* trusted information originated from CFPA */
+    fsl_nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM
+                                                                                 information in CFPA: ROTKH_REVOKE */
+    uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */
+
+    /* trusted information originated from CMPA */
+    uint32_t soc_rkh[kNBOOT_SocRkh_Size_Words_P384]; /*!< Provided by caller based on NVM information in CMPA: ROTKH
+                                                        (hash of hashes) */
+    /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */
+    /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */
+
+    uint32_t soc_numberOfRootKeys; /* unsigned int, between minimum = 1 and maximum = 4; */
+    fsl_nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /* CMPA */
+    fsl_nboot_root_key_type_and_length_t
+        soc_rootKeyTypeAndLength; /* static selection between ECDSA P-256 or ECDSA P-384 based root keys */
+
+    /* trusted information originated from OTP fuses */
+    fsl_nboot_soc_lifecycle_t soc_lifecycle;
+} fsl_nboot_rot_auth_parms_t;
+
+/*!
+ * @brief NBOOT SB3.1 header type
+ *
+ * This type defines the header used in the SB3.1 manifest
+ *
+ */
+typedef struct _fsl_nboot_sb3_header
+{
+    uint32_t magic;         /*! offset 0x00: Fixed 4-byte string of 'sbv3' without the trailing NULL */
+    uint32_t formatVersion; /*! offset 0x04: (major = 3, minor = 1); The format version determines the manifest (block0)
+                               size. */
+    uint32_t flags;         /*! offset 0x08: not defined yet, keep zero for future compatibility */
+    uint32_t blockCount;    /*! offset 0x0C: Number of blocks not including the manifest (block0). */
+    uint32_t blockSize; /*! offset 0x10: Size in bytes of data block (repeated blockCount times for SB3 data stream). */
+    fsl_nboot_timestamp_t timeStamp;     /*! offset 0x14: 64-bit value used as key derivation data. */
+    uint32_t firmwareVersion;        /*! offset 0x1c: Version number of the included firmware */
+    uint32_t imageTotalLength;       /*! offset 0x20: Total manifest length in bytes, including signatures etc. */
+    uint32_t imageType;              /*! offset 0x24: image type and flags */
+    uint32_t certificateBlockOffset; /*! offset 0x28: Offset from start of header block to the certificate block. */
+    uint8_t description[16];         /*! offset 0x32: This field provides description of the file. It is an arbitrary
+                                                      string injected by the signing tool, which helps to identify the file. */
+} fsl_nboot_sb3_header_t;
+
+/*!
+ * @brief  manifest loading parameters
+ *
+ * This type defines the NBOOT SB3.1 manifest loading parameters
+ *
+ */
+typedef struct _fsl_nboot_sb3_load_manifest_parms
+{
+    fsl_nboot_rot_auth_parms_t soc_RoTNVM;   /*! trusted information originated from CFPA and NMPA */
+    uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */
+    uint8_t pckBlob[48];                 /*! CSSv2 protected blob with Part Common Key (PCK) */
+} fsl_nboot_sb3_load_manifest_parms_t;
+
+/*! @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. Shall be read from SoC
+ * trusted NVM or SoC fuses. */
+typedef struct _fsl_nboot_img_auth_ecdsa_parms
+{
+    /* trusted information originated from CFPA and NMPA */
+    fsl_nboot_rot_auth_parms_t soc_RoTNVM;
+
+    uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */
+} fsl_nboot_img_auth_ecdsa_parms_t;
+
+/*! @brief The size of the blob with Key Blob. */
+#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32)
+#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48)
+#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384)
+
+#define NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES (808)
+#define NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES    (308)
+
+// Provides forward reference to the loader context definition.
+typedef struct _fsl_ldr_Context_v3 fsl_ldr_Context_v3_t;
+
+//! sb3 section definitions
+
+//! section type
+typedef enum _fsl_sectionType
+{
+    kSectionNone       = 0, // end or invalid
+    kSectionDataRange  = 1,
+    kSectionDiffUpdate = 2,
+    kSectionDDRConfig  = 3,
+    kSectionRegister   = 4,
+} fsl_section_type_t;
+
+#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) // bit 0
+#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK  (0x2u) // bit 1
+
+#define SB3_DATA_RANGE_HEADER_TAG       (0x55aaaa55U)
+#define SB3_DATA_ALIGNMENT_SIZE_IN_BYTE (16u)
+
+//! section data range structure
+typedef struct fsl_range_header
+{
+    uint32_t tag;
+    uint32_t startAddress;
+    uint32_t length;
+    uint32_t cmd;
+} fsl_sb3_data_range_header_t;
+
+typedef struct fsl_range_header_expansion
+{
+    uint32_t memoryId;
+    uint32_t pad0;
+    uint32_t pad1;
+    uint32_t pad2;
+} fsl_sb3_data_range_expansion_t;
+
+//! sb3 DATA section header format
+typedef struct fsl_section_header
+{
+    uint32_t sectionUid;
+    uint32_t sectionType;
+    uint32_t length;
+    uint32_t _pad;
+} fsl_sb3_section_header_t;
+
+// loader command enum
+
+typedef enum _fsl_loader_command_sb3
+{
+    kSB3_CmdInvalid = 0,
+    kSB3_CmdLoad    = 2,
+    kSB3_CmdExecute = 3,
+} fsl_sb3_cmd_t;
+
+//! The all of the allowed command
+#define SBLOADER_V3_CMD_SET_ALL ((1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute))
+
+#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(128, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX))
+
+/*! @brief Data structure holding secure counter value used by nboot library */
+typedef struct _fsl_nboot_secure_counter
+{
+    uint32_t sc;
+    uint32_t scAp;
+} fsl_nboot_secure_counter_t;
+
+/*!
+ * @brief NBOOT context type
+ *
+ * This type defines the NBOOT context
+ *
+ */
+typedef struct _fsl_nboot_context
+{
+    uint32_t totalBlocks; /*!< holds number of SB3 blocks. Initialized by nboot_sb3_load_header(). */
+    uint32_t processData; /*!< flag, initialized by nboot_sb3_load_header().
+                             SB3 related flag set by NBOOT in case the nboot_sb3_load_block()
+                             provides plain data to output buffer (for processing by ROM SB3 loader */
+    uint32_t timeout;     /*!< timeout value for css operation. In case it is 0, infinite wait is performed */
+    uint32_t keyinfo[NBOOT_KEYINFO_WORDLEN]; /*!< data for NBOOT key management. */
+    uint32_t context[NBOOT_CONTEXT_WORDLEN]; /*!< work area for NBOOT lib. */
+    uint32_t uuid[4];                        /*!< holds UUID value from NMPA */
+    uint32_t prngReadyFlag;     /*!< flag, used by nboot_rng_generate_lq_random() to determine whether CSS is ready to
+                                   generate rnd number */
+    uint32_t multipartMacBuffer[1024 / sizeof(uint32_t)];
+    uint32_t oemShareValidFlag; /*!< flag, used during TP to determine whether valid oemShare was set by
+                                   nboot_tp_isp_gen_oem_master_share() */
+    uint32_t oemShare[4]; /*!< buffer to store OEM_SHARE computed by nxpCLTrustProv_nboot_isp_gen_oem_master_share() */
+    fsl_nboot_secure_counter_t secureCounter; /*!< Secure counter used by nboot */
+    uint32_t rtf[NXPCLCSS_HASH_RTF_OUTPUT_SIZE / sizeof(uint32_t)];
+    uint32_t imageHash[48 / sizeof(uint32_t)];
+    uint32_t authStatus;
+    fsl_nboot_bool_t disableProvisioningFirmwareNXP; /*!< Flag to disable execution of NXP signed provisioning Firmwares */
+} fsl_nboot_context_t;
+
+//! @brief Structure of version property.
+//!
+//! @ingroup bl_core
+typedef union fsl_StandardVersion
+{
+    struct
+    {
+        uint8_t bugfix; //!< bugfix version [7:0]
+        uint8_t minor;  //!< minor version [15:8]
+        uint8_t major;  //!< major version [23:16]
+        char name;      //!< name [31:24]
+    };
+    uint32_t version;   //!< combined version numbers
+
+#if defined(__cplusplus)
+    StandardVersion() : version(0)
+    {
+    }
+    StandardVersion(uint32_t version) : version(version)
+    {
+    }
+#endif
+} fsl_standard_version_t;
+
+//!@brief Memory region information table
+typedef struct fsl_mem_region
+{
+    uint32_t start;
+    uint32_t end;
+} fsl_mem_region_t;
+
+//! @brief Memory Attribute Structure
+typedef struct _fsl_mem_attribute
+{
+    uint32_t memId;
+    uint32_t regionCount;
+    fsl_mem_region_t *memRegions;
+    void *context;
+} fsl_mem_attribute_t;
+
+typedef struct _fsl_arena_context
+{
+    uint32_t start;
+    uint32_t end;
+    uint32_t nextAddr;
+} fsl_arena_context_t;
+
+//!@brief Memory region interface structure
+typedef struct fsl_api_memory_region_interface
+{
+    status_t (*init)(fsl_mem_attribute_t *attr);
+#if defined(ROM_API_HAS_FEATURE_MEM_READ)
+#if ROM_API_HAS_FEATURE_MEM_READ
+    status_t (*read)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf);
+#endif
+#endif
+
+    status_t (*write)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf);
+    status_t (*fill)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern);
+    status_t (*flush)(fsl_mem_attribute_t *attr);
+    status_t (*erase)(fsl_mem_attribute_t *attr, uint32_t addr, uint32_t len);
+    status_t (*config)(fsl_mem_attribute_t *attr, uint32_t *buf);
+    status_t (*erase_all)(fsl_mem_attribute_t *attr);
+    status_t (*alloc_ctx)(fsl_arena_context_t *ctx, fsl_mem_attribute_t *attr, void *miscParams);
+} fsl_api_memory_region_interface_t;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+//! @brief Contiguous RAM region count
+#define RAM_REGION_COUNT (2U)
+
+//! @brief Contiguous FLEXSPINOR meomry count
+#define FLEXSPINOR_REGION_COUNT (1U)
+
+//! @brief Memory Interface count
+#define MEM_INTERFACE_COUNT (2U)
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _fsl_lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} fsl_flexspi_lut_seq_t;
+
+//!@brief FlexSPI Pad Configuration Override
+typedef struct
+{
+    uint8_t pu_pd_override_en;
+    uint8_t pu_pd_value;
+    uint8_t sr_config_override_en;
+    uint8_t sr_config_value;
+} fsl_flexspi_pad_config_override_t;
+
+typedef struct
+{
+    uint8_t time_100ps;  // Data valid time, in terms of 100ps
+    uint8_t delay_cells; // Data valid time, in terms of delay cells
+} fsl_flexspi_dll_time_t;
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _fsl_FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    fsl_flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    fsl_flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 (unused/not applicable on RW610)
+    uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 (unused/not applicable on RW610)
+    fsl_flexspi_pad_config_override_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    fsl_flexspi_pad_config_override_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    fsl_flexspi_pad_config_override_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    fsl_flexspi_pad_config_override_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;                                 //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;                             //!< [0x074-0x077] CS deselect interval between two commands
+    fsl_flexspi_dll_time_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B
+    uint16_t busyOffset;                 //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    fsl_flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t dll0CrVal;                 //!> [0x1b0-0x1b3] Customizable DLL0CR setting
+    uint32_t dll1CrVal;                 //!> [0x1b4-0x1b7] Customizable DLL1CR setting
+    uint32_t reserved4[2];              //!< [0x1b8-0x1bf] Reserved for future use
+} fsl_flexspi_mem_config_t;
+
+typedef struct fsl_soc_memory_map_struct
+{
+    struct
+    {
+        uint32_t start;
+        uint32_t end;
+    } ramRegions[RAM_REGION_COUNT];
+    struct
+    {
+        uint32_t start;
+        uint32_t end;
+    } flexspiNorRegions[FLEXSPINOR_REGION_COUNT];
+} fsl_soc_mem_regions_t;
+
+//!@brief Memory entry data structure
+typedef struct fsl_memory_map_entry
+{
+    fsl_mem_attribute_t *memoryAttribute;
+    const fsl_api_memory_region_interface_t *memoryInterface;
+} fsl_api_memory_map_entry_t;
+
+//!@brief API initialization data structure
+typedef struct fsl_kb_api_parameter_struct
+{
+    uint32_t allocStart;
+    uint32_t allocSize;
+} fsl_kp_api_init_param_t;
+
+//!@brief Memory context structure
+typedef struct fsl_memory_context_struct
+{
+    status_t (*flush)(fsl_mem_attribute_t *attr);
+    fsl_mem_attribute_t *attr;
+} fsl_mem_context_t;
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _fsl_flexspi_nor_config
+{
+    fsl_flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t isDataOrderSwapped;     //!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)
+    uint8_t reserved0[1];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t flashStateCtx;         //!< Flash State Context
+    uint32_t reserve2[10];          //!< Reserved for future use
+} fsl_flexspi_nor_config_t;
+
+//!@brief The API context structure
+typedef struct fsl_api_core_context
+{
+    fsl_soc_mem_regions_t memRegions;
+    fsl_arena_context_t arenaCtx;
+    fsl_flexspi_nor_config_t flexspinorCfg;
+    fsl_mem_context_t memCtx;
+    fsl_ldr_Context_v3_t *sbloaderCtx;
+    fsl_nboot_context_t *nbootCtx;
+    uint8_t *sharedBuf;
+    fsl_api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT];
+} fsl_api_core_context_t;
+
+//!@brief IAP API Interface structure
+typedef struct fsl_iap_api_interface_struct
+{
+    fsl_standard_version_t version; //!< IAP API version number.
+    status_t (*api_init)(fsl_api_core_context_t *coreCtx, const fsl_kp_api_init_param_t *param);
+    status_t (*api_deinit)(fsl_api_core_context_t *coreCtx);
+    status_t (*mem_init)(fsl_api_core_context_t *ctx);
+    status_t (*mem_read)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, uint8_t *buf, uint32_t memoryId);
+    status_t (*mem_write)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId);
+    status_t (*mem_fill)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId);
+    status_t (*mem_flush)(fsl_api_core_context_t *ctx);
+    status_t (*mem_erase)(fsl_api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId);
+    status_t (*mem_config)(fsl_api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId);
+    status_t (*mem_erase_all)(fsl_api_core_context_t *ctx, uint32_t memoryId);
+    status_t (*fsl_sbloader_init)(fsl_api_core_context_t *ctx);
+    status_t (*fsl_sbloader_pump)(fsl_api_core_context_t *ctx, uint8_t *data, uint32_t length);
+    status_t (*fsl_sbloader_finalize)(fsl_api_core_context_t *ctx);
+} fsl_iap_api_interface_t;
+
+//! Function pointer definition for all loader action functions.
+// typedef status_t (*fsl_pLdrFnc_v3_t)(ldr_Context_v3_t *);
+typedef status_t (*fsl_pLdrFnc_v3_t)(fsl_api_core_context_t *n);
+
+//! Loader context definition.
+struct _fsl_ldr_Context_v3
+{
+    fsl_pLdrFnc_v3_t Action;        //!< pointer to loader action function
+    uint32_t block_size;        //!< size of each block in bytes
+    uint32_t block_data_size;   //!< data size in bytes (NBOOT_SB3_CHUNK_SIZE_IN_BYTES)
+    uint32_t block_data_total;  //!< data max size in bytes (block_size * data_size
+    uint32_t block_buffer_size; //!< block0 and block size
+    uint32_t block_buffer_position;
+    uint8_t block_buffer[MAX(NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES,
+                             NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES)]; //! will be used for both block0 and blockx
+    uint32_t processedBlocks;
+
+    uint8_t data_block_offset; //! data block offset in a block.
+    bool in_data_block;        //!< in progress of handling a data block within a block
+    uint8_t *data_block;
+    uint32_t data_block_position;
+
+    bool in_data_section; //!< in progress of handling a data section within a data block
+    uint32_t data_section_handled;
+    fsl_sb3_section_header_t data_section_header;
+
+    bool in_data_range; //!< in progress of handling a data range within a data section
+    uint32_t data_range_handled;
+    uint32_t data_range_gap;
+    fsl_sb3_data_range_header_t data_range_header;
+    bool has_data_range_expansion;
+    fsl_sb3_data_range_expansion_t data_range_expansion;
+
+    uint32_t commandSet; //!< support command set during sb file handling
+
+    uint32_t data_position;
+    uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; //!< temporary data buffer
+
+    uint32_t fuse_cmd_position;
+    uint8_t fuse_cmd_buffer[32 * 4]; //!< used for fuse command
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif // __cplusplus
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+
+#define BIT0 (1UL << 0U)
+
+void power_on_device_impl(LOAD_Target_Type loadTarget);
+void power_off_device_impl(LOAD_Target_Type loadTarget);
+void reset_device(LOAD_Target_Type loadTarget);
+status_t load_service(LOAD_Target_Type loadTarget, uint32_t sourceAddr);
+status_t sb3_fw_download_impl(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+status_t sb3_fw_reset_impl(LOAD_Target_Type loadTarget, uint32_t flag, uint32_t sourceAddr);
+fsl_nboot_status_t nboot_hal_get_sb3_manifest_params(fsl_nboot_context_t *context, fsl_nboot_sb3_load_manifest_parms_t *parms);
+status_t loader_process_sb_file(uint32_t readOffset);
+status_t fsl_sbloader_init(fsl_api_core_context_t *ctx);
+status_t fsl_sbloader_finalize(fsl_api_core_context_t *ctx);
+uint8_t get_chip_revision(void);
+
+//! @}
+
+#endif /* __FSL_LOADER_UTILS_H__ */

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/life_cycle.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2020-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __LIFE_CYCLE_H__
+#define __LIFE_CYCLE_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Life cycle definitions. */
+#define LIFECYCLE_NXP_BLANK (0x0u)
+
+#define LIFECYCLE_NXP_DEV_NON_SEC (0xFDu)
+#define LIFECYCLE_NXP_DEV_SEC     (0xFEu)
+
+#define LIFECYCLE_NXP_PROVISIONED  (0x1u)
+#define LIFECYCLE_OEM_OPEN         (0x3u)
+#define LIFECYCLE_OEM_SECURE       (0x7u)
+#define LIFECYCLE_OEM_CLOSED       (0xFu)
+#define LIFECYCLE_OEM_FIELD_RETURN (0x1Fu)
+#define LIFECYCLE_NXP_FIELD_RETURN (0x3Fu)
+
+#define LIFECYCLE_OEM_LOCKED (0xCFu)
+#define LIFECYCLE_SHREDDED   (0xFFu)
+
+#define DIS_ROM_HIDIND_MASK  (0xF00000u)
+#define DIS_ROM_HIDIND_SHIFT (20u)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+uint32_t get_lifecycle_state(void);
+
+#endif

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/include/nboot_rom_api_table.h

@@ -0,0 +1,40 @@
+/*
+ *     Copyright 2020-2021 NXP
+ *     All rights reserved.
+ *
+ *     SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __NBOOT_ROM_API_TABLE_H__
+#define __NBOOT_ROM_API_TABLE_H__
+
+typedef int romapi_status_t;
+
+typedef struct
+{
+    romapi_status_t (*nboot_rsvd0)(void);
+    fsl_nboot_status_t (*nboot_context_init)(fsl_nboot_context_t *context);
+    fsl_nboot_status_t (*nboot_context_deinit)(fsl_nboot_context_t *context);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_manifest)(fsl_nboot_context_t *context,
+                                                        uint32_t *manifest,
+                                                        fsl_nboot_sb3_load_manifest_parms_t *parms);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_block)(fsl_nboot_context_t *context, uint32_t *block);
+    fsl_nboot_status_protected_t (*nboot_rsvd1)(void);
+    fsl_nboot_status_protected_t (*nboot_rsvd2)(void);
+} nboot_interface_v0_t;
+
+typedef struct
+{
+    romapi_status_t (*romapi_rng_generate_random)(uint8_t *output, size_t outputByteLen);
+    fsl_nboot_status_t (*nboot_context_init)(fsl_nboot_context_t *context);
+    fsl_nboot_status_t (*nboot_context_deinit)(fsl_nboot_context_t *context);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_manifest)(fsl_nboot_context_t *context,
+                                                        uint32_t *manifest,
+                                                        fsl_nboot_sb3_load_manifest_parms_t *parms);
+    fsl_nboot_status_protected_t (*nboot_sb3_load_block)(fsl_nboot_context_t *context, uint32_t *block);
+    fsl_nboot_status_protected_t (*nboot_img_authenticate_ecdsa)(fsl_nboot_context_t *context,
+                                                             uint8_t imageStartAddress[],
+                                                             fsl_nboot_bool_t *isSignatureVerified,
+                                                             fsl_nboot_img_auth_ecdsa_parms_t *parms);
+} nboot_interface_v1_t;
+
+#endif /* _NBOOT_ROM_API_TABLE_H_ */

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/life_cycle.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 - 2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "life_cycle.h"
+#include "fusemap.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+uint32_t get_lifecycle_state(void)
+{
+    uint32_t lifeCycleStateOtpShadow          = OTP_LCS_FUSE_VALUE();
+    uint32_t lifeCycleStateRedundantOtpShadow = OTP_LCS_REDUNDANT_FUSE_VALUE();
+    if (lifeCycleStateOtpShadow != lifeCycleStateRedundantOtpShadow)
+    {
+        while (true)
+        {
+            ; /* No necessary actions. */
+        }
+    }
+
+    return ((lifeCycleStateOtpShadow & OTP_LCS_FUSE_MASK) >> OTP_LCS_FUSE_SHIFT);
+}

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/nboot_hal.c

@@ -0,0 +1,304 @@
+/*
+ * Copyright 2020 - 2021,2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <limits.h>
+#include "fusemap.h"
+#include "fsl_loader_utils.h"
+#include "life_cycle.h"
+#include "fsl_ocotp.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define NBOOT_HAL_PRINTF(...)
+
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+/*!
+ * @brief Get the root security parameters.
+ *
+ * Read the root security configurations from OTP.
+ *
+ * @param context   NBOOT context.
+ * @param parms     Root security parameters.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_InvalidArgument Invalid values of the parms
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static fsl_nboot_status_t nboot_hal_get_root_auth_parms(fsl_nboot_context_t *context, fsl_nboot_rot_auth_parms_t *parms);
+
+/*!
+ * @brief Get the ROTK revoke settings.
+ *
+ * Read the OTP_ROTK_REVOKE.
+ *
+ * @param rotkRevoke ROTK revoke state.
+ * @param rotkCnt ROTK count.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static inline fsl_nboot_status_t nboot_hal_get_rotk_revoke(fsl_nboot_root_key_revocation_t *rotkRevoke, uint32_t rotkCnt);
+
+/*!
+ * @brief Get the ROTKH.
+ *
+ * Read the IFR_ROTKH.
+ *
+ * @param rotkh ROTKH value.
+ * @param rotkhSize ROTKH size in bytes.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static fsl_nboot_status_t nboot_hal_get_rotkh(uint32_t *rotkh, uint32_t rotkhSize);
+
+/*!
+ * @brief Get the type of the root keys.
+ *
+ * Get the root key type
+ *
+ * @param rootKeyType Type of the root keys.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static inline fsl_nboot_status_t nboot_hal_get_root_key_type(fsl_nboot_root_key_type_and_length_t *rootKeyType);
+
+/*!
+ * @brief Get the Part Common Key(PCK).
+ *
+ * Read the IFR_PCK_BLOB.
+ *
+ * @param pckBlob PCK blob.
+ * @param pckBlobSize PCK blob size in byte.
+ * @retval kStatus_NBOOT_Fail Operate successfully.
+ * @retval kStatus_NBOOT_Fail Failed to operate.
+ */
+static inline fsl_nboot_status_t nboot_hal_get_pck_blob(uint8_t *pckBlob, uint32_t pckBlobSize);
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static inline uint32_t set_antipole(uint32_t value)
+{
+    return (value & 0xFFFFu) | (~(value & 0xFFFFu) << 16);
+}
+
+static fsl_nboot_status_t nboot_hal_get_root_auth_parms(fsl_nboot_context_t *context, fsl_nboot_rot_auth_parms_t *parms)
+{
+    if ((NULL == context) || (NULL == parms))
+    {
+        return kStatus_NBOOT_InvalidArgument;
+    }
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Fail;
+    do
+    {
+        status =
+            nboot_hal_get_rotk_revoke(&parms->soc_rootKeyRevocation[0],
+                                      sizeof(parms->soc_rootKeyRevocation) / sizeof(parms->soc_rootKeyRevocation[0]));
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = nboot_hal_get_rotkh(&parms->soc_rkh[0], sizeof(parms->soc_rkh));
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        parms->soc_numberOfRootKeys = 0u;
+        parms->soc_rootKeyUsage[1]  = kNBOOT_RootKeyUsage_Unused;
+        parms->soc_rootKeyUsage[2]  = kNBOOT_RootKeyUsage_Unused;
+        parms->soc_rootKeyUsage[3]  = kNBOOT_RootKeyUsage_Unused;
+        for (size_t i = 0; i < (sizeof(parms->soc_rootKeyUsage) / sizeof(parms->soc_rootKeyUsage[0])); i++)
+        {
+            if ((parms->soc_rootKeyUsage[i] & OTP_ROTK0_USAGE_FUSE_MASK) != kNBOOT_RootKeyUsage_Unused)
+            {
+                parms->soc_numberOfRootKeys++;
+            }
+        }
+
+        status = nboot_hal_get_root_key_type(&parms->soc_rootKeyTypeAndLength);
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        parms->soc_lifecycle = (fsl_nboot_soc_lifecycle_t)set_antipole(get_lifecycle_state());
+        status               = kStatus_NBOOT_Success;
+    } while (false);
+	
+	if (status != kStatus_NBOOT_Success)
+	{
+	    (void)memset(parms, 0, sizeof(*parms));
+	}
+
+    return status;
+}
+
+static inline fsl_nboot_status_t nboot_hal_get_rotk_revoke(fsl_nboot_root_key_revocation_t *rotkRevoke, uint32_t rotkCnt)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(rotkRevoke);
+    assert(rotkCnt == NBOOT_ROOT_CERT_COUNT);
+
+    /* Set all root key to 'revoked' state */
+    for (uint32_t i = 0u; i < rotkCnt; i++)
+    {
+        rotkRevoke[i] = kNBOOT_RootKey_Enabled;
+    }
+
+    return kStatus_NBOOT_Success;
+}
+
+static fsl_nboot_status_t nboot_hal_get_rotkh(uint32_t *rotkh, uint32_t rotkhSize)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(rotkh);
+    assert(rotkhSize == (uint32_t)NBOOT_ROOT_ROTKH_SIZE_IN_BYTE);
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Success;
+
+    /* root key hash fixed in Flash memory */
+#ifdef USE_ENG_CERTIFICATE
+    rotkh[0]  = 0xd0cfb419U;
+    rotkh[1]  = 0x4037ee3cU;
+    rotkh[2]  = 0xde74393eU;
+    rotkh[3]  = 0x0156d0a3U;
+    rotkh[4]  = 0x373b8677U;
+    rotkh[5]  = 0x6b6aee3dU;
+    rotkh[6]  = 0x619b459eU;
+    rotkh[7]  = 0xfa33f31dU;
+    rotkh[8]  = 0x00000000U;
+    rotkh[9]  = 0x00000000U;
+    rotkh[10] = 0x00000000U;
+    rotkh[11] = 0x00000000U;
+#else
+    if ((get_chip_revision() == 0U))
+    {
+        rotkh[0]  = 0x60DFBEE6U;
+        rotkh[1]  = 0x8799305FU;
+        rotkh[2]  = 0xBA9E4AE6U;
+        rotkh[3]  = 0x1908394FU;
+        rotkh[4]  = 0x7AC4F934U;
+        rotkh[5]  = 0xEF76BF41U;
+        rotkh[6]  = 0x2E27796EU;
+        rotkh[7]  = 0x94DB19A0U;
+        rotkh[8]  = 0x00000000U;
+        rotkh[9]  = 0x00000000U;
+        rotkh[10] = 0x00000000U;
+        rotkh[11] = 0x00000000U;
+    }
+    else if ((get_chip_revision() == 1U))
+    {
+        rotkh[0]  = 0x9C758C58U;
+        rotkh[1]  = 0x0A5CCEAAU;
+        rotkh[2]  = 0x850DAD41U;
+        rotkh[3]  = 0x1371EEBAU;
+        rotkh[4]  = 0xB7874851U;
+        rotkh[5]  = 0x53C5BA44U;
+        rotkh[6]  = 0xF236F964U;
+        rotkh[7]  = 0x3320ECDFU;
+        rotkh[8]  = 0x00000000U;
+        rotkh[9]  = 0x00000000U;
+        rotkh[10] = 0x00000000U;
+        rotkh[11] = 0x00000000U;
+    }
+    else if ((get_chip_revision() == 2U))
+    {
+        rotkh[0]  = 0xE7C7E9BBU;
+        rotkh[1]  = 0x12C8C535U;
+        rotkh[2]  = 0x37E61148U;
+        rotkh[3]  = 0x2BE7F18CU;
+        rotkh[4]  = 0x8F0E3094U;
+        rotkh[5]  = 0xB2BA7F32U;
+        rotkh[6]  = 0xEC9B4ECBU;
+        rotkh[7]  = 0xAD9FC941U;
+        rotkh[8]  = 0x00000000U;
+        rotkh[9]  = 0x00000000U;
+        rotkh[10] = 0x00000000U;
+        rotkh[11] = 0x00000000U;
+    }
+	else
+	{
+	    ; /* none to do */
+	}
+#endif
+    return status;
+}
+
+static inline fsl_nboot_status_t nboot_hal_get_root_key_type(fsl_nboot_root_key_type_and_length_t *rootKeyType)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(rootKeyType);
+
+    *rootKeyType = kNBOOT_RootKey_Ecdsa_P256;
+
+    return kStatus_NBOOT_Success;
+}
+
+static inline fsl_nboot_status_t nboot_hal_get_pck_blob(uint8_t *pckBlob, uint32_t pckBlobSize)
+{
+    /* No need to check the input arguments for this inline functions. */
+    assert(pckBlob);
+    assert(pckBlobSize == (uint32_t)NBOOT_PCK_BLOB_SIZE_IN_BYTE);
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Fail;
+    status_t otpStatus    = kStatus_Fail;
+
+    do
+    {
+        uint32_t fuseIdxStart = OTP_NXP_WIFI_SK_MK_31_0_FUSE_IDX;
+        for (int i = 0; i < (NBOOT_PCK_BLOB_SIZE_IN_BYTE / 4); i++)
+        {
+            otpStatus = OCOTP_OtpFuseRead(fuseIdxStart, (uint32_t *)(&pckBlob[4 * i]));
+            if (otpStatus != kStatus_Success)
+            {
+                return kStatus_NBOOT_Fail;
+            }
+            ++fuseIdxStart;
+        }
+        status = kStatus_NBOOT_Success;
+    } while (false);
+
+    return status;
+}
+
+fsl_nboot_status_t nboot_hal_get_sb3_manifest_params(fsl_nboot_context_t *context, fsl_nboot_sb3_load_manifest_parms_t *parms)
+{
+    if ((NULL == context) || (NULL == parms))
+    {
+        return kStatus_NBOOT_InvalidArgument;
+    }
+
+    fsl_nboot_status_t status = kStatus_NBOOT_Fail;
+    do
+    {
+        status = nboot_hal_get_root_auth_parms(context, &parms->soc_RoTNVM);
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = nboot_hal_get_pck_blob(&parms->pckBlob[0], sizeof(parms->pckBlob));
+        if (status != kStatus_NBOOT_Success)
+        {
+            break;
+        }
+
+        status = kStatus_NBOOT_Success;
+    } while (false);
+
+    if (status != kStatus_NBOOT_Success)
+    {
+        (void)memset(parms, 0, sizeof(*parms));
+    }
+
+    return status;
+}

tutorials/nxp/frdm-rw612-xpresso-freertos-builtin-wifi/component/conn_fwloader/readme.txt

@@ -0,0 +1,38 @@
+1.Examples that support monolithic image download do not need the steps 2-6 to load fw:
+    Wi-Fi examples: wifi_cli, wifi_wpa_supplicant, wifi_cli_static, wifi_cert, wifi_cli_fw_dump, wifi_cli_prov, wifi_test_mode
+	ncp examples: ncp_device
+	coex examples: coex_cli, coex_supplicant_cli
+
+	These examples can load cpu1/2 fw automatically, don't need to load them seperatly.
+
+2. FW image names:
+	Production FW, for users:
+		rw61x_sb_wifi_a2.bin, for CPU1_wifi of redfinch a2 board
+		rw61x_sb_ble_a2.bin, for CPU2_ble of redfinch a2 board
+		rw61x_sb_ble_15d4_combo_a2.bin, for CPU2_ble_15.4_combo of redfinch a2 board
+
+3. where to get FW image(Production and mfg_FW):
+	In the directory:  /components/conn_fwloader/fw_bin
+
+4. How to load FW(Production and mfg_FW):
+	Need to write the FW image to flash first, then the loadservice will download FW when power on.
+	For example, the CMD to write CPU1 image to flash in J-link window:
+		loadbin C:\xxx\rw61x_sb_wifi_xx.bin,0x08400000
+
+	The CMD to write CPU2_ble image to flash in J-link window:
+		loadbin C:\xxx\rw61x_sb_ble_xx.bin,0x08540000
+
+	The CMD to write CPU2_15.4 image to flash in J-link window:
+		loadbin C:\xxx\rw61x_sb_ble_15d4_combo_xx.bin,0x085e0000
+
+5. How to generate the C files to be compiled in the monolithic binary:
+	In a shell go to directory /components/conn_fwloader. Enter the following command:
+	 'python script/fw_bin2c_conv.py -t sb fw_bin'
+	or 'python script/fw_bin2c_conv.py -t raw fw_bin':
+	This results in generating the C files under fw_bin/A1 and fw_bin/A2 subdirectories.
+
+6. Remap mechanism support
+	Whenever the remap feature is active, the flash should not be accessed in direct mode.
+	As a consequence, no structure cast should be done on flash direct addresses. Likewise memcpy operations
+	should be avoided. Instead all flash accesses must be done via staging buffers in RAM, that 
+	get loaded using the mflash driver.