mirror of
https://github.com/cesanta/mongoose.git
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217 lines
8.2 KiB
C
217 lines
8.2 KiB
C
#include "tcpip.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && \
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MG_ENABLE_DRIVER_SAME54
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#include <sam.h>
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ETH_PKT_SIZE 1536 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 2 // Descriptor size (words)
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_txno; // Current TX descriptor
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static uint8_t s_rxno; // Current RX descriptor
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static struct mg_tcpip_if *s_ifp; // MIP interface
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enum { PHY_ADDR = 0, PHY_BCR = 0, PHY_BSR = 1 };
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#define PHY_BCR_DUPLEX_MODE_Msk BIT(8)
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#define PHY_BCR_SPEED_Msk BIT(13)
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#define PHY_BSR_LINK_STATUS_Msk BIT(2)
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static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
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GMAC_REGS->GMAC_MAN = GMAC_MAN_CLTTO_Msk |
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GMAC_MAN_OP(2) | // Setting the read operation
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GMAC_MAN_WTN(2) | GMAC_MAN_PHYA(addr) | // PHY address
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GMAC_MAN_REGA(reg); // Setting the register
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while (!(GMAC_REGS->GMAC_NSR & GMAC_NSR_IDLE_Msk)) (void) 0;
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return GMAC_REGS->GMAC_MAN & GMAC_MAN_DATA_Msk; // Getting the read value
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}
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#if 0
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint16_t val) {
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GMAC_REGS->GMAC_MAN = GMAC_MAN_CLTTO_Msk | GMAC_MAN_OP(1) | // Setting the write operation
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GMAC_MAN_WTN(2) | GMAC_MAN_PHYA(addr) | // PHY address
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GMAC_MAN_REGA(reg) | GMAC_MAN_DATA(val); // Setting the register
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while (!(GMAC_REGS->GMAC_NSR & GMAC_NSR_IDLE_Msk)); // Waiting until the write op is complete
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}
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#endif
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int get_clock_rate(struct mg_tcpip_driver_same54_data *d) {
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if (d && d->mdc_cr >= 0 && d->mdc_cr <= 5) {
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return d->mdc_cr;
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} else {
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// get MCLK from GCLK_GENERATOR 0
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uint32_t div = 512;
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uint32_t mclk;
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if (!(GCLK_REGS->GCLK_GENCTRL[0] & GCLK_GENCTRL_DIVSEL_Msk)) {
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div = ((GCLK_REGS->GCLK_GENCTRL[0] & 0x00FF0000) >> 16);
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if (div == 0) div = 1;
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}
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switch (GCLK_REGS->GCLK_GENCTRL[0] & GCLK_GENCTRL_SRC_Msk) {
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case GCLK_GENCTRL_SRC_XOSC0_Val:
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mclk = 32000000UL; /* 32MHz */
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break;
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case GCLK_GENCTRL_SRC_XOSC1_Val:
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mclk = 32000000UL; /* 32MHz */
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break;
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case GCLK_GENCTRL_SRC_OSCULP32K_Val:
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mclk = 32000UL;
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break;
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case GCLK_GENCTRL_SRC_XOSC32K_Val:
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mclk = 32000UL;
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break;
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case GCLK_GENCTRL_SRC_DFLL_Val:
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mclk = 48000000UL; /* 48MHz */
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break;
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case GCLK_GENCTRL_SRC_DPLL0_Val:
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mclk = 200000000UL; /* 200MHz */
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break;
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case GCLK_GENCTRL_SRC_DPLL1_Val:
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mclk = 200000000UL; /* 200MHz */
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break;
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default:
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mclk = 200000000UL; /* 200MHz */
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}
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mclk /= div;
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uint8_t crs[] = {0, 1, 2, 3, 4, 5}; // GMAC->NCFGR::CLK values
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uint8_t dividers[] = {8, 16, 32, 48, 64, 128}; // Respective CLK dividers
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for (int i = 0; i < 6; i++) {
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if (mclk / dividers[i] <= 2375000UL /* 2.5MHz - 5% */) {
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return crs[i];
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}
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}
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return 5;
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}
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}
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static bool mg_tcpip_driver_same54_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_same54_data *d =
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(struct mg_tcpip_driver_same54_data *) ifp->driver_data;
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s_ifp = ifp;
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MCLK_REGS->MCLK_APBCMASK |= MCLK_APBCMASK_GMAC_Msk;
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MCLK_REGS->MCLK_AHBMASK |= MCLK_AHBMASK_GMAC_Msk;
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GMAC_REGS->GMAC_NCFGR = GMAC_NCFGR_CLK(get_clock_rate(d)); // Set MDC divider
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GMAC_REGS->GMAC_NCR = 0; // Disable RX & TX
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GMAC_REGS->GMAC_NCR |= GMAC_NCR_MPE_Msk; // Enable MDC & MDIO
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init TX descriptors
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s_txdesc[i][0] = (uint32_t) s_txbuf[i]; // Point to data buffer
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s_txdesc[i][1] = BIT(31); // OWN bit
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}
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s_txdesc[ETH_DESC_CNT - 1][1] |= BIT(30); // Last tx descriptor - wrap
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GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18); // DMA recv buf 1536
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init RX descriptors
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s_rxdesc[i][0] = (uint32_t) s_rxbuf[i]; // Address of the data buffer
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s_rxdesc[i][1] = 0; // Clear status
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}
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s_rxdesc[ETH_DESC_CNT - 1][0] |= BIT(1); // Last rx descriptor - wrap
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GMAC_REGS->GMAC_TBQB = (uint32_t) s_txdesc; // about the descriptor addresses
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GMAC_REGS->GMAC_RBQB = (uint32_t) s_rxdesc; // Let the controller know
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GMAC_REGS->SA[0].GMAC_SAB =
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MG_U32(ifp->mac[3], ifp->mac[2], ifp->mac[1], ifp->mac[0]);
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GMAC_REGS->SA[0].GMAC_SAT = MG_U32(0, 0, ifp->mac[5], ifp->mac[4]);
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GMAC_REGS->GMAC_UR &= ~GMAC_UR_MII_Msk; // Disable MII, use RMII
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GMAC_REGS->GMAC_NCFGR |= GMAC_NCFGR_MAXFS_Msk | GMAC_NCFGR_MTIHEN_Msk |
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GMAC_NCFGR_EFRHD_Msk | GMAC_NCFGR_CAF_Msk;
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GMAC_REGS->GMAC_TSR = GMAC_TSR_HRESP_Msk | GMAC_TSR_UND_Msk |
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GMAC_TSR_TXCOMP_Msk | GMAC_TSR_TFC_Msk |
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GMAC_TSR_TXGO_Msk | GMAC_TSR_RLE_Msk |
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GMAC_TSR_COL_Msk | GMAC_TSR_UBR_Msk;
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GMAC_REGS->GMAC_RSR = GMAC_RSR_HNO_Msk | GMAC_RSR_RXOVR_Msk |
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GMAC_RSR_REC_Msk | GMAC_RSR_BNA_Msk;
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GMAC_REGS->GMAC_IDR = ~0U; // Disable interrupts, then enable required
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GMAC_REGS->GMAC_IER = GMAC_IER_HRESP_Msk | GMAC_IER_ROVR_Msk |
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GMAC_IER_TCOMP_Msk | GMAC_IER_TFC_Msk |
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GMAC_IER_RLEX_Msk | GMAC_IER_TUR_Msk |
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GMAC_IER_RXUBR_Msk | GMAC_IER_RCOMP_Msk;
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GMAC_REGS->GMAC_NCR |= GMAC_NCR_TXEN_Msk | GMAC_NCR_RXEN_Msk;
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NVIC_EnableIRQ(GMAC_IRQn);
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return true;
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}
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static size_t mg_tcpip_driver_same54_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[s_txno])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][1] & BIT(31)) == 0) {
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ifp->nerr++;
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MG_ERROR(("No free descriptors"));
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len = 0; // All descriptors are busy, fail
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} else {
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uint32_t status = len | BIT(15); // Frame length, last chunk
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if (s_txno == ETH_DESC_CNT - 1) status |= BIT(30); // wrap
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = status;
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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__DSB(); // Ensure descriptors have been written
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GMAC_REGS->GMAC_NCR |= GMAC_NCR_TSTART_Msk; // Enable transmission
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return len;
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}
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static bool mg_tcpip_driver_same54_up(struct mg_tcpip_if *ifp) {
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uint16_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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bool up = bsr & PHY_BSR_LINK_STATUS_Msk ? 1 : 0;
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// If PHY is ready, update NCFGR accordingly
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if (ifp->state == MG_TCPIP_STATE_DOWN && up) {
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uint16_t bcr = eth_read_phy(PHY_ADDR, PHY_BCR);
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bool fd = bcr & PHY_BCR_DUPLEX_MODE_Msk ? 1 : 0;
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bool spd = bcr & PHY_BCR_SPEED_Msk ? 1 : 0;
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GMAC_REGS->GMAC_NCFGR =
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GMAC_REGS->GMAC_NCFGR & ~(GMAC_NCFGR_SPD_Msk | PHY_BCR_SPEED_Msk) |
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GMAC_NCFGR_SPD(spd) | GMAC_NCFGR_FD(fd);
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}
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return up;
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}
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void GMAC_Handler(void);
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void GMAC_Handler(void) {
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uint32_t isr = GMAC_REGS->GMAC_ISR;
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uint32_t rsr = GMAC_REGS->GMAC_RSR;
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uint32_t tsr = GMAC_REGS->GMAC_TSR;
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if (isr & GMAC_ISR_RCOMP_Msk) {
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if (rsr & GMAC_ISR_RCOMP_Msk) {
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for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
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if ((s_rxdesc[s_rxno][0] & BIT(0)) == 0) break;
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size_t len = s_rxdesc[s_rxno][1] & (BIT(13) - 1);
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
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s_rxdesc[s_rxno][0] &= ~BIT(0); // Disown
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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}
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}
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if ((tsr & (GMAC_TSR_HRESP_Msk | GMAC_TSR_UND_Msk | GMAC_TSR_TXCOMP_Msk |
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GMAC_TSR_TFC_Msk | GMAC_TSR_TXGO_Msk | GMAC_TSR_RLE_Msk |
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GMAC_TSR_COL_Msk | GMAC_TSR_UBR_Msk)) != 0) {
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// MG_INFO((" --> %#x %#x", s_txdesc[s_txno][1], tsr));
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if (!(s_txdesc[s_txno][1] & BIT(31))) s_txdesc[s_txno][1] |= BIT(31);
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}
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GMAC_REGS->GMAC_RSR = rsr;
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GMAC_REGS->GMAC_TSR = tsr;
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}
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struct mg_tcpip_driver mg_tcpip_driver_same54 = {
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mg_tcpip_driver_same54_init, mg_tcpip_driver_same54_tx, NULL,
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mg_tcpip_driver_same54_up};
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#endif
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