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https://github.com/lm-sensors/lm-sensors.git
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remove initialization of limits by driver
git-svn-id: http://lm-sensors.org/svn/lm-sensors/trunk@2071 7894878c-1315-0410-8ee3-d5d059ff63e0
This commit is contained in:
Mark D. Studebaker committed
1 parent
8cf5eaa5f1
commit
06d823b430
1 file changed
-252
@@ -234,111 +234,6 @@ static inline u8 DIV_TO_REG(long val, enum chips type)
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return ((u8) i);
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}
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/* Initial limits */
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#define W83781D_INIT_IN_0 (vid==3500?280:vid/10)
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#define W83781D_INIT_IN_1 (vid==3500?280:vid/10)
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#define W83781D_INIT_IN_2 330
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#define W83781D_INIT_IN_3 (((500) * 100)/168)
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#define W83781D_INIT_IN_4 (((1200) * 10)/38)
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#define W83781D_INIT_IN_5 (((-1200) * -604)/2100)
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#define W83781D_INIT_IN_6 (((-500) * -604)/909)
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#define W83781D_INIT_IN_7 (((500) * 100)/168)
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#define W83781D_INIT_IN_8 300
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#define W83781D_INIT_IN_9 250 /* 2.5 Volt for the DDR interface. */
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/* Initial limits for 782d/783s negative voltages */
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/* Note level shift. Change min/max below if you change these. */
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#define W83782D_INIT_IN_5 ((((-1200) + 1491) * 100)/514)
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#define W83782D_INIT_IN_6 ((( (-500) + 771) * 100)/314)
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#define W83781D_INIT_IN_PERCENTAGE 10
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#define W83781D_INIT_IN_MIN_0 \
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(W83781D_INIT_IN_0 - W83781D_INIT_IN_0 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_0 \
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(W83781D_INIT_IN_0 + W83781D_INIT_IN_0 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_1 \
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(W83781D_INIT_IN_1 - W83781D_INIT_IN_1 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_1 \
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(W83781D_INIT_IN_1 + W83781D_INIT_IN_1 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_2 \
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(W83781D_INIT_IN_2 - W83781D_INIT_IN_2 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_2 \
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(W83781D_INIT_IN_2 + W83781D_INIT_IN_2 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_3 \
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(W83781D_INIT_IN_3 - W83781D_INIT_IN_3 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_3 \
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(W83781D_INIT_IN_3 + W83781D_INIT_IN_3 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_4 \
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(W83781D_INIT_IN_4 - W83781D_INIT_IN_4 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_4 \
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(W83781D_INIT_IN_4 + W83781D_INIT_IN_4 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_5 \
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(W83781D_INIT_IN_5 - W83781D_INIT_IN_5 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_5 \
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(W83781D_INIT_IN_5 + W83781D_INIT_IN_5 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_6 \
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(W83781D_INIT_IN_6 - W83781D_INIT_IN_6 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_6 \
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(W83781D_INIT_IN_6 + W83781D_INIT_IN_6 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_7 \
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(W83781D_INIT_IN_7 - W83781D_INIT_IN_7 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_7 \
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(W83781D_INIT_IN_7 + W83781D_INIT_IN_7 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_8 \
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(W83781D_INIT_IN_8 - W83781D_INIT_IN_8 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_8 \
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(W83781D_INIT_IN_8 + W83781D_INIT_IN_8 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MIN_9 \
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(W83781D_INIT_IN_9 - W83781D_INIT_IN_9 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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#define W83781D_INIT_IN_MAX_9 \
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(W83781D_INIT_IN_9 + W83781D_INIT_IN_9 * W83781D_INIT_IN_PERCENTAGE \
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/ 100)
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/* Initial limits for 782d/783s negative voltages */
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/* These aren't direct multiples because of level shift */
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/* Beware going negative - check */
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#define W83782D_INIT_IN_MIN_5_TMP \
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(((-1200 * (100 + W83781D_INIT_IN_PERCENTAGE)) + (1491 * 100))/514)
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#define W83782D_INIT_IN_MIN_5 \
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((W83782D_INIT_IN_MIN_5_TMP > 0) ? W83782D_INIT_IN_MIN_5_TMP : 0)
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#define W83782D_INIT_IN_MAX_5 \
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(((-1200 * (100 - W83781D_INIT_IN_PERCENTAGE)) + (1491 * 100))/514)
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#define W83782D_INIT_IN_MIN_6_TMP \
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((( -500 * (100 + W83781D_INIT_IN_PERCENTAGE)) + (771 * 100))/314)
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#define W83782D_INIT_IN_MIN_6 \
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((W83782D_INIT_IN_MIN_6_TMP > 0) ? W83782D_INIT_IN_MIN_6_TMP : 0)
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#define W83782D_INIT_IN_MAX_6 \
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((( -500 * (100 - W83781D_INIT_IN_PERCENTAGE)) + (771 * 100))/314)
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#define W83781D_INIT_FAN_MIN_1 3000
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#define W83781D_INIT_FAN_MIN_2 3000
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#define W83781D_INIT_FAN_MIN_3 3000
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#define W83781D_INIT_TEMP_OVER 600
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#define W83781D_INIT_TEMP_HYST 1270 /* must be 127 for ALARM to work */
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#define W83781D_INIT_TEMP2_OVER 600
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#define W83781D_INIT_TEMP2_HYST 500
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#define W83781D_INIT_TEMP3_OVER 600
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#define W83781D_INIT_TEMP3_HYST 500
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/* There are some complications in a module like this. First off, W83781D chips
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may be both present on the SMBus and the ISA bus, and we have to handle
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those cases separately at some places. Second, there might be several
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@@ -1480,154 +1375,7 @@ static void w83781d_init_client(struct i2c_client *client)
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#endif /* W83781D_RT */
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if(init) {
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if (type == w83791d) {
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w83781d_write_value(client, W83791D_REG_IN_MIN(0),
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IN_TO_REG(W83781D_INIT_IN_MIN_0));
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w83781d_write_value(client, W83791D_REG_IN_MAX(0),
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IN_TO_REG(W83781D_INIT_IN_MAX_0));
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w83781d_write_value(client, W83791D_REG_IN_MIN(1),
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IN_TO_REG(W83781D_INIT_IN_MIN_1));
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w83781d_write_value(client, W83791D_REG_IN_MAX(1),
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IN_TO_REG(W83781D_INIT_IN_MAX_1));
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w83781d_write_value(client, W83791D_REG_IN_MIN(2),
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IN_TO_REG(W83781D_INIT_IN_MIN_2));
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w83781d_write_value(client, W83791D_REG_IN_MAX(2),
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IN_TO_REG(W83781D_INIT_IN_MAX_2));
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w83781d_write_value(client, W83791D_REG_IN_MIN(3),
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IN_TO_REG(W83781D_INIT_IN_MIN_3));
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w83781d_write_value(client, W83791D_REG_IN_MAX(3),
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IN_TO_REG(W83781D_INIT_IN_MAX_3));
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w83781d_write_value(client, W83791D_REG_IN_MIN(4),
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IN_TO_REG(W83781D_INIT_IN_MIN_4));
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w83781d_write_value(client, W83791D_REG_IN_MAX(4),
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IN_TO_REG(W83781D_INIT_IN_MAX_4));
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w83781d_write_value(client, W83791D_REG_IN_MIN(5),
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IN_TO_REG(W83781D_INIT_IN_MIN_5));
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w83781d_write_value(client, W83791D_REG_IN_MAX(5),
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IN_TO_REG(W83781D_INIT_IN_MAX_5));
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w83781d_write_value(client, W83791D_REG_IN_MIN(6),
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IN_TO_REG(W83781D_INIT_IN_MIN_6));
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w83781d_write_value(client, W83791D_REG_IN_MAX(6),
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IN_TO_REG(W83781D_INIT_IN_MAX_6));
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w83781d_write_value(client, W83791D_REG_IN_MIN(7),
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IN_TO_REG(W83781D_INIT_IN_MIN_7));
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w83781d_write_value(client, W83791D_REG_IN_MAX(7),
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IN_TO_REG(W83781D_INIT_IN_MAX_7));
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w83781d_write_value(client, W83791D_REG_IN_MIN(8),
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IN_TO_REG(W83781D_INIT_IN_MIN_8));
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w83781d_write_value(client, W83791D_REG_IN_MAX(8),
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IN_TO_REG(W83781D_INIT_IN_MAX_8));
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w83781d_write_value(client, W83791D_REG_IN_MIN(9),
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IN_TO_REG(W83781D_INIT_IN_MIN_9));
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w83781d_write_value(client, W83791D_REG_IN_MAX(9),
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IN_TO_REG(W83781D_INIT_IN_MAX_9));
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} else {
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w83781d_write_value(client, W83781D_REG_IN_MIN(0),
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IN_TO_REG(W83781D_INIT_IN_MIN_0));
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w83781d_write_value(client, W83781D_REG_IN_MAX(0),
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IN_TO_REG(W83781D_INIT_IN_MAX_0));
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if (type != w83783s && type != w83697hf) {
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w83781d_write_value(client, W83781D_REG_IN_MIN(1),
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IN_TO_REG(W83781D_INIT_IN_MIN_1));
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w83781d_write_value(client, W83781D_REG_IN_MAX(1),
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IN_TO_REG(W83781D_INIT_IN_MAX_1));
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}
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w83781d_write_value(client, W83781D_REG_IN_MIN(2),
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IN_TO_REG(W83781D_INIT_IN_MIN_2));
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w83781d_write_value(client, W83781D_REG_IN_MAX(2),
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IN_TO_REG(W83781D_INIT_IN_MAX_2));
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w83781d_write_value(client, W83781D_REG_IN_MIN(3),
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IN_TO_REG(W83781D_INIT_IN_MIN_3));
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w83781d_write_value(client, W83781D_REG_IN_MAX(3),
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IN_TO_REG(W83781D_INIT_IN_MAX_3));
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w83781d_write_value(client, W83781D_REG_IN_MIN(4),
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IN_TO_REG(W83781D_INIT_IN_MIN_4));
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w83781d_write_value(client, W83781D_REG_IN_MAX(4),
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IN_TO_REG(W83781D_INIT_IN_MAX_4));
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if (type == w83781d || type == as99127f) {
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w83781d_write_value(client, W83781D_REG_IN_MIN(5),
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IN_TO_REG(W83781D_INIT_IN_MIN_5));
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w83781d_write_value(client, W83781D_REG_IN_MAX(5),
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IN_TO_REG(W83781D_INIT_IN_MAX_5));
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} else {
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w83781d_write_value(client, W83781D_REG_IN_MIN(5),
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IN_TO_REG(W83782D_INIT_IN_MIN_5));
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w83781d_write_value(client, W83781D_REG_IN_MAX(5),
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IN_TO_REG(W83782D_INIT_IN_MAX_5));
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}
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if (type == w83781d || type == as99127f) {
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w83781d_write_value(client, W83781D_REG_IN_MIN(6),
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IN_TO_REG(W83781D_INIT_IN_MIN_6));
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w83781d_write_value(client, W83781D_REG_IN_MAX(6),
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IN_TO_REG(W83781D_INIT_IN_MAX_6));
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} else {
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w83781d_write_value(client, W83781D_REG_IN_MIN(6),
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IN_TO_REG(W83782D_INIT_IN_MIN_6));
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w83781d_write_value(client, W83781D_REG_IN_MAX(6),
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IN_TO_REG(W83782D_INIT_IN_MAX_6));
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}
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if ((type == w83782d) || (type == w83627hf) ||
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(type == w83697hf)) {
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w83781d_write_value(client, W83781D_REG_IN_MIN(7),
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IN_TO_REG(W83781D_INIT_IN_MIN_7));
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w83781d_write_value(client, W83781D_REG_IN_MAX(7),
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IN_TO_REG(W83781D_INIT_IN_MAX_7));
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w83781d_write_value(client, W83781D_REG_IN_MIN(8),
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IN_TO_REG(W83781D_INIT_IN_MIN_8));
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w83781d_write_value(client, W83781D_REG_IN_MAX(8),
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IN_TO_REG(W83781D_INIT_IN_MAX_8));
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w83781d_write_value(client, W83781D_REG_VBAT,
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(w83781d_read_value(client, W83781D_REG_VBAT) | 0x01));
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}
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}
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w83781d_write_value(client, W83781D_REG_FAN_MIN(1),
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FAN_TO_REG(W83781D_INIT_FAN_MIN_1, 2));
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w83781d_write_value(client, W83781D_REG_FAN_MIN(2),
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FAN_TO_REG(W83781D_INIT_FAN_MIN_2, 2));
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if (type != w83697hf) {
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w83781d_write_value(client, W83781D_REG_FAN_MIN(3),
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FAN_TO_REG(W83781D_INIT_FAN_MIN_3, 2));
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}
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w83781d_write_value(client, W83781D_REG_TEMP_OVER,
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TEMP_TO_REG(W83781D_INIT_TEMP_OVER));
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w83781d_write_value(client, W83781D_REG_TEMP_HYST,
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TEMP_TO_REG(W83781D_INIT_TEMP_HYST));
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if (type == as99127f) {
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w83781d_write_value(client, W83781D_REG_TEMP2_OVER,
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AS99127_TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP2_OVER));
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w83781d_write_value(client, W83781D_REG_TEMP2_HYST,
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AS99127_TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP2_HYST));
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} else {
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w83781d_write_value(client, W83781D_REG_TEMP2_OVER,
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TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP2_OVER));
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w83781d_write_value(client, W83781D_REG_TEMP2_HYST,
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TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP2_HYST));
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}
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w83781d_write_value(client, W83781D_REG_TEMP2_CONFIG, 0x00);
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if (type == as99127f) {
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w83781d_write_value(client, W83781D_REG_TEMP3_OVER,
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AS99127_TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP3_OVER));
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w83781d_write_value(client, W83781D_REG_TEMP3_HYST,
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AS99127_TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP3_HYST));
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} else if (type != w83783s && type != w83697hf) {
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w83781d_write_value(client, W83781D_REG_TEMP3_OVER,
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TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP3_OVER));
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w83781d_write_value(client, W83781D_REG_TEMP3_HYST,
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TEMP_ADD_TO_REG
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(W83781D_INIT_TEMP3_HYST));
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}
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if (type != w83783s && type != w83697hf) {
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w83781d_write_value(client, W83781D_REG_TEMP3_CONFIG,
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0x00);
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