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(Phil) Added some eeprom docs/tools and fixed some typos while I was at it.
git-svn-id: http://lm-sensors.org/svn/lm-sensors/trunk@79 7894878c-1315-0410-8ee3-d5d059ff63e0
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+83
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Some quick notes about the eeprom.o module and decode_dimms.pl.
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EEPROM Module
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-------------
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This is a simple EEPROM module meant to enable reading the first 128 bytes
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of an EEPROM (on a SDRAM DIMM). This module will probably need to be at
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least expanded. A /dev file interface would probably be more effective.
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This module was a programming exercise to get used to the new project
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organization laid out by Frodo, but it should be at least completely
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effective for decoding the contents of EEPROMs on DIMMs.
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Lacking functionality:
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* Read past byte 128. There is no technical restriction for not doing
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this, but making a zillion dataxx-xx files would be a bit rediculous.
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EEPROMs on DIMMs shouldn't use the contents past byte 128, so we are fine.
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* Enable Writing. Again, no technical reason why not, but making it easy
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to change the contents of the EEPROMs (on DIMMs anyway) also makes it easy
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to disable the DIMMs until the values are restored somehow.
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Use:
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After inserting the module (and any other required smbus/i2c modules), you
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should have some EEPROM directories in /proc/sys/dev/sensors/ of names such
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as "eeprom-i2c-0-50". Inside each of these is a series of files which
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represent 16 bytes blocks from the EEPROM. The data is in decimal (base
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10) delimited by spaces.
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Note:
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EEPROMs reported are not nessesarily all from DIMMs. Xeon processors, for
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example, have serial EEPROMs in them connected to the SMBus which will be
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found by the module. Take care to ignore the output of decode_dimms.pl for
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these EEPROMs.
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DECODE_DIMMS.PL
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---------------
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This Perl script attempts to make sense of the first 128 bytes of a SDRAM
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DIMM. Using the 'Serial Presence Detect (SPD)' Spec (Rev1.2a)** from
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Intel. When finished, it will decode and report all the values defined in
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the spec. Much of the information is technical timing and interfacing info
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(probably not all used by the Bios or clocking IC.
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Note: During testing, we noticed that many DIMMs have trucated SPD records.
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I'm not sure if these conform to an old spec, or if the manufacturers are
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simply just taking short-cuts. But, many DIMMs have all zeros stored past
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byte 21. I asked an Intel SDRAM tester, Sat Kolli (skolli@smartm.com),
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about this and this is what he had to say:
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"[...] Now in terms of SPD contents, you are right that people do all kinds
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of things. The way to insure that any module works is to look for the most
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basic information, such as module bank density, number of banks, and device
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addresses. That will give you the module size and what devices are used. It
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is very difficult to verify if the module is PC-100, because of
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inconsistencies between spd data from different manufacturers. You could
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read the timing information or the special Intel bytes (126 & 127) but I do
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not know how many program that information.These inconsistencies may be
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minimized if you or your customers stay with some of the better known
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manufacturers." (Thanks goes to Sat Kolli for his comments and help)
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Use:
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After inserting the nessesary modules, run the script!
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Notes:
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The script assumes that Perl can be found at /usr/bin/perl. If different,
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you will need to adjust the first line of the file accordingly, or else
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you will get a strange "decode_dimms.pl: no such file or directory" error.
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Also note that the script assumes that _all_ the eeproms belong to DIMMs,
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which may not be the case.
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------------------------------------------------------------------------
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** PDF is available from Intel or our web site:
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http://www.netroedge.com/~lm78
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"eeprom" doc created Dec. 14, 1998 by Philip Edelbrock
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@@ -1,6 +1,6 @@
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The PIIX4 (properly known as the 82371AB) is an Intel chip with a lot of
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functionality. Among other things, it implements the PCI bus. One of its
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minor functions is implementing a System Management MBus. This is a true
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minor functions is implementing a System Management Bus. This is a true
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SMBus - you can not access it on I2C levels. The good news is that it
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natively understands SMBus commands and you do not have to worry about
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timing problems. The bad news is that non-SMBus devices connected to it
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@@ -286,7 +286,7 @@ void eeprom_update_client(struct i2c_client *client)
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#endif
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}
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for (i=0;i<EEPROM_SIZE;i++) {
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data->data[i] = (u8)smbus_read_byte(client->adapter,client->addr);
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data->data[i] = (u8)smbus_read_byte(client->adapter,client->addr);
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}
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data->last_updated = jiffies;
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Executable
+293
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#!/usr/bin/perl
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#
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# Copyright 1998, Philip Edelbrock <phil@netroedge.com>
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#
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# Version 0.2
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#
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# EEPROM data decoding for SDRAM DIMM modules.
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#
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# Two assumptions: lm_sensors-2.0.2 installed,
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# and Perl is at /usr/bin/perl
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#
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#
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# Reference: PC SDRAM Serial Presence
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# Detect (SPD) Specification, Intel,
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# Dec '97, Rev 1.2A
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#
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print "SDRAM Serial Presence Detect Tester/Decoder\n";
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print "Written by Philip Edelbrock. Copyright 1998.\n";
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print "Version 0.2\n\n";
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$dimm_count=0;
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$_=`ls /proc/sys/dev/sensors/`;
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@dimm_list=split();
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for $i ( 0 .. $#dimm_list ) {
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$_=$dimm_list[$i];
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if (/^eeprom-/) {
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$dimm_count=$dimm_count + 1;
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print "\nDecoding EEPROM: /proc/sys/dev/sensors/$dimm_list[$i]\n";
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if (/^[^-]+-[^-]+-[^-]+-([^-]+)$/) {
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$dimm_num=$1 - 49;
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print "Guessing DIMM is in bank $dimm_num\n";
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}
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# Decode first 16 bytes
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print "\t\t----=== The Following is Required Data and is Applicable to all DIMM Types ===----\n";
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$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data0-15`;
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@bytes=split(" ");
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print "\t# of bytes written to SDRAM EEPROM:\t\t$bytes[0]\n";
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print "\tTotal number of bytes in EEPROM:\t\t";
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if ($bytes[1] < 13) {
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print 2**$bytes[1];
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print "\n";
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} elsif ($bytes[1] == 0) {
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print "RFU\n";
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} else { print "ERROR!\n"; }
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print "\tFundemental Memory type:\t\t\t";
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if ($bytes[2] == 2) { print "EDO\n"; } elsif ($bytes[2] == 4) { print "SDRAM\n";
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} else { print "???\n"; }
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print "\tNumber of Row Address Bits (SDRAM only):\t";
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if ($bytes[3] == 0) { print "Undefined!\n" }
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elsif ($bytes[3] == 1) { print "1/16\n" }
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elsif ($bytes[3] == 2) { print "2/17\n" }
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elsif ($bytes[3] == 3) { print "3/18\n" }
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else { print $bytes[3]; print "\n"; }
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print "\tNumber of Col Address Bits (SDRAM only):\t";
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if ($bytes[4] == 0) { print "Undefined!\n" }
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elsif ($bytes[4] == 1) { print "1/16\n" }
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elsif ($bytes[4] == 2) { print "2/17\n" }
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elsif ($bytes[4] == 3) { print "3/18\n" }
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else { print $bytes[4]; print "\n"; }
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print "\tNumber of Module Rows:\t\t\t\t";
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if ($bytes[5] == 0 ) { print "Undefined!\n"; } else { print $bytes[5]; print "\n"; }
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print "\tData Width (SDRAM only):\t\t\t";
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if ($bytes[7] > 1) { print "Undefined!\n" } else {
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$temp=($bytes[7]*256) + $bytes[6];
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print $temp; print "\n"; }
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print "\tModule Interface Signal Levels:\t\t\t";
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if ($bytes[8] == 0) { print "5.0 Volt/TTL\n";} elsif ($bytes[8] == 1) {
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print "LVTTL\n";} elsif ($bytes[8] == 2) { print "HSTL 1.5\n";} elsif ($bytes[8] == 3) {
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print "SSTL 3.3\n";} elsif ($bytes[8] == 4) { print "SSTL 2.5\n";} else { print "Undefined!\n";}
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print "\tCycle Time (SDRAM):\t\t\t\t";
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$temp=($bytes[9] >> 4) + (($bytes[9] - (($bytes[9] >> 4)<< 4)) * 0.1);
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print $temp; print "ns\n";
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print "\tAccess Time (SDRAM):\t\t\t\t";
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$temp=($bytes[10] >> 4) + (($bytes[10] - (($bytes[10] >> 4)<< 4)) * 0.1);
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print $temp; print "ns\n";
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print "\tModule Configuration Type:\t\t\t";
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if ($bytes[11] == 0) { print "No Parity\n"; } elsif ($bytes[11] == 1) { print "Parity\n";
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} elsif ($bytes[11] == 2) { print "ECC\n"; } else { print "Undefined!"; }
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print "\tRefresh Type:\t\t\t\t\t";
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if ($bytes[12] > 126) { print "Self Refreshing\n"; $temp=$bytes[12] - 127;
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} else { print "Not Self Refreshing\n"; $temp=$bytes[12];}
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print "\tRefresh Rate:\t\t\t\t\t";
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if ($temp == 0) { print "Normal (15.625uS)\n"; } elsif ($temp == 1) { print "Reduced (3.9uS)\n";
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} elsif ($temp == 2) { print "Reduced (7.8uS)\n"; } elsif ($temp == 3) { print "Extended (31.3uS)\n";
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} elsif ($temp == 4) { print "Extended (62.5uS)\n"; } elsif ($temp == 5) { print "Extended (125uS)\n";
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} else { print "Undefined!";}
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print "\tPrimary SDRAM Component Bank Config:\t\t";
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if ($bytes[13]>126) {$temp=$bytes[13]-127; print "Bank2 = 2 x Bank1\n";} else {
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$temp=$bytes[13]; print "No Bank2 OR Bank2 = Bank1 width\n";}
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print "\tPrimary SDRAM Component Widths:\t\t\t";
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if ($temp == 0) { print "Undefined!\n"; } else { print "$temp\n"; }
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print "\tError Checking SDRAM Component Bank Config:\t";
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if ($bytes[14]>126) {$temp=$bytes[14]-127; print "Bank2 = 2 x Bank1\n";} else {
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$temp=$bytes[14]; print "No Bank2 OR Bank2 = Bank1 width\n";}
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print "\tError Checking SDRAM Component Widths:\t\t";
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if ($temp == 0) { print "Undefined!\n"; } else { print "$temp\n"; }
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print "\tMin Clock Delay for Back to Back Random Access:\t";
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if ($bytes[15] == 0) { print "Undefined!\n"; } else { print "$bytes[15]\n"; }
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print "\t\t----=== The Following Apply to SDRAM DIMMs ONLY ===----\n";
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# Decode next 16 bytes
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$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data16-31`;
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@bytes=split(" ");
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print "\tBurst lengths supported:\t\t\t";
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$temp="";
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if (($bytes[0] & 1) > 0) { print "${temp}Burst Length = 1\n"; $temp="\t\t\t\t\t\t\t";}
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if (($bytes[0] & 2) > 0) { print "${temp}Burst Length = 2\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[0] & 4) > 0) { print "${temp}Burst Length = 4\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[0] & 8) > 0) { print "${temp}Burst Length = 8\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[0] & 16) > 0) { print "${temp}Undefined! (bit 4)\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[0] & 32) > 0) { print "${temp}Undefined! (bit 5)\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[0] & 64) > 0) { print "${temp}Undefined! (bit 6)\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[0] & 128) > 0) { print "${temp}Burst Length = Page\n"; $temp="\t\t\t\t\t\t\t"; }
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if ($bytes[0] == 0) { print "(None Supported)\n";}
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print "\tNumber of Device Banks:\t\t\t\t";
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if ($bytes[1] == 0) { print "Undefined/Reserved!\n"; } else { print "$bytes[1]\n"; }
|
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|
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print "\tSupported CAS Latencies:\t\t\t";
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$temp="";
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if (($bytes[2] & 1) > 0) { print "${temp}CAS Latency = 1\n"; $temp="\t\t\t\t\t\t\t";}
|
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if (($bytes[2] & 2) > 0) { print "${temp}CAS Latency = 2\n"; $temp="\t\t\t\t\t\t\t"; }
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if (($bytes[2] & 4) > 0) { print "${temp}CAS Latency = 3\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[2] & 8) > 0) { print "${temp}CAS Latency = 4\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[2] & 16) > 0) { print "${temp}CAS Latency = 5\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[2] & 32) > 0) { print "${temp}CAS Latency = 6\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[2] & 64) > 0) { print "${temp}CAS Latency = 7\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[2] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if ($bytes[2] == 0) { print "(None Supported)\n";}
|
||||
|
||||
print "\tSupported CS Latencies:\t\t\t\t";
|
||||
$temp="";
|
||||
if (($bytes[3] & 1) > 0) { print "${temp}CS Latency = 0\n"; $temp="\t\t\t\t\t\t\t";}
|
||||
if (($bytes[3] & 2) > 0) { print "${temp}CS Latency = 1\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[3] & 4) > 0) { print "${temp}CS Latency = 2\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[3] & 8) > 0) { print "${temp}CS Latency = 3\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[3] & 16) > 0) { print "${temp}CS Latency = 4\n"; $temp="\t\t\t\t\t\t\t"; }
|
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if (($bytes[3] & 32) > 0) { print "${temp}CS Latency = 5\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[3] & 64) > 0) { print "${temp}CS Latency = 6\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[3] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if ($bytes[3] == 0) { print "(None Supported)\n";}
|
||||
|
||||
print "\tSupported WE Latencies:\t\t\t\t";
|
||||
$temp="";
|
||||
if (($bytes[4] & 1) > 0) { print "${temp}WE Latency = 0\n"; $temp="\t\t\t\t\t\t\t";}
|
||||
if (($bytes[4] & 2) > 0) { print "${temp}WE Latency = 1\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[4] & 4) > 0) { print "${temp}WE Latency = 2\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[4] & 8) > 0) { print "${temp}WE Latency = 3\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[4] & 16) > 0) { print "${temp}WE Latency = 4\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[4] & 32) > 0) { print "${temp}WE Latency = 5\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[4] & 64) > 0) { print "${temp}WE Latency = 6\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[4] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if ($bytes[4] == 0) { print "(None Supported)\n";}
|
||||
|
||||
print "\tSDRAM Module Attributes:\t\t\t";
|
||||
$temp="";
|
||||
if (($bytes[5] & 1) > 0) { print "${temp}Buffered Address/Control Inputs\n"; $temp="\t\t\t\t\t\t\t";}
|
||||
if (($bytes[5] & 2) > 0) { print "${temp}Registered Address/Control Inputs\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[5] & 4) > 0) { print "${temp}On card PLL (clock)\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[5] & 8) > 0) { print "${temp}Buffered DQMB Inputs\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[5] & 16) > 0) { print "${temp}Registered DQMB Inputs\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[5] & 32) > 0) { print "${temp}Differential Clock Input\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[5] & 64) > 0) { print "${temp}Redundant Row Address\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[5] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if ($bytes[5] == 0) { print "(None Reported)\n";}
|
||||
|
||||
print "\tSDRAM Device Attributes (General):\t\t";
|
||||
$temp="";
|
||||
if (($bytes[6] & 1) > 0) { print "${temp}Supports Early RAS# Recharge\n"; $temp="\t\t\t\t\t\t\t";}
|
||||
if (($bytes[6] & 2) > 0) { print "${temp}Supports Auto-Precharge\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 4) > 0) { print "${temp}Supports Precharge All\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 8) > 0) { print "${temp}Supports Write1/Read Burst\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 16) > 0) { print "${temp}Lower VCC Tolerance:5%\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 16) == 0) { print "${temp}Lower VCC Tolerance:10%\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 32) > 0) { print "${temp}Upper VCC Tolerance:5%\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 32) == 0) { print "${temp}Upper VCC Tolerance:10%\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 64) > 0) { print "${temp}Undefined (bit 6)\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[6] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
|
||||
print "\tSDRAM Cycle Time (2ns highest CAS):\t\t";
|
||||
$temp=$bytes[7] >> 4;
|
||||
if ($temp == 0) { print "Undefined!\n"; } else {
|
||||
if ($temp < 4 ) {$temp=$temp + 15;}
|
||||
print $temp + (($bytes[7] & 15) / 10);
|
||||
print "nS\n";
|
||||
}
|
||||
|
||||
print "\tSDRAM Access from Clock Time (2nd highest CAS):\t";
|
||||
$temp=$bytes[8] >> 4;
|
||||
if ($temp == 0) { print "Undefined!\n"; } else {
|
||||
if ($temp < 4 ) {$temp=$temp + 15;}
|
||||
print $temp + (($bytes[8] & 15) / 10.0);
|
||||
print "nS\n";
|
||||
}
|
||||
|
||||
print "\t\t----=== The Following are Optional (may be Bogus) ===----\n";
|
||||
|
||||
print "\tSDRAM Cycle Time (3rd highest CAS):\t\t";
|
||||
$temp=$bytes[9] >> 2;
|
||||
if ($temp == 0) { print "Undefined!\n"; } else {
|
||||
print $temp + (($bytes[9] & 3) / 4.0);
|
||||
print "nS\n";
|
||||
}
|
||||
|
||||
print "\tSDRAM Access from Clock Time (3rd highest CAS):\t";
|
||||
$temp=$bytes[10] >> 2;
|
||||
if ($temp == 0) { print "Undefined!\n"; } else {
|
||||
print $temp + (($bytes[10] & 3) / 4.0);
|
||||
print "nS\n";
|
||||
}
|
||||
|
||||
print "\t\t----=== The Following are Required (for SDRAMs) ===----\n";
|
||||
|
||||
print "\tMinumum Row Precharge Time:\t\t\t";
|
||||
if ($bytes[11] == 0) { print "Undefined!\n"; } else { print "$bytes[11]nS\n"; }
|
||||
|
||||
print "\tRow Active to Row Active Min:\t\t\t";
|
||||
if ($bytes[12] == 0) { print "Undefined!\n"; } else { print "$bytes[12]nS\n"; }
|
||||
|
||||
print "\tRAS to CAS Delay:\t\t\t\t";
|
||||
if ($bytes[13] == 0) { print "Undefined!\n"; } else { print "$bytes[13]nS\n"; }
|
||||
|
||||
print "\tMin RAS Pulse Width:\t\t\t\t";
|
||||
if ($bytes[14] == 0) { print "Undefined!\n"; } else { print "$bytes[14]nS\n"; }
|
||||
|
||||
|
||||
print "\t\t----=== The Following are Required and Apply to ALL DIMMs ===----\n";
|
||||
|
||||
print "\tRow Densities:\t\t\t\t\t";
|
||||
$temp="";
|
||||
if (($bytes[15] & 1) > 0) { print "${temp}4 MByte\n"; $temp="\t\t\t\t\t\t\t";}
|
||||
if (($bytes[15] & 2) > 0) { print "${temp}8 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[15] & 4) > 0) { print "${temp}16 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[15] & 8) > 0) { print "${temp}32 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[15] & 16) > 0) { print "${temp}64 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[15] & 32) > 0) { print "${temp}128 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[15] & 64) > 0) { print "${temp}256 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if (($bytes[15] & 128) > 0) { print "${temp}512 MByte\n"; $temp="\t\t\t\t\t\t\t"; }
|
||||
if ($bytes[15] == 0) { print "(Undefined! -- None Reported!)\n";}
|
||||
|
||||
|
||||
# Decode next 16 bytes (32-47)
|
||||
$_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data32-47`;
|
||||
@bytes=split(" ");
|
||||
|
||||
print "\tCommand and Address Signal Setup Time:\t\t";
|
||||
if ($bytes[0] > 127) { $temp=($bytes[0]-128)>>4; $temp2=-1; } else { $temp=$bytes[0]>>4; $temp2=1;}
|
||||
print $temp2 * ($temp + (($bytes[0] & 15) / 10.0));
|
||||
print "nS\n";
|
||||
|
||||
print "\tCommand and Address Signal Hold Time:\t\t";
|
||||
if ($bytes[1] > 127) { $temp=($bytes[1]-128)>>4; $temp2=-1; } else { $temp=$bytes[1]>>4; $temp2=1;}
|
||||
print $temp2 * ($temp + (($bytes[1] & 15) / 10.0));
|
||||
print "nS\n";
|
||||
|
||||
print "\tData Signal Setup Time:\t\t\t\t";
|
||||
if ($bytes[2] > 127) { $temp=($bytes[2]-128)>>4; $temp2=-1; } else { $temp=$bytes[2]>>4; $temp2=1;}
|
||||
print $temp2 * ($temp + (($bytes[2] & 15) / 10.0));
|
||||
print "nS\n";
|
||||
|
||||
print "\tData Signal Hold Time:\t\t\t\t";
|
||||
if ($bytes[3] > 127) { $temp=($bytes[3]-128)>>4; $temp2=-1; } else { $temp=$bytes[3]>>4; $temp2=1;}
|
||||
print $temp2 * ($temp + (($bytes[3] & 15) / 10.0));
|
||||
print "nS\n";
|
||||
|
||||
# That's it for the lower part of an SDRAM EEPROM's memory!
|
||||
|
||||
}
|
||||
}
|
||||
print "\n\nNumber of SDRAM DIMMs detected and decoded: $dimm_count\n";
|
||||
+1
-1
@@ -286,7 +286,7 @@ void eeprom_update_client(struct i2c_client *client)
|
||||
#endif
|
||||
}
|
||||
for (i=0;i<EEPROM_SIZE;i++) {
|
||||
data->data[i] = (u8)smbus_read_byte(client->adapter,client->addr);
|
||||
data->data[i] = (u8)smbus_read_byte(client->adapter,client->addr);
|
||||
}
|
||||
|
||||
data->last_updated = jiffies;
|
||||
|
||||
Reference in new issue
Block a user