fix mg_send() failing on 0 length

Fix 2-way auth max msg size, + some neats

.github/ISSUE_TEMPLATE/config.yml

@@ -0,0 +1 @@
+blank_issues_enabled: false

.github/ISSUE_TEMPLATE/issue.md

@@ -1,3 +1,11 @@
+---
+name: Issue template
+about: Please fill this issue template for reporting Mongoose issues
+#title: 
+#labels: 
+#assignees: 
+---
+
 - My goal is: _describe_
 - My actions were: _describe_
 - My expectation was: _describe_

.github/workflows/cifuzz.yml

@@ -11,17 +11,14 @@ jobs:
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: if ./test/match_changed_files.sh '^src/' ; then echo GO=1 >> $GITHUB_ENV ; fi
     - name: Build Fuzzers
       id: build
-      if: ${{ env.GO == 1 }}
       uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master
       with:
         oss-fuzz-project-name: 'mongoose'
         dry-run: false
         language: c++
     - name: Run Fuzzers
-      if: ${{ env.GO == 1 }}
       uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master
       with:
         oss-fuzz-project-name: 'mongoose'
@@ -30,7 +27,7 @@ jobs:
         language: c++
     - name: Upload Crash
       uses: actions/upload-artifact@v4
-      if: env.GO == 1 && failure() && steps.build.outcome == 'success'
+      if: failure() && steps.build.outcome == 'success'
       with:
         name: artifacts
         path: ./out/artifacts

.github/workflows/codeql.yml

@@ -2,8 +2,8 @@ name: "CodeQL Scanning"
 # https://github.com/github/codeql-action
 
 on:
-  schedule:
-    - cron: '30 2 * * *' # run at 2:30 AM UTC
+  #schedule:
+  #  - cron: '30 23 * * *' # run at 11:30 PM UTC
   # Allow manual runs
   workflow_dispatch:
 

.github/workflows/fuzz.yml

@@ -0,0 +1,24 @@
+name: Fuzz
+on:
+  schedule:
+    - cron: '0 21 * * *' # run at 9 PM UTC
+  # Allow manual runs
+  workflow_dispatch:
+env:
+  CC: clang
+jobs:
+  fuzz:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        target: [fuzz, fuzz_tls]
+    name: ${{ matrix.target }}
+    steps:
+    - uses: actions/checkout@v4
+      with: { fetch-depth: 2 }
+    - run: make -C test ${{ matrix.target }} ARGS="-max_total_time=7200"
+
+# as we're not getting access to test units causing a problem, convert from the log:
+# base64 -d > dataofdeath
+# then paste the base64 data, enter, Ctrl-D; maybe check with hexdump -C dataofdeath

.github/workflows/nightly.yml

@@ -1,7 +1,7 @@
 name: Full build and test
 on:
   schedule:
-    - cron: '0 1 * * *' # run at 1 AM UTC
+    - cron: '0 22 * * *' # run at 10 PM UTC
   # Allow manual runs
   workflow_dispatch:
 env:
@@ -33,11 +33,19 @@ jobs:
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
-      TFLAGS: ${{ matrix.select }}
+      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST -DNO_ABORT
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }}
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/linux_${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
   mip:
     runs-on: ubuntu-latest
     strategy:
@@ -46,14 +54,40 @@ jobs:
         cc: [gcc, clang, g++, clang++]
         target: [mip_test, mip_tap_test]
         ssl: ["", BUILTIN, MBEDTLS, OPENSSL, WOLFSSL]
+        # #3226: built-in TCP is currently not working with WolfSSL (builds fine)
+        exclude:
+        - ssl: WOLFSSL
+          target: mip_tap_test
     name: ${{ matrix.target }} CC=${{ matrix.cc }} SSL=${{ matrix.ssl }}
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
+      TFLAGS: -DMQTT_LOCALHOST -DNO_ABORT
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: if [ "${{ matrix.target }}" == "mip_tap_test" ]; then ./test/setup_ga_network.sh ; fi && sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }} IPV6=0
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: if [ "${{ matrix.target }}" == "mip_tap_test" ]; then ./test/setup_ga_network.sh ; fi && sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev && make -C test ${{ matrix.target }} IPV6=0 > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_$(date +"%Y%m%d").json"
+
+  mip89:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      max-parallel: 1   # no parallel runs, to minimize MQTT errors
+      matrix:
+        target: [mip_vc98]
+    name: mip89 ${{ matrix.target }}
+    steps:
+    - uses: actions/checkout@v4
+      with: { fetch-depth: 2 }
+    - run: make -C test ${{ matrix.target }} 
   s390:
     runs-on: ubuntu-latest
     strategy:
@@ -61,10 +95,12 @@ jobs:
       matrix:
         ssl: ["", BUILTIN]
     name: S390 SSL=${{ matrix.ssl }}
+    env:
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: sudo apt -y update ; sudo apt -y install qemu binfmt-support qemu-user-static && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test s390 SSL=${{ matrix.ssl }}
+    - run: sudo apt -y update ; sudo apt -y install binfmt-support qemu-user-static && ./test/setup_mqtt_server.sh && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test s390 SSL=${{ matrix.ssl }} MULTIREC=NO
   armhf:
     runs-on: ubuntu-latest
     strategy:
@@ -72,10 +108,12 @@ jobs:
       matrix:
         ssl: ["", BUILTIN]
     name: ArmHF SSL=${{ matrix.ssl }}
+    env:
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: sudo apt -y update ; sudo apt -y install qemu binfmt-support qemu-user-static && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test armhf SSL=${{ matrix.ssl }}
+    - run: sudo apt -y update ; sudo apt -y install binfmt-support qemu-user-static && ./test/setup_mqtt_server.sh && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test armhf SSL=${{ matrix.ssl }} MULTIREC=NO
   unamalgamated-mg_prefix:
     runs-on: ubuntu-latest
     strategy:
@@ -87,7 +125,7 @@ jobs:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev
-    - run: make -C test unamalgamated && make -C test mg_prefix
+    - run: make -C test unamalgamated SSL=${{ matrix.ssl }} && make -C test mg_prefix
   valgrind:
     runs-on: ubuntu-latest
     strategy:
@@ -95,35 +133,53 @@ jobs:
       matrix:
         ssl: ["", BUILTIN, MBEDTLS, OPENSSL, WOLFSSL]
     name: Valgrind SSL=${{ matrix.ssl }}
+    env:
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: sudo apt -y update ; sudo apt -y install libmbedtls-dev libwolfssl-dev valgrind
-    - run: make -C test valgrind SSL=${{ matrix.ssl }}
+    - run: ./test/setup_mqtt_server.sh && make -C test valgrind SSL=${{ matrix.ssl }}
   macos:
     runs-on: macos-latest
     strategy:
       fail-fast: false
       matrix:
-        ssl: ["", BUILTIN, MBEDTLS, OPENSSL, WOLFSSL]
+        # Mongoose does not work with WolfSSL version in MacOS
+        ssl: ["", BUILTIN, MBEDTLS, OPENSSL] # , WOLFSSL]
         select: [-DMG_ENABLE_POLL=0, -DMG_ENABLE_POLL=1]
+        include:
+        - ssl: MBEDTLS
+          env:
+            # MbedTLS version in MacOS refuses to validate a certificate without a hostname, causing MQTT tests to fail when using MQTT_LOCALHOST
+            tflags: -DNO_MQTT_TESTS 
         exclude:
         - ssl: MBEDTLS
           select: -DMG_ENABLE_POLL=0
         - ssl: OPENSSL
           select: -DMG_ENABLE_POLL=0
-        - ssl: WOLFSSL
-          select: -DMG_ENABLE_POLL=0
+        #- ssl: WOLFSSL
+        #  select: -DMG_ENABLE_POLL=0
     name: macos SSL=${{ matrix.ssl }} TFLAGS=${{ matrix.select }}
     env:
       SSL: ${{ matrix.ssl }}
-      TFLAGS: ${{ matrix.select }} -DNO_SNTP_CHECK -Wno-sign-conversion # Workaround for MbedTLS 3.5.0
+      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST ${{ matrix.env.tflags }} -Wno-sign-conversion # Workaround for MbedTLS 3.5.0
       HOMEBREW_NO_AUTO_UPDATE: 1
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: brew install mbedtls wolfssl # jq openssl already pre-installed
-    - run: make -C test test ASAN_OPTIONS= MBEDTLS=$(echo $(brew --cellar)/mbedtls*/*) OPENSSL=$(echo $(brew --cellar)/openssl*/*) WOLFSSL=$(echo $(brew --cellar)/wolfssl*/*)
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: brew install mbedtls wolfssl mosquitto gawk # jq openssl already pre-installed
+    - run: /opt/homebrew/opt/mosquitto/sbin/mosquitto -c /Users/runner/work/mongoose/mongoose/test/mosquitto.conf.macos &
+    - run: make -C test test ASAN_OPTIONS= MBEDTLS=$(echo $(brew --cellar)/mbedtls*/*) OPENSSL=$(echo $(brew --cellar)/openssl*/*) WOLFSSL=$(echo $(brew --cellar)/wolfssl*/*) > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/macos_test_cc_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
+
   windows:
     runs-on: ubuntu-latest
     strategy:
@@ -138,12 +194,21 @@ jobs:
           select: -DMG_ENABLE_POLL=1
     name: windows ${{ matrix.target }} SSL=${{ matrix.ssl }} TFLAGS=${{ matrix.select }}
     env:
-      SSL: SSL=${{ matrix.ssl }}
-      TFLAGS: ${{ matrix.select }}
+      SSL: ${{ matrix.ssl }}
+      TFLAGS: ${{ matrix.select }} -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
-    - run: make -C test ${{ matrix.target }} 
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
+    - run: ./test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/windows_${{ matrix.target }}_${{ matrix.cc }}_${{ matrix.ssl }}_${{ matrix.select }}_$(date +"%Y%m%d").json"
+ 
   arm:
     runs-on: ubuntu-latest
     strategy:
@@ -165,109 +230,33 @@ jobs:
     - uses: actions/checkout@v4
     - run: make -C test riscv SSL=${{ matrix.ssl }}
 
-  examples:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
-    name: examples ${{ matrix.ssl }}
-    steps:
-    - uses: actions/checkout@v4
-    - run: sudo apt -y install libpcap-dev
-    - run: make -C test examples CFLAGS_EXTRA="${{ matrix.ssl }}"
-    - run: make -C test clean_examples
-  examples_win:
-    runs-on: windows-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
-    name: examples_win ${{ matrix.ssl }}
-    steps:
-    - uses: actions/checkout@v4
-#    - uses: egor-tensin/setup-mingw@v2
-#      with:
-#        platform: x64
-    - name: test they build
-      run: make -C test examples_win CFLAGS_EXTRA="${{ matrix.ssl }}"
-      shell: cmd
-    - name: test they clean
-      run: make -C test clean_examples_win
-      shell: cmd
-  examples_mac:
-    runs-on: macos-latest
-    env: { HOMEBREW_NO_AUTO_UPDATE: 1 }
-    strategy:
-      fail-fast: false
-      matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
-    name: examples_mac ${{ matrix.ssl }}
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test examples_mac CFLAGS_EXTRA="${{ matrix.ssl }}"
-    - run: make -C test clean_examples_mac
-
-  refprojs:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
-    name: reference-projects ${{ matrix.ssl }}
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test refprojs CFLAGS_EXTRA="${{ matrix.ssl }}"
-    - run: make -C test clean_refprojs
-  refprojs_win:
-    runs-on: windows-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
-    name: reference-projects_win ${{ matrix.ssl }}
-    steps:
-    - uses: actions/checkout@v4
-#    - uses: egor-tensin/setup-mingw@v2
-#      with:
-#        platform: x64
-    - name: test they build
-      run: make -C test refprojs_win CFLAGS_EXTRA="${{ matrix.ssl }}"
-      shell: cmd
-    - name: test they clean
-      run: make -C test clean_refprojs_win
-      shell: cmd
-  refprojs_mac:
-    runs-on: macos-latest
-    env: { HOMEBREW_NO_AUTO_UPDATE: 1 }
-    strategy:
-      fail-fast: false
-      matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
-    name: reference-projects_mac ${{ matrix.ssl }}
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test refprojs CFLAGS_EXTRA="${{ matrix.ssl }}"
-    - run: make -C test clean_refprojs
-
   tutorials:
     runs-on: ubuntu-latest
     strategy:
       fail-fast: false
       matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
+        ssl: [-DMG_TLS=MG_TLS_NONE, -DMG_TLS=MG_TLS_BUILTIN]
     name: tutorials ${{ matrix.ssl }}
     steps:
     - uses: actions/checkout@v4
+    - uses: webfactory/ssh-agent@v0.9.1
+      with:
+            ssh-private-key: ${{ secrets.HEALTH_TESTS_SSH_KEY }}
     - run: sudo apt -y install libpcap-dev
-    - run: make -C test tutorials CFLAGS_EXTRA="${{ matrix.ssl }}"
+    - run: make -C test tutorials CFLAGS_EXTRA="${{ matrix.ssl }}" > log
+    - if: success() || failure()
+      run: |
+        cat log
+        test/health.awk < log > json
+        scp -o "StrictHostKeyChecking=no" json "root@176.9.217.245:/data/downloads/health/tutorials_${{ matrix.ssl }}_$(date +"%Y%m%d").json"
     - run: make -C test clean_tutorials
+
   tutorials_win:
     runs-on: windows-latest
     strategy:
       fail-fast: false
       matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
+        ssl: [-DMG_TLS=MG_TLS_NONE, -DMG_TLS=MG_TLS_BUILTIN]
     name: tutorials_win ${{ matrix.ssl }}
     steps:
     - uses: actions/checkout@v4
@@ -286,7 +275,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
+        ssl: [-DMG_TLS=MG_TLS_NONE, -DMG_TLS=MG_TLS_BUILTIN]
     name: tutorials_mac ${{ matrix.ssl }}
     steps:
     - uses: actions/checkout@v4
@@ -300,9 +289,8 @@ jobs:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: echo # nothing specific to install or do
-    - run: make -C examples/arduino arduino-xiao
-#   - run: make -C examples/arduino arduino-nano
-    - run: make -C examples/arduino clean
+    - run: make -C test/arduino
+    - run: make -C test/arduino cleanall
 
 
 #  wizard_examples:
@@ -320,7 +308,7 @@ jobs:
 #        with: { fetch-depth: 2 }
 #      - run: echo # nothing specific to install or do
 #          fi
-#      - run: make -C examples/${{ matrix.example.path }} build
+#      - run: make -C tutorials/${{ matrix.example.path }} build
 
   wizard_examples_arm:
     runs-on: ubuntu-latest
@@ -328,11 +316,18 @@ jobs:
       fail-fast: false
       matrix:
         example:
+          - path: infineon/xmc47_relax-make-baremetal-builtin
+          - path: infineon/xmc_plt2go_4400-make-baremetal-builtin
+          - path: infineon/xmc72_evk-make-baremetal-builtin
           - path: nxp/frdm-mcxn947-make-baremetal-builtin
           - path: nxp/frdm-mcxn947-make-freertos-builtin
           - path: nxp/rt1020-evk-make-baremetal-builtin
           - path: nxp/rt1060-evk-make-baremetal-builtin
           - path: nxp/rt1170-evk-make-baremetal-builtin
+          - path: pico-sdk/pico-w-picosdk-baremetal-builtin
+          - path: pico-sdk/pico-2-w-picosdk-baremetal-builtin
+          - path: pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin
+          - path: pico-sdk/w5500-evb-pico2-picosdk-baremetal-builtin
           - path: stm32/nucleo-f429zi-make-baremetal-builtin
           - path: stm32/nucleo-f429zi-make-freertos-builtin
           - path: stm32/nucleo-f746zg-make-baremetal-builtin
@@ -354,7 +349,7 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-      - run: make -C examples/${{ matrix.example.path }} build
+      - run: make -C tutorials/${{ matrix.example.path }} build
 
 
   generic_examples:
@@ -363,9 +358,9 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: esp32/uart-bridge
-          - path: esp32/micropython
-          - path: esp8266/http-client-server
+          - path: micropython/esp32
+          - path: http/uart-bridge/esp32
+          - path: http/http-client/esp8266/http-client-server
     name: ${{ matrix.example.path }}
     env:
       GO: 0
@@ -373,7 +368,7 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: echo # nothing specific to install or do
-      - run: make -C examples/${{ matrix.example.path }} build
+      - run: make -C tutorials/${{ matrix.example.path }} build
   
   generic_examples_arm:
     runs-on: ubuntu-latest
@@ -381,9 +376,7 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: microchip/same54-xpro/mqtt-client
-          - path: infineon/infineon-xmc4700_4800-lwip-rtx-rtos
-          - path: nxp/nxp-mimxrt1020-azurertos
+          - path: mqtt/mqtt-client/microchip/same54-xpro
           - path: nxp/nxp-frdmk66f-freertos
           - path: nxp/nxp-lpcxpresso54s018m-freertos
           - path: nxp/nxp-mimxrt1020-freertos
@@ -413,7 +406,7 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-      - run: make -C examples/${{ matrix.example.path }} build
+      - run: make -C tutorials/${{ matrix.example.path }} build
 
   device_dashboard_examples:
     runs-on: ubuntu-latest
@@ -421,13 +414,14 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: esp32/device-dashboard
+          - path: esp32
     name: ${{ matrix.example.path }}
     steps:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: echo # nothing specific to install or do
-      - run: make -C examples/${{ matrix.example.path }} build
+      - run: make -C tutorials/http/device-dashboard/${{ matrix.example.path }} build
+
 
   device_dashboard_examples_arm:
     runs-on: ubuntu-latest
@@ -436,16 +430,14 @@ jobs:
       matrix:
         ssl: ["", -DMG_TLS=MG_TLS_BUILTIN]
         example:
-          - path: infineon/infineon-xmc7200
-          - path: microchip/same54-xpro/device-dashboard
+          - path: http/device-dashboard/microchip/same54-xpro
           - path: nxp/rt1020-evk-make-freertos-builtin
           - path: nxp/rt1060-evk-make-freertos-builtin
           - path: nxp/rt1170-evk-make-freertos-builtin
           - path: renesas/ek-ra6m4-make-baremetal-builtin
           - path: pico-sdk/pico-rndis-dashboard
-          - path: pico-sdk/pico-w
-          - path: pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin
-          - path: pico-sdk/w5500-evb-pico2-picosdk-baremetal-builtin
+          - path: pico-sdk/pico-w-picosdk-freertos-lwip
+          - path: pico-sdk/pico-2-w-picosdk-freertos-lwip
           - path: stm32/nucleo-f746zg-make-freertos-tcp
           - path: stm32/nucleo-f746zg-make-baremetal-builtin-cmsis_driver
     name: ${{ matrix.example.path }} ${{ matrix.ssl }}
@@ -453,7 +445,7 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-      - run: make -C examples/${{ matrix.example.path }} build CFLAGS_EXTRA="${{ matrix.ssl }}"
+      - run: make -C tutorials/${{ matrix.example.path }} build CFLAGS_EXTRA="${{ matrix.ssl }}"
 
 #  mqtt_dashboard_examples:
 #    runs-on: ubuntu-latest
@@ -467,7 +459,7 @@ jobs:
 #      - uses: actions/checkout@v4
 #        with: { fetch-depth: 2 }
 #      - run: echo # nothing specific to install or do
-#      - run: make -C examples/${{ matrix.example.path }} build
+#      - run: make -C tutorials/${{ matrix.example.path }} build
       
   mqtt_dashboard_examples_arm:
     runs-on: ubuntu-latest
@@ -481,7 +473,7 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-      - run: make -C examples/${{ matrix.example.path }} build
+      - run: make -C tutorials/${{ matrix.example.path }} build
       
 #  dual_examples:
 #    runs-on: ubuntu-latest
@@ -495,8 +487,8 @@ jobs:
 #      - uses: actions/checkout@v4
 #        with: { fetch-depth: 2 }
 #      - run: echo # nothing specific to install or do
-#      - run: make -C examples/${{ matrix.example.path }} device_dashboard
-#      - run: make -C examples/${{ matrix.example.path }} mqtt_dashboard
+#      - run: make -C tutorials/${{ matrix.example.path }} device_dashboard
+#      - run: make -C tutorials/${{ matrix.example.path }} mqtt_dashboard
 
   cube_examples:
     runs-on: ubuntu-latest
@@ -506,24 +498,6 @@ jobs:
       - run: sudo pip install yq
       - run: cd test/cube && make
 
-  zephyr_examples:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v4
-        with: { fetch-depth: 2 }
-      - run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-      - run: make -C examples/zephyr init REPO=zephyrprojectrtos/ci:v.0.26.14 # "no space left on device" with newers
-      - name: minify manifest
-        uses: mikefarah/yq@master
-        with:
-          cmd: yq -i eval '(.manifest.defaults, .manifest.remotes, .manifest.projects[] | select(.name == "cmsis" or .name == "hal_stm32" or .name == "mbedtls" or .name == "mcuboot" or .name == "picolibc" | del(.null) ), .manifest.self) as $i ireduce({};setpath($i | path; $i)) | del(.manifest.projects.[].null) | del(..|select(length==0))' examples/zephyr/zephyrproject/zephyr/west.yml
-      - run: make -C examples/zephyr update
-      - run: make -C examples/zephyr/device-dashboard build
-      - run: make -C examples/zephyr/http-client build
-      - run: make -C examples/zephyr/http-server build
-      - run: make -C examples/zephyr/mqtt-aws-client build
-      - run: make -C examples/zephyr/websocket-server build
-
   test_f7:
     runs-on: ubuntu-latest
     steps:
@@ -531,14 +505,14 @@ jobs:
       with: { fetch-depth: 2 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/stm32/nucleo-f746zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/stm32/nucleo-f746zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/stm32/nucleo-f746zg-make-freertos-tcp test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-f746zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-f746zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-f746zg-make-freertos-tcp test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     - name: Cube
       run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
-#    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
-    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
+    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
 
   test_f4:
     runs-on: ubuntu-latest
@@ -547,13 +521,13 @@ jobs:
       with: { fetch-depth: 2 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/stm32/nucleo-f429zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/stm32/nucleo-f429zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-f429zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-f429zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     - name: Cube
       run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-#    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
 
   test_h743:
     runs-on: ubuntu-latest
@@ -562,12 +536,12 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/stm32/nucleo-h743zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/stm32/nucleo-h743zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-h743zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-h743zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #    - name: Cube
 #      run: echo # nothing specific to install or do
-#    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
-#    - run: make -C test/cube test PROJECTS=../../examples/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#    - run: make -C test/cube PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
 
   test_h723:
     runs-on: ubuntu-latest
@@ -576,8 +550,8 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/stm32/nucleo-h723zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/stm32/nucleo-h723zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-h723zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-h723zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
     
   test_h5:
     runs-on: ubuntu-latest
@@ -586,8 +560,8 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/stm32/nucleo-h563zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/stm32/nucleo-h563zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-h563zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/stm32/nucleo-h563zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_rt1020:
     runs-on: ubuntu-latest
@@ -596,8 +570,8 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/nxp/rt1020-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/nxp/rt1020-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/nxp/rt1020-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/nxp/rt1020-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_rt1060:
     runs-on: ubuntu-latest
@@ -606,8 +580,8 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/nxp/rt1060-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/nxp/rt1060-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/nxp/rt1060-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/nxp/rt1060-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_rt1170:
     runs-on: ubuntu-latest
@@ -616,8 +590,8 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/nxp/rt1170-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run: make -C examples/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/nxp/rt1170-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_ra6m4:
     runs-on: ubuntu-latest
@@ -626,8 +600,8 @@ jobs:
       with: { fetch-depth: 3 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run: make -C examples/renesas/ek-ra6m4-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-#    - run: make -C examples/renesas/ek-ra6m4-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run: make -C tutorials/renesas/ek-ra6m4-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#    - run: make -C tutorials/renesas/ek-ra6m4-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_tm4c:
     runs-on: ubuntu-latest
@@ -636,8 +610,8 @@ jobs:
       with: { fetch-depth: 2 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run:  make -C examples/ti/ek-tm4c1294xl-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run:  make -C examples/ti/ek-tm4c1294xl-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run:  make -C tutorials/ti/ek-tm4c1294xl-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run:  make -C tutorials/ti/ek-tm4c1294xl-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_same54:
     runs-on: ubuntu-latest
@@ -646,8 +620,8 @@ jobs:
       with: { fetch-depth: 2 }
     - name: baremetal
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run:  make -C examples/microchip/same54-xpro/device-dashboard test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-    - run:  make -C examples/microchip/same54-xpro/mqtt-client test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run:  make -C tutorials/http/device-dashboard/microchip/same54-xpro test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run:  make -C tutorials/mqtt/mqtt-client/microchip/same54-xpro test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 
   test_pico_w5500:
     runs-on: ubuntu-latest
@@ -656,5 +630,5 @@ jobs:
       with: { fetch-depth: 2 }
     - name: SDK
       run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-    - run:  make -C examples/pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+    - run:  make -C tutorials/pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 

.github/workflows/quicktest.yml

@@ -5,6 +5,8 @@ on:
       - "**Makefile"
       - "**.c"
       - "**.h"
+  # Allow manual runs
+  workflow_dispatch:
 env:
   IPV6: 0
 jobs:
@@ -20,28 +22,33 @@ jobs:
     env:
       CC: ${{ matrix.cc }}
       SSL: ${{ matrix.ssl }}
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: if ./test/match_changed_files.sh '^test|^src/.*.[ch]' ; then echo GO=1 >> $GITHUB_ENV ; fi
     - if: ${{ env.GO == 1 }}
-      run: make -C test ${{ matrix.target }}
+      run: if [ "${{ matrix.target }}" == "test" ]; then ./test/setup_mqtt_server.sh ; fi && make -C test ${{ matrix.target }}
   s390:
     runs-on: ubuntu-latest
+    env:
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: if ./test/match_changed_files.sh '^test|^src/.*.[ch]' ; then echo GO=1 >> $GITHUB_ENV ; fi
     - if: ${{ env.GO == 1 }}
-      run: sudo apt -y update ; sudo apt -y install qemu binfmt-support qemu-user-static && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test s390
+      run: sudo apt -y update ; sudo apt -y install binfmt-support qemu-user-static && ./test/setup_mqtt_server.sh && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test s390
   armhf:
     runs-on: ubuntu-latest
+    env:
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: if ./test/match_changed_files.sh '^test|^src/.*.[ch]' ; then echo GO=1 >> $GITHUB_ENV ; fi
     - if: ${{ env.GO == 1 }}
-      run: sudo apt -y update ; sudo apt -y install qemu binfmt-support qemu-user-static && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test armhf
+      run: sudo apt -y update ; sudo apt -y install binfmt-support qemu-user-static && ./test/setup_mqtt_server.sh && docker run --rm --privileged multiarch/qemu-user-static --reset -p yes && make -C test armhf
   unamalgamated-mg_prefix:
     runs-on: ubuntu-latest
     steps:
@@ -59,14 +66,17 @@ jobs:
     name: macos SSL=${{ matrix.ssl }}
     env:
       SSL: ${{ matrix.ssl }}
-      TFLAGS: -DNO_SNTP_CHECK
+      TFLAGS: -DMQTT_LOCALHOST # -DNO_SNTP_CHECK
       HOMEBREW_NO_AUTO_UPDATE: 1
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: if ./test/match_changed_files.sh '^test|^src/.*.[ch]' ; then echo GO=1 >> $GITHUB_ENV ; fi
     - if: ${{ env.GO == 1 }}
-      run:  make -C test test ASAN_OPTIONS=
+      run: |
+        brew install mosquitto
+        /opt/homebrew/opt/mosquitto/sbin/mosquitto -c /Users/runner/work/mongoose/mongoose/test/mosquitto.conf.macos &
+        make -C test test ASAN_OPTIONS=
   windows:
     runs-on: ubuntu-latest
     strategy:
@@ -74,12 +84,14 @@ jobs:
       matrix:
         target: [vc98, vc22, mingw++]
     name: windows ${{ matrix.target }}
+    env:
+      TFLAGS: -DMQTT_LOCALHOST
     steps:
     - uses: actions/checkout@v4
       with: { fetch-depth: 2 }
     - run: if ./test/match_changed_files.sh '^test|^src/.*.[ch]' ; then echo GO=1 >> $GITHUB_ENV ; fi
     - if: ${{ env.GO == 1 }}
-      run: make -C test ${{ matrix.target }} 
+      run: ./test/setup_mqtt_server.sh && make -C test ${{ matrix.target }} 
   arm:
     runs-on: ubuntu-latest
     steps:
@@ -91,60 +103,6 @@ jobs:
     - uses: actions/checkout@v4
     - run: make -C test riscv
 
-  examples:
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test examples_essential
-    - run: make -C test clean_examples_essential
-  examples_win:
-    runs-on: windows-latest
-    steps:
-    - uses: actions/checkout@v4
-#    - uses: egor-tensin/setup-mingw@v2
-#      with:
-#        platform: x64
-    - name: test they build
-      run: make -C test examples_win
-      shell: cmd
-    - name: test they clean
-      run: make -C test clean_examples_win
-      shell: cmd
-  examples_mac:
-    runs-on: macos-latest
-    env: { HOMEBREW_NO_AUTO_UPDATE: 1 }
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test examples_mac
-    - run: make -C test clean_examples_mac
-
-  refprojs:
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test refprojs
-    - run: make -C test clean_refprojs
-  refprojs_win:
-    runs-on: windows-latest
-    steps:
-    - uses: actions/checkout@v4
-#    - uses: egor-tensin/setup-mingw@v2
-#      with:
-#        platform: x64
-    - name: test they build
-      run: make -C test refprojs_win
-      shell: cmd
-    - name: test they clean
-      run: make -C test clean_refprojs_win
-      shell: cmd
-  refprojs_mac:
-    runs-on: macos-latest
-    env: { HOMEBREW_NO_AUTO_UPDATE: 1 }
-    steps:
-    - uses: actions/checkout@v4
-    - run: make -C test refprojs
-    - run: make -C test clean_refprojs
-
   tutorials:
     runs-on: ubuntu-latest
     steps:
@@ -192,7 +150,7 @@ jobs:
 #            # nothing specific to install or do
 #          fi
 #      - if: ${{ env.GO == 1 }}
-#        run: make -C examples/${{ matrix.example.path }} build
+#        run: make -C tutorials/${{ matrix.example.path }} build
 
   wizard_examples_arm:
     runs-on: ubuntu-latest
@@ -200,11 +158,18 @@ jobs:
       fail-fast: false
       matrix:
         example:
+          - path: infineon/xmc47_relax-make-baremetal-builtin
+          - path: infineon/xmc_plt2go_4400-make-baremetal-builtin
+          - path: infineon/xmc72_evk-make-baremetal-builtin
           - path: nxp/frdm-mcxn947-make-baremetal-builtin
           - path: nxp/frdm-mcxn947-make-freertos-builtin
           - path: nxp/rt1020-evk-make-baremetal-builtin
           - path: nxp/rt1060-evk-make-baremetal-builtin
           - path: nxp/rt1170-evk-make-baremetal-builtin
+          - path: pico-sdk/pico-w-picosdk-baremetal-builtin
+          - path: pico-sdk/pico-2-w-picosdk-baremetal-builtin
+          - path: pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin
+          - path: pico-sdk/w5500-evb-pico2-picosdk-baremetal-builtin
           - path: stm32/nucleo-f429zi-make-baremetal-builtin
           - path: stm32/nucleo-f429zi-make-freertos-builtin
           - path: stm32/nucleo-f746zg-make-baremetal-builtin
@@ -231,7 +196,7 @@ jobs:
             sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
           fi
       - if: ${{ env.GO == 1 }}
-        run: make -C examples/${{ matrix.example.path }} build
+        run: make -C tutorials/${{ matrix.example.path }} build
 
 
   generic_examples:
@@ -240,20 +205,20 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: esp32/uart-bridge
-          - path: esp8266/http-client-server
+          - path: http/uart-bridge/esp32
+          - path: http/http-client/esp8266/http-client-server
     name: ${{ matrix.example.path }}
     env:
       GO: 0
     steps:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
-      - run: if ./test/match_changed_files.sh '^src|^examples/${{ matrix.example.path }}'; then echo GO=1 >> $GITHUB_ENV ; fi
+      - run: if ./test/match_changed_files.sh '^src|^tutorials/http/uart-bridge|^tutorials/${{ matrix.example.path }}'; then echo GO=1 >> $GITHUB_ENV ; fi
       - if: ${{ env.GO == 1 }}
         run: |
           # nothing specific to install or do
       - if: ${{ env.GO == 1 }}
-        run: make -C examples/${{ matrix.example.path }} build
+        run: make -C tutorials/${{ matrix.example.path }} build
   
   generic_examples_arm:
     runs-on: ubuntu-latest
@@ -261,7 +226,6 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: infineon/infineon-xmc4700_4800-lwip-rtx-rtos
           - path: stm32/nucleo-g031-make-baremetal-builtin
     name: ${{ matrix.example.path }}
     env:
@@ -269,11 +233,11 @@ jobs:
     steps:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
-      - run: if ./test/match_changed_files.sh '^src|^examples/${{ matrix.example.path }}'; then echo GO=1 >> $GITHUB_ENV ; fi
+      - run: if ./test/match_changed_files.sh '^src|^tutorials/${{ matrix.example.path }}'; then echo GO=1 >> $GITHUB_ENV ; fi
       - if: ${{ env.GO == 1 }}
         run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
       - if: ${{ env.GO == 1 }}
-        run: make -C examples/${{ matrix.example.path }} build
+        run: make -C tutorials/${{ matrix.example.path }} build
 
   device_dashboard_examples:
     runs-on: ubuntu-latest
@@ -281,7 +245,7 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: esp32/device-dashboard
+          - path: esp32
     name: ${{ matrix.example.path }}
     env:
       GO: 0
@@ -289,12 +253,12 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: |
-          if ./test/match_changed_files.sh '^src|examples/device-dashboard|^examples/${{ matrix.example.path }}'; then
+          if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard'; then
             echo GO=1 >> $GITHUB_ENV
             # nothing specific to install or do
           fi
       - if: ${{ env.GO == 1 }}
-        run: make -C examples/${{ matrix.example.path }} build
+        run: make -C tutorials/http/device-dashboard/${{ matrix.example.path }} build
 
   device_dashboard_examples_arm:
     runs-on: ubuntu-latest
@@ -302,16 +266,14 @@ jobs:
       fail-fast: false
       matrix:
         example:
-          - path: infineon/infineon-xmc7200
-          - path: microchip/same54-xpro/device-dashboard
+          - path: http/device-dashboard/microchip/same54-xpro
           - path: nxp/rt1020-evk-make-freertos-builtin
           - path: nxp/rt1060-evk-make-freertos-builtin
           - path: nxp/rt1170-evk-make-freertos-builtin
           - path: renesas/ek-ra6m4-make-baremetal-builtin
           - path: pico-sdk/pico-rndis-dashboard
-          - path: pico-sdk/pico-w
-          - path: pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin
-          - path: pico-sdk/w5500-evb-pico2-picosdk-baremetal-builtin
+          - path: pico-sdk/pico-w-picosdk-freertos-lwip
+          - path: pico-sdk/pico-2-w-picosdk-freertos-lwip
           - path: stm32/nucleo-f746zg-make-freertos-tcp
           - path: stm32/nucleo-f746zg-make-baremetal-builtin-cmsis_driver
     name: ${{ matrix.example.path }}
@@ -321,12 +283,12 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: |
-          if ./test/match_changed_files.sh '^src|examples/device-dashboard|^examples/${{ matrix.example.path }}'; then
+          if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|^tutorials/${{ matrix.example.path }}'; then
             echo GO=1 >> $GITHUB_ENV
             sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
           fi
       - if: ${{ env.GO == 1 }}
-        run: make -C examples/${{ matrix.example.path }} build
+        run: make -C tutorials/${{ matrix.example.path }} build
 
 #  mqtt_dashboard_examples:
 #    runs-on: ubuntu-latest
@@ -342,12 +304,12 @@ jobs:
 #      - uses: actions/checkout@v4
 #        with: { fetch-depth: 2 }
 #      - run: |
-#          if ./test/match_changed_files.sh '^src|examples/mqtt-dashboard/device|^examples/${{ matrix.example.path }}'; then
+#          if ./test/match_changed_files.sh '^src|tutorials/mqtt/mqtt-dashboard/device|^tutorials/${{ matrix.example.path }}'; then
 #            echo GO=1 >> $GITHUB_ENV
 #            # nothing specific to install or do
 #          fi
 #      - if: ${{ env.GO == 1 }}
-#        run: make -C examples/${{ matrix.example.path }} build
+#        run: make -C tutorials/${{ matrix.example.path }} build
       
   mqtt_dashboard_examples_arm:
     runs-on: ubuntu-latest
@@ -363,12 +325,12 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: |
-          if ./test/match_changed_files.sh '^src|examples/mqtt-dashboard/device|^examples/${{ matrix.example.path }}'; then
+          if ./test/match_changed_files.sh '^src|tutorials/mqtt/mqtt-dashboard/device|^tutorials/${{ matrix.example.path }}'; then
             echo GO=1 >> $GITHUB_ENV
             sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
           fi
       - if: ${{ env.GO == 1 }}
-        run: make -C examples/${{ matrix.example.path }} build
+        run: make -C tutorials/${{ matrix.example.path }} build
       
   cube_examples:
     runs-on: ubuntu-latest
@@ -378,367 +340,367 @@ jobs:
       - uses: actions/checkout@v4
         with: { fetch-depth: 2 }
       - run: |
-          if ./test/match_changed_files.sh '^src|examples/stm32/nucleo-*-cube-*'; then
+          if ./test/match_changed_files.sh '^src|tutorials/stm32/nucleo-*-cube-*'; then
             echo GO=1 >> $GITHUB_ENV
             sudo pip install yq
           fi
       - if: ${{ env.GO == 1 }}
         run: cd test/cube && make
 
-  test_f7:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 2 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/stm32|examples/nxp|examples/ti|examples/microchip/same" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    # always run baremetal on core or dashboard or specific example changes; other examples only on specific example changes
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true   # continue so next test has a chance to re-flash and exit from collisions and flash failures
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/stm32/nucleo-f746zg-make-baremetal-builtin'; then
-          make -C examples/stm32/nucleo-f746zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f746zg-make-freertos-builtin'; then
-          make -C examples/stm32/nucleo-f746zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f746zg-make-freertos-tcp'; then
-          make -C examples/stm32/nucleo-f746zg-make-freertos-tcp test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - name: Cube
-      run: |
-        echo GO=0 >> $GITHUB_ENV
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f7.*-cube-'; then
-          echo GO=1 >> $GITHUB_ENV
-          # nothing specific to install or do
-        fi
-#    - if: ${{ env.GO == 1 }}
+#  test_f7:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 2 }
+#    - name: baremetal
 #      run: |
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f746zg-cube-baremetal-builtin'; then
-#          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-f7.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    # always run baremetal on core or dashboard or specific example changes; other examples only on specific example changes
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true   # continue so next test has a chance to re-flash and exit from collisions and flash failures
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-f746zg-make-baremetal-builtin'; then
+#          make -C tutorials/stm32/nucleo-f746zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #        fi
 #    - if: ${{ env.GO == 1 }}
 #      run: |
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f746zg-cube-freertos-builtin'; then
-#          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
-#        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f746zg-cube-freertos-lwip'; then
-          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
-        fi
-
-
-  test_f4:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 2 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/stm32/nucleo-f4.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/stm32/nucleo-f429zi-make-baremetal-builtin'; then
-          make -C examples/stm32/nucleo-f429zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f429zi-make-freertos-builtin'; then
-          make -C examples/stm32/nucleo-f429zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - name: Cube
-      run: |
-        echo GO=0 >> $GITHUB_ENV
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f4.*-cube-'; then
-          echo GO=1 >> $GITHUB_ENV
-          # nothing specific to install or do
-        fi
-#    - if: ${{ env.GO == 1 }}
-#      run: |
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f429zi-cube-baremetal-builtin'; then
-#          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f746zg-make-freertos-builtin'; then
+#          make -C tutorials/stm32/nucleo-f746zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #        fi
 #    - if: ${{ env.GO == 1 }}
 #      run: |
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f429zi-cube-freertos-builtin'; then
-#          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f746zg-make-freertos-tcp'; then
+#          make -C tutorials/stm32/nucleo-f746zg-make-freertos-tcp test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-f429zi-cube-freertos-lwip'; then
-          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
-        fi
-
-  test_h743:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/stm32/nucleo-h74.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/stm32/nucleo-h743zi-make-baremetal-builtin'; then
-        make -C examples/stm32/nucleo-h743zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-h743zi-make-freertos-builtin'; then
-          make -C examples/stm32/nucleo-h743zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
 #    - name: Cube
 #      run: |
 #        echo GO=0 >> $GITHUB_ENV
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-h74.*-cube-'; then
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f7.*-cube-'; then
 #          echo GO=1 >> $GITHUB_ENV
 #          # nothing specific to install or do
 #        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin'; then
+##          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+##        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f746zg-cube-freertos-builtin'; then
+##          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5    
+##        fi
 #    - if: ${{ env.GO == 1 }}
 #      run: |
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-h743zi-cube-baremetal-builtin'; then
-#          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f746zg-cube-freertos-lwip'; then
+#          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f746zg-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=5
+#        fi
+#
+#
+#  test_f4:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 2 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-f4.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-f429zi-make-baremetal-builtin'; then
+#          make -C tutorials/stm32/nucleo-f429zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #        fi
 #    - if: ${{ env.GO == 1 }}
 #      run: |
-#        if ./test/match_changed_files.sh 'examples/stm32/nucleo-h743zi-cube-freertos-builtin'; then
-#          make -C test/cube test PROJECTS=../../examples/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f429zi-make-freertos-builtin'; then
+#          make -C tutorials/stm32/nucleo-f429zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 #        fi
-
-  test_h723:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/stm32/nucleo-h72.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/stm32/nucleo-h723zg-make-baremetal-builtin'; then
-          make -C examples/stm32/nucleo-h723zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-h723zg-make-freertos-builtin'; then
-          make -C examples/stm32/nucleo-h723zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    
-  test_h5:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/stm32/nucleo-h5.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/stm32/nucleo-h563zi-make-baremetal-builtin'; then
-          make -C examples/stm32/nucleo-h563zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/stm32/nucleo-h563zi-make-freertos-builtin'; then
-          make -C examples/stm32/nucleo-h563zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-
-  test_rt1020:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/nxp/rt1020.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/nxp/rt1020-evk-make-baremetal-builtin'; then
-          make -C examples/nxp/rt1020-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/nxp/rt1020-evk-make-freertos-builtin'; then
-          make -C examples/nxp/rt1020-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-
-  test_rt1060:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/nxp/rt1060.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/nxp/rt1060-evk-make-baremetal-builtin'; then
-          make -C examples/nxp/rt1060-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/nxp/rt1060-evk-make-freertos-builtin'; then
-          make -C examples/nxp/rt1060-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-
-  test_rt1170:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/nxp/rt1170.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/nxp/rt1170-evk-make-baremetal-builtin'; then
-          make -C examples/nxp/rt1170-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/nxp/rt1170-evk-make-freertos-builtin'; then
-          make -C examples/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-
-  test_ra6m4:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 3 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/renesas/ek-ra6m4.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      continue-on-error: true
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/renesas/ek-ra6m4-make-baremetal-builtin'; then
-          make -C examples/renesas/ek-ra6m4-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
+#    - name: Cube
+#      run: |
+#        echo GO=0 >> $GITHUB_ENV
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f4.*-cube-'; then
+#          echo GO=1 >> $GITHUB_ENV
+#          # nothing specific to install or do
+#        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin'; then
+##          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+##        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f429zi-cube-freertos-builtin'; then
+##          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
+##        fi
 #    - if: ${{ env.GO == 1 }}
 #      run: |
-#        if ./test/match_changed_files.sh 'examples/renesas/ek-ra6m4-make-freertos-builtin'; then
-#          make -C examples/renesas/ek-ra6m4-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-f429zi-cube-freertos-lwip'; then
+#          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-f429zi-cube-freertos-lwip VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=2
 #        fi
-
-  test_tm4c:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 2 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/ti/ek-tm4c.*-make-" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/ti/ek-tm4c1294xl-make-baremetal-builtin'; then
-          make -C examples/ti/ek-tm4c1294xl-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/ti/ek-tm4c1294xl-make-freertos-builtin'; then
-          make -C examples/ti/ek-tm4c1294xl-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-
-  test_same54:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 2 }
-    - name: baremetal
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/microchip/same54-xpro" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh '^src|examples/device-dashboard|examples/microchip/same54-xpro/device-dashboard'; then
-          make -C examples/microchip/same54-xpro/device-dashboard test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-    - if: ${{ env.GO == 1 }}
-      run: |
-        if ./test/match_changed_files.sh 'examples/microchip/same54-xpro/mqtt-client'; then
-          make -C examples/microchip/same54-xpro/mqtt-client test VCON_API_KEY=${{secrets.VCON_API_KEY}}
-        fi
-
-  test_pico_w5500:
-    runs-on: ubuntu-latest
-    env:
-      GO: 0
-    steps:
-    - uses: actions/checkout@v4
-      with: { fetch-depth: 2 }
-    - name: SDK
-      run: |
-        if ./test/match_changed_files.sh "^src|examples/device-dashboard|examples/pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin" ; then
-          echo GO=1 >> $GITHUB_ENV
-          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
-        fi
-    - if: ${{ env.GO == 1 }}
-      run:  make -C examples/pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#
+#  test_h743:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-h74.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-h743zi-make-baremetal-builtin'; then
+#        make -C tutorials/stm32/nucleo-h743zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-h743zi-make-freertos-builtin'; then
+#          make -C tutorials/stm32/nucleo-h743zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+##    - name: Cube
+##      run: |
+##        echo GO=0 >> $GITHUB_ENV
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-h74.*-cube-'; then
+##          echo GO=1 >> $GITHUB_ENV
+##          # nothing specific to install or do
+##        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin'; then
+##          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-baremetal-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+##        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-h743zi-cube-freertos-builtin'; then
+##          make -C test/cube test PROJECTS=../../tutorials/stm32/nucleo-h743zi-cube-freertos-builtin VCON_API_KEY=${{secrets.VCON_API_KEY}} DEVICE=6
+##        fi
+#
+#  test_h723:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-h72.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-h723zg-make-baremetal-builtin'; then
+#          make -C tutorials/stm32/nucleo-h723zg-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-h723zg-make-freertos-builtin'; then
+#          make -C tutorials/stm32/nucleo-h723zg-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    
+#  test_h5:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-h5.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/stm32/nucleo-h563zi-make-baremetal-builtin'; then
+#          make -C tutorials/stm32/nucleo-h563zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/stm32/nucleo-h563zi-make-freertos-builtin'; then
+#          make -C tutorials/stm32/nucleo-h563zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#
+#  test_rt1020:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/nxp/rt1020.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/nxp/rt1020-evk-make-baremetal-builtin'; then
+#          make -C tutorials/nxp/rt1020-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/nxp/rt1020-evk-make-freertos-builtin'; then
+#          make -C tutorials/nxp/rt1020-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#
+#  test_rt1060:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/nxp/rt1060.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/nxp/rt1060-evk-make-baremetal-builtin'; then
+#          make -C tutorials/nxp/rt1060-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/nxp/rt1060-evk-make-freertos-builtin'; then
+#          make -C tutorials/nxp/rt1060-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#
+#  test_rt1170:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/nxp/rt1170.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/nxp/rt1170-evk-make-baremetal-builtin'; then
+#          make -C tutorials/nxp/rt1170-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/nxp/rt1170-evk-make-freertos-builtin'; then
+#          make -C tutorials/nxp/rt1170-evk-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#
+#  test_ra6m4:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 3 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/renesas/ek-ra6m4.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      continue-on-error: true
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/renesas/ek-ra6m4-make-baremetal-builtin'; then
+#          make -C tutorials/renesas/ek-ra6m4-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+##    - if: ${{ env.GO == 1 }}
+##      run: |
+##        if ./test/match_changed_files.sh 'tutorials/renesas/ek-ra6m4-make-freertos-builtin'; then
+##          make -C tutorials/renesas/ek-ra6m4-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+##        fi
+#
+#  test_tm4c:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 2 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/ti/ek-tm4c.*-make-" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard|tutorials/ti/ek-tm4c1294xl-make-baremetal-builtin'; then
+#          make -C tutorials/ti/ek-tm4c1294xl-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh 'tutorials/ti/ek-tm4c1294xl-make-freertos-builtin'; then
+#          make -C tutorials/ti/ek-tm4c1294xl-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#
+#  test_same54:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 2 }
+#    - name: baremetal
+#      run: |
+#        if ./test/match_changed_files.sh "^src|tutorials/http/device-dashboard|tutorials/mqtt/mqtt-client" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/http/device-dashboard'; then
+#          make -C tutorials/http/device-dashboard/microchip/same54-xpro test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run: |
+#        if ./test/match_changed_files.sh '^src|tutorials/mqtt/mqtt-client'; then
+#          make -C tutorials/mqtt/mqtt-client/microchip/same54-xpro test VCON_API_KEY=${{secrets.VCON_API_KEY}}
+#        fi
+#
+#  test_pico_w5500:
+#    runs-on: ubuntu-latest
+#    env:
+#      GO: 0
+#    steps:
+#    - uses: actions/checkout@v4
+#      with: { fetch-depth: 2 }
+#    - name: SDK
+#      run: |
+#        if ./test/match_changed_files.sh "^src" ; then
+#          echo GO=1 >> $GITHUB_ENV
+#          sudo apt -y update && sudo apt -y install gcc-arm-none-eabi
+#        fi
+#    - if: ${{ env.GO == 1 }}
+#      run:  make -C tutorials/pico-sdk/w5500-evb-pico-picosdk-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}}
 

.github/workflows/zephyr.yml

@@ -0,0 +1,26 @@
+name: Zephyr
+on:
+  schedule:
+    - cron: '0 0 * * *' # run at 12 AM UTC
+  # Allow manual runs
+  workflow_dispatch:
+jobs:
+  zephyr_examples:
+    runs-on: ubuntu-24.04
+    strategy:
+      fail-fast: false
+      matrix:
+        revno: ["--mr v3.7-branch", "--mr v4.2.0"] # LTS, latest stable
+    name: Zephyr ${{ matrix.revno }}
+    steps:
+      - uses: actions/checkout@v4
+        with: { fetch-depth: 2 }
+      - run: test/setup_ga_docker_filesystem.sh
+      - run: make -C tutorials/zephyr init REPO=zephyrprojectrtos/ci REVNO="${{ matrix.revno }}"
+      - run: make -C tutorials/zephyr minify REVNO="${{ matrix.revno }}"
+      - run: make -C tutorials/zephyr update
+      - run: make -C tutorials/zephyr/device-dashboard build
+      - run: make -C tutorials/zephyr/http-client build
+      - run: make -C tutorials/zephyr/http-server build
+      - run: make -C tutorials/zephyr/mqtt-aws-client build
+      - run: make -C tutorials/zephyr/websocket-server build

LICENSE

@@ -1,5 +1,5 @@
 Copyright (c) 2004-2013 Sergey Lyubka
-Copyright (c) 2013-2024 Cesanta Software Limited
+Copyright (c) 2013-2025 Cesanta Software Limited
 All rights reserved
 
 This software is dual-licensed: you can redistribute it and/or modify

README.md

@@ -1,9 +1,9 @@
 # Mongoose - Embedded Web Server / Embedded Network Library
 
 [![License: GPLv2/Commercial](https://img.shields.io/badge/License-GPLv2%20or%20Commercial-green.svg)](https://opensource.org/licenses/gpl-2.0.php)
-[![Build Status]( https://github.com/cesanta/mongoose/workflows/build/badge.svg)](https://github.com/cesanta/mongoose/actions)
+[![Build Status]( https://github.com/cesanta/mongoose/actions/workflows/quicktest.yml/badge.svg)](https://github.com/cesanta/mongoose/actions)
 [![Code Coverage](https://codecov.io/gh/cesanta/mongoose/branch/master/graph/badge.svg)](https://codecov.io/gh/cesanta/mongoose)
-[![Fuzzing Status](https://oss-fuzz-build-logs.storage.googleapis.com/badges/mongoose.svg)](https://bugs.chromium.org/p/oss-fuzz/issues/list?sort=-opened&can=1&q=proj:mongoose)
+[![Fuzzing Status](https://oss-fuzz-build-logs.storage.googleapis.com/badges/mongoose.svg)](https://issues.oss-fuzz.com/issues?sort=-opened&can=1&q=proj:mongoose)
 
 Mongoose is a network library for C/C++.  It provides event-driven non-blocking
 APIs for TCP, UDP, HTTP, WebSocket, MQTT, and other protocols.  It is designed
@@ -14,7 +14,7 @@ robust, and easy. Features include:
 
 - Cross-platform:
   - works on Linux/UNIX, MacOS, Windows, Android
-  - works on STM32, NXP, ESP32, NRF52, TI, Microchip, and other
+  - works on ST, NXP, ESP32, Nordic, TI, Microchip, Infineon, Renesas and other chips
   - write code once - and it'll work everywhere
   - ideal for the unification of the network infrastructure code across company
 - Built-in protocols: plain TCP/UDP, SNTP, HTTP, MQTT, Websocket, and other
@@ -34,6 +34,35 @@ robust, and easy. Features include:
 
 See https://mongoose.ws/ for complete documentation, videos, case studies, etc.
 
+## Supported platforms
+
+Mongoose can work on top of any TCP/IP stack that supports BSD sockets API.
+Platforms supported by the 3rd party TCP/IP stacks:
+
+| TCP/IP stack    | Notes |
+| :-------------- | :------- |
+| **lwIP**        | All devices running lwIP, for example ESP32, ESP32S3, ESP32C3, ESP32C6, etc |
+| **Zephyr**      | All devices supported by Zephyr |
+| **Other**       | Any other TCP/IP stack that supports BSD socket API, for example Amazon FreeRTOS-TCP |
+| **Linux, Mac, Windows**   | Workstations, server, single board computers, embedded Linux devices running on MPUs or FPGAs |
+
+Optionally, Mongoose provides its own built-in TCP/IP stack, eliminating the
+need for additional software to implement networking functionality. The
+built-in stack supports operation in both bare-metal and RTOS environments.
+Platforms supported by the Mongoose built-in TCP/IP stack:
+
+| Hardware       | Notes |
+| :------------- | :------- |
+| **STM32**      | All STM32 MCUs with built-in Ethernet: STM32Fxx, STM32H5xx, STM32H7xx |
+| **NXP**        |  All NXP MCUs with built-in Ethernet: IMXRT102x, IMXRT104x, IMXRT105x, IMXRT106x, IMXRT117x, RW612, MCXN94x   |
+| **Microchip**  | ATSAME54 MCUs with built-int Ethernet  |
+| **Renesas**    | RA5M, RA6M, RA8M MCUs with built-in Ethernet    |
+| **Infineon**   | XMC4, XMC7 MCUs with built-in Ethernet    |
+| **Texas Instruments**  |  TM4C, TMS570 MCUs with built-in Ethernet   |
+| **Cypress WiFi**  | Any MCU with CY43xx WiFi chips, like RP2040 Pico-W, RP2350 Pico2-W, Arduino Portenta    |
+| **Wiznet Ethernet**  | Any MCU that use Wiznet W5500 or Wiznet 5100 MAC+PHY chips    |
+| **Cellular**   | NRF9160, SIM800    |
+
 ## Usage Examples
 
 Below are quick snippets that should give an idea how simple the API is and
@@ -170,6 +199,20 @@ We take security seriously:
   of which we get notified and in case of any issue, act similar to (3).
 
 
+## Articles
+
+Technical guides and deep dives into embedded web servers, WebUI integration and embedded networking technologies:
+- [Embedded Web Server: A Comprehensive Guide for Modern Connected Devices](https://mongoose.ws/articles/embedded-web-server-a-comprehensive-guide-for-modern-connected-devices/)
+- [Building Embedded Web Device Dashboards](https://mongoose.ws/articles/building-embedded-web-device-dashboard/)
+- [ESP32 Device Dashboard: A Step-by-Step Guide for Developers](https://mongoose.ws/articles/esp32-device-dashboard/)
+- [How to build an STM32 Web Dashboard](https://mongoose.ws/articles/stm32-device-dashboard/)
+- [STM32 WebSocket Guide](https://mongoose.ws/articles/stm32-websocket-guide/)
+- [Web File Manager on STM32, ESP32 and Embedded Linux](https://mongoose.ws/articles/building-a-web-file-manager-on-stm32-esp32-embedded-linux/)
+- [Web dashboard on Zephyr RTOS](https://mongoose.ws/articles/web-dashboard-on-zephyr-rtos/)
+- [Limiting TCP/IP RAM usage on STM32](https://mongoose.ws/articles/limiting-tcpip-ram-usage-on-stm32/)
+- [STM32 Ethernet explained](https://mongoose.ws/articles/stm32-ethernet-explained/)
+
+
 ## Contributions
 
 Contributions are welcome! Please follow the guidelines below:

examples/README.md

@@ -1,24 +0,0 @@
-# Mongoose Network Library Examples
-
-In order to build and run any of the existing examples, please follow:
-https://mongoose.ws/documentation/#how-to-build-and-run-examples
-
-## Contributing
-
-Rules for creating a new example:
-
-- Makefile golden reference for desktop/server example: [http-server](http-server)
-- Makefile golden reference for the embedded example:
-   [stm32/nucleo-f746zg-baremetal](stm32/nucleo-f746zg-baremetal)
-- An example must build on Windows, Mac and Ubuntu Linux systems
-- Assume that user installed tools according to https://mongoose.ws/tutorials/tools/
-- Makefile must not include any other make files
-- Use `CFLAGS` for system-specific compilation options
-- Use `CFLAGS_MONGOOSE` for mongoose-specific compilation options
-- Use `$(CFLAGS) $(CFLAGS_MONGOOSE) $(CFLAGS_EXTRA)` to compile
-- If external repository is required, download it on demand using git
-  shallow clone. See embedded example golden reference
-- Keep Makefile as short as possible, but verbose to understand it easily
-- Symlink files when required, like `mongoose.c`, `ca.pem`, etc. Make no copies
-- Example's README.md should contain only the title and the link to mongoose.ws
-  tutorial page

examples/arduino/Makefile

@@ -1,28 +0,0 @@
-
-all:
-example:
-	true
-
-arduino: ENV = -v $(CWD):/root
-arduino:
-	curl -sL http://downloads.arduino.cc/arduino-1.8.19-linux64.tar.xz | unxz | tar -xf -
-	mv arduino-* $@
-
-arduino-xiao-board:
-	./arduino/arduino --pref "boardsmanager.additional.urls=https://files.seeedstudio.com/arduino/package_seeeduino_boards_index.json" --save-prefs
-	./arduino/arduino --pref "compiler.warning_level=all" --save-prefs
-	./arduino/arduino --install-boards Seeeduino:samd
-
-arduino-xiao: arduino arduino-xiao-board
-	cd w5500-http && ../arduino/arduino --verbose --verify --board Seeeduino:samd:seeed_XIAO_m0 w5500-http.ino
-	cd w5500-mqtt && ../arduino/arduino --verbose --verify --board Seeeduino:samd:seeed_XIAO_m0 w5500-mqtt.ino
-
-arduino-nano: arduino
-	cd w5500-http && ../arduino/arduino --pref compiler.cpp.extra_flags=-DMG_ENABLE_LOG=0 --verbose --verify --board arduino:avr:nano w5500-http.ino
-	cd w5500-mqtt && ../arduino/arduino --pref compiler.cpp.extra_flags=-DMG_ENABLE_LOG=0 --verbose --verify --board arduino:avr:nano w5500-mqtt.ino
-
-clean:
-	rm -rf arduino 
-
-cleanall: clean		#otherwise some parts of xiao-board installation will fail as already installed
-	rm -rf ~/.arduino15 ~/.oracle_jre_usage

examples/arduino/w5500-http/w5500-http.ino

@@ -1,49 +0,0 @@
-#include <SPI.h>
-#include "mongoose.h"
-
-#define SS_PIN 3    // Slave select pin
-struct mg_mgr mgr;  // Mongoose event manager
-struct mg_tcpip_spi spi = {
-    NULL,                                               // SPI data
-    [](void *) { digitalWrite(SS_PIN, LOW); },          // begin transation
-    [](void *) { digitalWrite(SS_PIN, HIGH); },         // end transaction
-    [](void *, uint8_t c) { return SPI.transfer(c); },  // execute transaction
-};
-struct mg_tcpip_if mif = {.mac = {2, 0, 1, 2, 3, 5}};  // network interface
-
-void setup() {
-  Serial.begin(115200);
-  pinMode(SS_PIN, OUTPUT);
-  SPI.begin();
-
-  // Set logging function to a serial print
-  mg_log_set_fn([](char ch, void *) { Serial.print(ch); }, NULL);
-  mg_mgr_init(&mgr);
-
-  delay(3000);
-  MG_INFO(("Starting TCP/IP stack..."));
-
-  mif.driver = &mg_tcpip_driver_w5500;
-  mif.driver_data = &spi;
-  mg_tcpip_init(&mgr, &mif);
-
-  // Start a 5 sec timer, print status message periodically
-  mg_timer_add(
-      &mgr, 5000, MG_TIMER_REPEAT,
-      [](void *) {
-        MG_INFO(("ethernet: %s", mg_tcpip_driver_w5500.up(&mif) ? "up" : "down"));
-      },
-      NULL);
-
-  // Setup HTTP listener. Respond "ok" on any HTTP request
-  mg_http_listen(
-      &mgr, "http://0.0.0.0",
-      [](struct mg_connection *c, int ev, void *ev_data) {
-        if (ev == MG_EV_HTTP_MSG) mg_http_reply(c, 200, "", "ok\n");
-      },
-      &mgr);
-}
-
-void loop() {
-  mg_mgr_poll(&mgr, 1);
-}

examples/arduino/w5500-mqtt/net.c

@@ -1,58 +0,0 @@
-#include "net.h"
-
-#define MQTT_SERVER "mqtt://broker.hivemq.com:1883"
-struct mg_connection *mqtt_connection;
-const char *mqtt_subscribe_topic = "mg/rx";
-const char *mqtt_publish_topic = "mg/tx";
-
-struct mg_mgr mgr;  // Mongoose event manager
-struct mg_tcpip_if mif = {.mac = {2, 0, 1, 2, 3, 5}};  // network interface
-
-void mqtt_publish(const char *message) {
-  struct mg_mqtt_opts opts = {};
-  opts.topic = mg_str(mqtt_publish_topic);
-  opts.message = mg_str(message);
-  if (mqtt_connection) mg_mqtt_pub(mqtt_connection, &opts);
-}
-
-static void fn(struct mg_connection *c, int ev, void *ev_data) {
-  if (ev == MG_EV_MQTT_OPEN) {
-    MG_INFO(("%lu CONNECTED to %s", c->id, MQTT_SERVER));
-    struct mg_mqtt_opts opts = {};
-    opts.topic = mg_str(mqtt_subscribe_topic);
-    mg_mqtt_sub(c, &opts);
-    MG_INFO(("%lu SUBSCRIBED to %s", c->id, mqtt_subscribe_topic));
-  } else if (ev == MG_EV_MQTT_MSG) {
-    // Received MQTT message
-    struct mg_mqtt_message *mm = (struct mg_mqtt_message *) ev_data;
-    MG_INFO(("%lu RECEIVED %.*s <- %.*s", c->id, (int) mm->data.len,
-             mm->data.buf, (int) mm->topic.len, mm->topic.buf));
-    exec_command(mm->data.buf, mm->data.len);
-  } else if (ev == MG_EV_CLOSE) {
-    MG_INFO(("%lu CLOSED", c->id));
-    mqtt_connection = NULL;
-  }
-}
-
-static void timer_fn(void *arg) {
-  struct mg_mgr *mgr = (struct mg_mgr *) arg;
-  struct mg_mqtt_opts opts;
-  memset(&opts, 0, sizeof(opts));
-  opts.clean = true;
-  if (mif.state == MG_TCPIP_STATE_READY && mqtt_connection == NULL) {
-    mqtt_connection = mg_mqtt_connect(mgr, MQTT_SERVER, &opts, fn, NULL);
-  }
-  // MG_INFO(("Eth: %d, MQTT: %p", mif.state, mqtt_connection));
-}
-
-void net_init(void) {
-  // Set Mongoose logging function to a serial print
-  mg_mgr_init(&mgr);
-
-  mif.driver = &mg_tcpip_driver_w5500;
-  mif.driver_data = &spi;
-  mg_tcpip_init(&mgr, &mif);
-
-  // Start a timer that keeps MQTT connection alive
-  mg_timer_add(&mgr, 3000, MG_TIMER_REPEAT, timer_fn, &mgr);
-}

examples/arduino/w5500-mqtt/net.h

@@ -1,16 +0,0 @@
-#pragma once
-#include "mongoose.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern struct mg_tcpip_spi spi;
-extern struct mg_mgr mgr;
-void mqtt_publish(const char *message);
-void net_init(void);
-void exec_command(const char *req, size_t req_len);
-
-#ifdef __cplusplus
-}
-#endif

examples/arduino/w5500-mqtt/w5500-mqtt.ino

@@ -1,51 +0,0 @@
-#include <SPI.h>
-#include "net.h"
-
-#define SS_PIN 17   // Slave select pin
-struct mg_tcpip_spi spi = {
-    NULL,                                               // SPI data
-    [](void *) { digitalWrite(SS_PIN, LOW); },          // Begin transaction
-    [](void *) { digitalWrite(SS_PIN, HIGH); },         // End transaction
-    [](void *, uint8_t c) { return SPI.transfer(c); },  // Execute transaction
-};
-
-void exec_command(const char *req, size_t req_len) {
-  char res[100];
-  if (req_len == 2 && strncmp(req, "on", req_len) == 0) {
-    digitalWrite(LED_BUILTIN, true);
-    snprintf(res, sizeof(res), "LED on");
-  } else if (req_len == 3 && strncmp(req, "off", req_len) == 0) {
-    digitalWrite(LED_BUILTIN, false);
-    snprintf(res, sizeof(res), "LED off");
-  } else {
-    snprintf(res, sizeof(res), "Unknown command: [%.*s]", (int) req_len, req);
-  }
-  Serial.println(res);
-  mqtt_publish(res);
-}
-
-static void process_input(char c) {
-  static char buf[100];
-  static size_t len = 0;
-  char response[100];
-  if (c != '\n' && c != '\0') buf[len++] = c;  // Append to the buffer
-  if (len >= sizeof(buf)) len = 0;             // On overflow, reset
-  if (c == '\n' && len > 0) {
-    exec_command(buf, len);
-    len = 0;
-  }
-}
-
-void setup() {
-  Serial.begin(115200);
-  SPI.begin();
-  pinMode(SS_PIN, OUTPUT);
-  pinMode(LED_BUILTIN, OUTPUT);
-  mg_log_set_fn([](char ch, void *) { Serial.print(ch); }, NULL);
-  net_init();
-}
-
-void loop() {
-  if (Serial.available()) process_input(Serial.read());
-  mg_mgr_poll(&mgr, 1);
-}

examples/device-dashboard/mongoose.c

@@ -1 +0,0 @@
-../../mongoose.c

examples/device-dashboard/mongoose.h

@@ -1 +0,0 @@
-../../mongoose.h

examples/device-dashboard/web_root/main.css

@@ -1 +0,0 @@
-/*! tailwindcss v3.3.2 | MIT License | https://tailwindcss.com*/*,:after,:before{box-sizing:border-box;border:0 solid #e5e7eb}:after,:before{--tw-content:""}html{line-height:1.5;-webkit-text-size-adjust:100%;-moz-tab-size:4;-o-tab-size:4;tab-size:4;font-family:Inter var,Helvetica,sans-serif;font-feature-settings:"cv11","ss01";font-variation-settings:"opsz" 32}body{margin:0;line-height:inherit}hr{height:0;color:inherit;border-top-width:1px}abbr:where([title]){-webkit-text-decoration:underline dotted;text-decoration:underline dotted}h1,h2,h3,h4,h5,h6{font-size:inherit;font-weight:inherit}a{color:inherit;text-decoration:inherit}b,strong{font-weight:bolder}code,kbd,pre,samp{font-family:ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,Liberation Mono,Courier New,monospace;font-size:1em}small{font-size:80%}sub,sup{font-size:75%;line-height:0;position:relative;vertical-align:initial}sub{bottom:-.25em}sup{top:-.5em}table{text-indent:0;border-color:inherit;border-collapse:collapse}button,input,optgroup,select,textarea{font-family:inherit;font-size:100%;font-weight:inherit;line-height:inherit;color:inherit;margin:0;padding:0}button,select{text-transform:none}[type=button],[type=reset],[type=submit],button{-webkit-appearance:button;background-color:initial;background-image:none}:-moz-focusring{outline:auto}:-moz-ui-invalid{box-shadow:none}progress{vertical-align:initial}::-webkit-inner-spin-button,::-webkit-outer-spin-button{height:auto}[type=search]{-webkit-appearance:textfield;outline-offset:-2px}::-webkit-search-decoration{-webkit-appearance:none}::-webkit-file-upload-button{-webkit-appearance:button;font:inherit}summary{display:list-item}blockquote,dd,dl,figure,h1,h2,h3,h4,h5,h6,hr,p,pre{margin:0}fieldset{margin:0}fieldset,legend{padding:0}menu,ol,ul{list-style:none;margin:0;padding:0}textarea{resize:vertical}input::-moz-placeholder,textarea::-moz-placeholder{opacity:1;color:#9ca3af}input::placeholder,textarea::placeholder{opacity:1;color:#9ca3af}[role=button],button{cursor:pointer}:disabled{cursor:default}audio,canvas,embed,iframe,img,object,svg,video{display:block;vertical-align:middle}img,video{max-width:100%;height:auto}[hidden]{display:none}*,::backdrop,:after,:before{--tw-border-spacing-x:0;--tw-border-spacing-y:0;--tw-translate-x:0;--tw-translate-y:0;--tw-rotate:0;--tw-skew-x:0;--tw-skew-y:0;--tw-scale-x:1;--tw-scale-y:1;--tw-pan-x: ;--tw-pan-y: ;--tw-pinch-zoom: ;--tw-scroll-snap-strictness:proximity;--tw-gradient-from-position: ;--tw-gradient-via-position: ;--tw-gradient-to-position: ;--tw-ordinal: ;--tw-slashed-zero: ;--tw-numeric-figure: ;--tw-numeric-spacing: ;--tw-numeric-fraction: ;--tw-ring-inset: ;--tw-ring-offset-width:0px;--tw-ring-offset-color:#fff;--tw-ring-color:#3b82f680;--tw-ring-offset-shadow:0 0 #0000;--tw-ring-shadow:0 0 #0000;--tw-shadow:0 0 #0000;--tw-shadow-colored:0 0 #0000;--tw-blur: ;--tw-brightness: ;--tw-contrast: ;--tw-grayscale: ;--tw-hue-rotate: ;--tw-invert: ;--tw-saturate: ;--tw-sepia: ;--tw-drop-shadow: ;--tw-backdrop-blur: ;--tw-backdrop-brightness: ;--tw-backdrop-contrast: ;--tw-backdrop-grayscale: ;--tw-backdrop-hue-rotate: ;--tw-backdrop-invert: ;--tw-backdrop-opacity: ;--tw-backdrop-saturate: ;--tw-backdrop-sepia: }.sr-only{position:absolute;width:1px;height:1px;padding:0;margin:-1px;overflow:hidden;clip:rect(0,0,0,0);white-space:nowrap;border-width:0}.pointer-events-none{pointer-events:none}.pointer-events-auto{pointer-events:auto}.fixed{position:fixed}.absolute{position:absolute}.relative{position:relative}.sticky{position:sticky}.inset-0{inset:0}.bottom-0{bottom:0}.left-0{left:0}.right-auto{right:auto}.top-0{top:0}.isolate{isolation:isolate}.z-10{z-index:10}.z-\[48\]{z-index:48}.z-\[60\]{z-index:60}.col-span-2{grid-column:span 2/span 2}.m-4{margin:1rem}.mx-auto{margin-left:auto;margin-right:auto}.my-0{margin-top:0;margin-bottom:0}.my-1{margin-top:.25rem;margin-bottom:.25rem}.my-2{margin-top:.5rem;margin-bottom:.5rem}.my-3{margin-top:.75rem;margin-bottom:.75rem}.my-4{margin-top:1rem;margin-bottom:1rem}.my-5{margin-top:1.25rem;margin-bottom:1.25rem}.mb-1{margin-bottom:.25rem}.ml-3{margin-left:.75rem}.ml-4{margin-left:1rem}.mr-2{margin-right:.5rem}.mr-4{margin-right:1rem}.mt-1{margin-top:.25rem}.mt-3{margin-top:.75rem}.mt-5{margin-top:1.25rem}.mt-7{margin-top:1.75rem}.block{display:block}.inline-block{display:inline-block}.flex{display:flex}.inline-flex{display:inline-flex}.table{display:table}.grid{display:grid}.hidden{display:none}.h-10{height:2.5rem}.h-12{height:3rem}.h-5{height:1.25rem}.h-6{height:1.5rem}.h-full{height:100%}.min-h-screen{min-height:100vh}.w-0{width:0}.w-11{width:2.75rem}.w-4{width:1rem}.w-5{width:1.25rem}.w-6{width:1.5rem}.w-72{width:18rem}.w-96{width:24rem}.w-full{width:100%}.min-w-full{min-width:100%}.max-w-sm{max-width:24rem}.flex-1{flex:1 1 0%}.flex-shrink-0{flex-shrink:0}.shrink{flex-shrink:1}.shrink-0{flex-shrink:0}.grow{flex-grow:1}.grow-0{flex-grow:0}.basis-\[30px\]{flex-basis:30px}.border-separate{border-collapse:initial}.border-spacing-0Line truncated

examples/esp32/micropython/mongoose/micropython.cmake

@@ -1 +0,0 @@
-../../../micropython/mongoose/micropython.cmake

examples/esp32/micropython/mongoose/micropython.mk

@@ -1 +0,0 @@
-../../../micropython/mongoose/micropython.mk

examples/esp32/micropython/mongoose/module.c

@@ -1 +0,0 @@
-../../../micropython/mongoose/module.c

examples/esp32/uart-bridge/main/net.c

@@ -1 +0,0 @@
-../../../uart-bridge/net.c

examples/esp32/uart-bridge/main/packed_fs.c

@@ -1 +0,0 @@
-../../../uart-bridge/packed_fs.c

examples/file-transfer/mongoose.c

@@ -1 +0,0 @@
-../../mongoose.c

examples/file-transfer/mongoose.h

@@ -1 +0,0 @@
-../../mongoose.h

examples/infineon/infineon-xmc4700_4800-lwip-rtx-rtos/Makefile

@@ -1,9 +0,0 @@
-NAME ?= $(notdir $(CURDIR))
-
-build:
-	git clone --depth 1 https://github.com/mongoose-examples/$(NAME)
-	cp ./../../../mongoose.[ch] $(NAME)
-	make -C $(NAME) build
-
-clean:
-	rm -rf $(NAME)

examples/infineon/infineon-xmc7200/Makefile

@@ -1,41 +0,0 @@
-CFLAGS  = -W -Wall -Werror -Wextra  -Wundef -Wshadow -Wdouble-promotion
-CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly
-CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
-CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_xmc7/devices/COMPONENT_CAT1C/include/
-CFLAGS += -Icmsis_xmc7/devices/COMPONENT_CAT1C/include/ip/
-CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
-LDSCRIPT = link.ld
-LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map 
-
-SOURCES = main.c hal.c startup.c
-CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS	# Make startup code work as expected
-
-# Mongoose options are defined in mongoose_custom.h
-SOURCES += mongoose.c net.c packed_fs.c
-
-# Example specific build options. See README.md
-CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
-
-ifeq ($(OS),Windows_NT)
-  RM = cmd /C del /Q /F /S
-else
-  RM = rm -rf
-endif
-
-all build example: firmware.bin
-
-firmware.bin: firmware.elf
-	arm-none-eabi-objcopy -O binary $< $@
-
-firmware.elf: cmsis_core cmsis_xmc7 $(SOURCES) hal.h link.ld Makefile
-	arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
-	arm-none-eabi-size $@
-
-cmsis_core:     # ARM CMSIS core headers
-	git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
-cmsis_xmc7:
-	git clone https://github.com/Infineon/mtb-pdl-cat1.git $@
-	echo "" > cmsis_xmc7/devices/COMPONENT_CAT1C/include/ip/system_cat1c.h
-
-clean:
-	$(RM) firmware.* *.su cmsis_core cmsis_xmc7 *.zip

examples/infineon/infineon-xmc7200/hal.c

@@ -1,147 +0,0 @@
-// Copyright (c) 2024 Cesanta Software Limited
-// All rights reserved
-
-#include "hal.h"
-
-static volatile uint64_t s_ticks;  // Milliseconds since boot
-void SysTick_Handler(void) {       // SyStick IRQ handler, triggered every 1ms
-  s_ticks++;
-}
-
-bool mg_random(void *buf, size_t len) {  // Use on-board RNG
-  for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
-    uint32_t r = rng_read();
-    memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
-  }
-  return true;
-}
-
-uint64_t mg_millis(void) {  // Let Mongoose use our uptime function
-  return s_ticks;           // Return number of milliseconds since boot
-}
-
-void hal_init(void) {
-  clock_init();                            // Set system clock to SYS_FREQUENCY
-  SystemCoreClock = SYS_FREQUENCY;         // Update SystemCoreClock global var
-  SysTick_Config(SystemCoreClock / 1000);  // Sys tick every 1ms
-  rng_init();                              // Initialise random number generator
-
-  uart_init(UART_DEBUG, 115200);  // Initialise UART
-  gpio_output(LED1);              // Initialise LED1
-  gpio_output(LED2);              // Initialise LED2
-  gpio_output(LED3);              // Initialise LED3
-  ethernet_init();                // Initialise Ethernet pins
-}
-
-#if defined(__ARMCC_VERSION)
-// Keil specific - implement IO printf redirection
-int fputc(int c, FILE *stream) {
-  if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c);
-  return c;
-}
-#elif defined(__GNUC__)
-// ARM GCC specific. ARM GCC is shipped with Newlib C library.
-// Implement newlib syscalls:
-//      _sbrk() for malloc
-//      _write() for printf redirection
-//      the rest are just stubs
-#include <sys/stat.h>  // For _fstat()
-
-uint32_t SystemCoreClock;
-void SystemInit(void) {  // Called automatically by startup code
-}
-
-int _fstat(int fd, struct stat *st) {
-  (void) fd, (void) st;
-  return -1;
-}
-
-extern unsigned char _end[];  // End of data section, start of heap. See link.ld
-static unsigned char *s_current_heap_end = _end;
-
-size_t hal_ram_used(void) {
-  return (size_t) (s_current_heap_end - _end);
-}
-
-size_t hal_ram_free(void) {
-  unsigned char endofstack;
-  return (size_t) (&endofstack - s_current_heap_end);
-}
-
-void *_sbrk(int incr) {
-  unsigned char *prev_heap;
-  unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
-  prev_heap = s_current_heap_end;
-  // Check how much space we  got from the heap end to the stack end
-  if (s_current_heap_end + incr > heap_end) return (void *) -1;
-  s_current_heap_end += incr;
-  return prev_heap;
-}
-
-int _open(const char *path) {
-  (void) path;
-  return -1;
-}
-
-int _close(int fd) {
-  (void) fd;
-  return -1;
-}
-
-int _isatty(int fd) {
-  (void) fd;
-  return 1;
-}
-
-int _lseek(int fd, int ptr, int dir) {
-  (void) fd, (void) ptr, (void) dir;
-  return 0;
-}
-
-void _exit(int status) {
-  (void) status;
-  for (;;) asm volatile("BKPT #0");
-}
-
-void _kill(int pid, int sig) {
-  (void) pid, (void) sig;
-}
-
-int _getpid(void) {
-  return -1;
-}
-
-int _write(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
-  return -1;
-}
-
-int _read(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  return -1;
-}
-
-int _link(const char *a, const char *b) {
-  (void) a, (void) b;
-  return -1;
-}
-
-int _unlink(const char *a) {
-  (void) a;
-  return -1;
-}
-
-int _stat(const char *path, struct stat *st) {
-  (void) path, (void) st;
-  return -1;
-}
-
-int mkdir(const char *path, mode_t mode) {
-  (void) path, (void) mode;
-  return -1;
-}
-
-void _init(void) {
-}
-#endif                 // __GNUC__

examples/infineon/infineon-xmc7200/hal.h

@@ -1,244 +0,0 @@
-// Copyright (c) 2023 Cesanta Software Limited
-// All rights reserved
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#define LED1 PIN(16, 1)
-#define LED2 PIN(16, 2)
-#define LED3 PIN(16, 3)
-
-#include "xmc7200d_e272k8384.h"
-
-#define BIT(x) (1UL << (x))
-#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
-#define PIN(bank, num) ((bank << 8) | (num))
-#define PINNO(pin) (pin & 255)
-#define PINBANK(pin) (pin >> 8)
-
-void hal_init(void);
-size_t hal_ram_free(void);
-size_t hal_ram_used(void);
-
-static inline void spin(volatile uint32_t count) {
-  while (count--) (void) 0;
-}
-
-extern uint32_t SystemCoreClock;
-
-enum {PLL_FEEDBACK = 50, PLL_REF = 1, PLL_OUT = 4};
-#define CLK_IMO 8000000UL
-#define SYS_FREQUENCY ((CLK_IMO * PLL_FEEDBACK) / (PLL_REF * PLL_OUT))
-
-#ifndef UART_DEBUG
-#define UART_DEBUG SCB3
-#endif
-
-enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
-enum { GPIO_HIGHZ = 0, GPIO_PULLUP = 2, GPIO_PULLDOWN = 3, GPIO_OPENDRAIN_LOW = 4,
-       GPIO_OPENDRAIN_HIGH = 5, GPIO_STRONG = 6, GPIO_PULLUP_DOWN = 7};
-enum { GPIO_SPEED_LOW = 3, GPIO_SPEED_MEDIUM = 2, GPIO_SPEED_HIGH = 0};
-#undef GPIO
-#define GPIO_TypeDef GPIO_PRT_Type
-#define GPIO(N) ((GPIO_TypeDef *) (GPIO_BASE + 0x80 * (N)))
-
-static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
-
-static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
-                             uint8_t speed, uint8_t pull, uint8_t af) {
-	(void) pin, (void) mode, (void) type, (void) speed, (void) pull, (void) af;
-  GPIO_TypeDef *gpio = gpio_bank(pin);
-  uint8_t pinno = PINNO(pin);
-  uint32_t msk, pos;
-
-  // configure input / output direction
-  if (mode == GPIO_MODE_INPUT) {
-    gpio->CFG |= 1 << (4 * pinno + 3); // enable input buffer (IN_ENx)
-  }
-
-  if (af || (mode == GPIO_MODE_AF && af)) {
-    // configure alternate function
-    HSIOM_PRT_Type* hsiom = ((HSIOM_PRT_Type*) HSIOM) + PINBANK(pin);
-    volatile uint32_t *port_sel = pinno < 4 ? &hsiom->PORT_SEL0 : &hsiom->PORT_SEL1;
-    pos = 8 * (pinno % 4), msk = 0x1f << pos;
-    *port_sel &= ~msk, *port_sel |= af << pos;
-  }
-
-  // configure driver mode
-  msk = 7, pos = 4 * pinno;
-  CLRSET(gpio->CFG, msk << pos, type << pos);
-
-  // configure speed
-  msk = 3, pos = 2 * pinno + 16;
-  CLRSET(gpio->CFG_OUT, msk << pos, speed << pos);
-
-  if (mode == GPIO_MODE_OUTPUT /*&& af == 0*/) {
-    gpio->OUT_SET = (1 << pinno);
-  }
-}
-
-static inline void gpio_input(uint16_t pin) {
-	gpio_init(pin, GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH,
-	            0, 0);
-}
-
-static inline void gpio_output(uint16_t pin) {
-	gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_MEDIUM,
-	            0, 0);
-}
-
-static inline bool gpio_read(uint16_t pin) {
-  GPIO_TypeDef *gpio = gpio_bank(pin);
-  uint8_t pinno = PINNO(pin);
-  if (gpio->CFG & (1 << (4 * pinno + 3))) {
-    // pin mode is input, reading from GPIO_PRT_IN
-    return gpio->IN & (1 << pinno);
-  } else {
-    // pin mode is output, reading from GPIO_PRT_OUT
-    return gpio->OUT & (1 << pinno);
-  }
-}
-
-static inline void gpio_write(uint16_t pin, bool value) {
-	GPIO_TypeDef *gpio = gpio_bank(pin);
-  uint8_t pinno = PINNO(pin);
-  if (value) {
-    gpio->OUT_SET = 1 << pinno;
-  } else {
-    gpio->OUT_CLR = 1 << pinno;
-  }
-}
-
-static inline void gpio_toggle(uint16_t pin) {
-  gpio_write(pin, !gpio_read(pin));
-}
-
-static inline void uart_init(volatile CySCB_Type *uart, unsigned long baud) {
-  (void) uart, (void) baud;
-  uint16_t rx = 0, tx = 0;
-  if (uart == SCB3) {
-    rx = PIN(13, 0), tx = PIN(13, 1);
-  } else {
-    return; // unsupported uart
-  }
-
-  // set pins
-  gpio_init(rx, GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 17);
-  gpio_init(tx, GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 17);
-
-  // enable peripheral clock (18.6.2)
-  // compute divider first (we choose 24 bit divider 0)
-  unsigned long div = 0, frac = 0, ovs = 16;
-  div = SYS_FREQUENCY / (baud * ovs);
-  if (div == 0) div = 1;
-  frac = SYS_FREQUENCY % (baud * ovs);
-  frac = (frac * 100) / (baud * ovs);
-  PERI_PCLK->GR[1].DIV_CMD = (3 << PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos) |
-                             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk |
-                             PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk;
-  PERI_PCLK->GR[1].DIV_CMD |= PERI_PCLK_GR_DIV_CMD_DISABLE_Msk; // disable divider
-  PERI_PCLK->GR[1].DIV_24_5_CTL[0] = (((uint8_t) (div - 1)) << PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos) |
-                                     (frac << PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos);
-  PERI_PCLK->GR[1].DIV_CMD = (3 << PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos) |
-                             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk |
-                             PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk;;
-  PERI_PCLK->GR[1].DIV_CMD |= PERI_PCLK_GR_DIV_CMD_ENABLE_Msk; // enable divider
-  PERI_PCLK->GR[1].CLOCK_CTL[PCLK_SCB3_CLOCK & 0xff] = 3 << PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos;  // connect SCB3 to div_24_5_ctl[0]
-
-  // configure UART interface
-  uart->CTRL = ((ovs - 1) << SCB_CTRL_OVS_Pos) | (2 << SCB_CTRL_MODE_Pos);
-  uart->UART_CTRL = 0;
-  uart->UART_RX_CTRL = 1 << SCB_UART_RX_CTRL_STOP_BITS_Pos;
-  uart->RX_CTRL = 7 << SCB_RX_CTRL_DATA_WIDTH_Pos;
-  uart->UART_TX_CTRL = 1 << SCB_UART_TX_CTRL_STOP_BITS_Pos;
-  uart->TX_CTRL = 7 << SCB_TX_CTRL_DATA_WIDTH_Pos;
-  uart->TX_FIFO_CTRL = 1 << 16;
-  uart->TX_FIFO_CTRL = 0;
-  uart->CTRL |= 1 << SCB_CTRL_ENABLED_Pos;
-}
-
-static inline void uart_write_byte(volatile CySCB_Type *uart, uint8_t byte) {
-  (void) byte; (void) uart;
-  while((uart->INTR_TX & SCB_INTR_TX_EMPTY_Msk) == 0) spin(1);
-  uart->TX_FIFO_WR = byte;
-  uart->INTR_TX |= ~SCB_INTR_TX_EMPTY_Msk;
-}
-
-static inline void uart_write_buf(volatile CySCB_Type *uart, char *buf, size_t len) {
-	while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
-}
-
-static inline void rng_init(void) {
-}
-static inline uint32_t rng_read(void) {
-   return 0;
-}
-
-static inline void ethernet_init(void) {
-  gpio_init(PIN(26, 0), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_REF_CLK
-  gpio_init(PIN(26, 1), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TX_CTL
-  gpio_init(PIN(26, 2), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TX_CLK
-  gpio_init(PIN(26, 3), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_0
-  gpio_init(PIN(26, 4), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_1
-  gpio_init(PIN(26, 5), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_2
-  gpio_init(PIN(26, 6), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_3
-  gpio_init(PIN(26, 7), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_0
-
-  gpio_init(PIN(27, 0), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_1
-  gpio_init(PIN(27, 1), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_2
-  gpio_init(PIN(27, 2), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_3
-  gpio_init(PIN(27, 3), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RX_CTL
-  gpio_init(PIN(27, 4), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RX_CLK
-  gpio_init(PIN(27, 5), GPIO_MODE_INPUT, GPIO_STRONG, GPIO_SPEED_LOW, 0, 27); // ETH1_MDIO
-  gpio_init(PIN(27, 6), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_LOW, 0, 27); // ETH1_MDC
-  //gpio_init(PIN(27, 7), GPIO_MODE_OUTPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 0); // ETH1_RST
-
-  CPUSS->CM7_0_SYSTEM_INT_CTL[eth_1_interrupt_eth_0_IRQn] = 0x80000003; // assign CPU interrupt #3
-  NVIC->ISER[0] = 1 << 3;
-
-  spin(10000000); // artificial delay to wait for PHY init
-}
-
-static inline void clock_init(void) {
-  SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
-  asm("DSB");
-  asm("ISB");
-  
-  // configure PLL
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_BYPASS_SEL_Msk, BIT(29)); // First bypass PLL
-  spin(10);
-  SRSS->CLK_PLL400M[0].CONFIG &= ~CLK_PLL400M_CONFIG_ENABLE_Msk; // disable the PLL itself
-
-  // IMO source generates a frequency of 8MHz. The final frequency will be
-  // calculated as (CLK_IMO * feedback) / (reference * output_div)
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk, PLL_FEEDBACK << CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk, PLL_REF << CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk, PLL_OUT << CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_DIV_Msk, 0);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk, 0);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_EN_Msk, 1 << CLK_PLL400M_CONFIG2_FRAC_EN_Pos);
-  CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_BYPASS_SEL_Msk, 0);
-  spin(10);
-  SRSS->CLK_PLL400M[0].CONFIG |= CLK_PLL400M_CONFIG_ENABLE_Msk; // enable the PLL
-  while (SRSS->CLK_PLL400M[0].CONFIG & 1) spin(1);
-
-  // configure PATH1 with source set to IMO
-  SRSS->CLK_PATH_SELECT[1] = 0;
-
-  // enable CLK_HFx
-  uint8_t clocks[] = {0, 1, 2, 3, 4, 5, 6};
-  for (size_t i = 0; i < sizeof(clocks) / sizeof(uint8_t); i++) {
-    CLRSET(SRSS->CLK_ROOT_SELECT[clocks[i]], SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk, 1); // choose PATH1
-    CLRSET(SRSS->CLK_ROOT_SELECT[clocks[i]], SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk, 1 << SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos);
-    if (clocks[i] != 0) // CLF_HF0 is already enabled
-      SRSS->CLK_ROOT_SELECT[clocks[i]] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk; // enable clock root
-  }
-
-  // set systick frequency
-  uint32_t tenms = SYS_FREQUENCY / 100 - 1; // number of cycles executed in 10ms
-  CPUSS->SYSTICK_CTL = tenms | (3 << CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos); // select CLK_HF as source
-}

examples/infineon/infineon-xmc7200/link.ld

@@ -1,31 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(Reset_Handler)
-
-MEMORY
-{
-    flash(RX) : ORIGIN = 0x10080000, LENGTH = 0x80000
-    sram(!RX) : ORIGIN = 0x28000800, LENGTH = 510K
-}
-
-_estack     = ORIGIN(sram) + LENGTH(sram);
-
-SECTIONS
-{ 
-    .vectors  : { . = ALIGN(4); KEEP(*(.vectors)); . = ALIGN(4); } > flash
-    .text     : { *(.text*) } > flash
-    .rodata   : { *(.rodata*) } > flash
-
-    .data : {
-        _sdata = .;
-        *(.first_data)
-        *(.data SORT(.data.*))
-        _edata = .;
-    } > sram AT > flash
-    _sidata = LOADADDR(.data);
-
-    .bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram
-
-    . = ALIGN(8);
-    _end = .;
-}

examples/infineon/infineon-xmc7200/main.c

@@ -1,32 +0,0 @@
-// Copyright (c) 2024 Cesanta Software Limited
-// All rights reserved
-
-#include "hal.h"
-#include "mongoose.h"
-#include "net.h"
-
-#define BLINK_PERIOD_MS 1000
-
-static void timer_fn(void *arg) {
-  gpio_toggle(LED1);  // Blink LED
-  (void) arg;         // Unused
-}
-
-int main(void) {
-  struct mg_mgr mgr;  // Mongoose event manager
-
-  hal_init();  // Cross-platform hardware init
-  
-  mg_mgr_init(&mgr);        // Initialise it
-  mg_log_set(MG_LL_DEBUG);  // Set log level to debug
-  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mgr);
-
-  MG_INFO(("Initialising application..."));
-  web_init(&mgr);
-
-  for (;;) {
-    mg_mgr_poll(&mgr, 0);
-  }
-
-  return 0;
-}

examples/infineon/infineon-xmc7200/mongoose_config.h

@@ -1,26 +0,0 @@
-#pragma once
-
-// See https://mongoose.ws/documentation/#build-options
-#define MG_ARCH MG_ARCH_NEWLIB
-
-#define MG_ENABLE_TCPIP 1
-#define MG_ENABLE_DRIVER_XMC7 1
-#define MG_IO_SIZE 256
-#define MG_ENABLE_CUSTOM_MILLIS 1
-#define MG_ENABLE_CUSTOM_RANDOM 1
-#define MG_ENABLE_PACKED_FS 1
-
-// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
-// By default, those are set to zero, meaning that DHCP is used
-//
-// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
-// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
-// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
-
-// Set custom MAC address. By default, it is randomly generated
-// Using a build-time constant:
-// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0)
-//
-// Using custom function:
-// extern void my_function(unsigned char *mac);
-// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)

examples/infineon/infineon-xmc7200/startup.c

@@ -1,83 +0,0 @@
-#include "xmc7200d_e272k8384.h"
-
-void Reset_Handler(void);    // Defined below
-void Dummy_Handler(void);    // Defined below
-void SysTick_Handler(void);  // Defined in main.c
-void SystemInit(void);       // Defined in main.c, called by reset handler
-void _estack(void);          // Defined in link.ld
-
-#define WEAK_ALIAS __attribute__((weak, alias("Default_Handler")))
-
-WEAK_ALIAS void NMI_Handler(void);
-WEAK_ALIAS void HardFault_Handler(void);
-WEAK_ALIAS void SVCall_Handler(void);
-WEAK_ALIAS void PendSV_Handler(void);
-WEAK_ALIAS void SysTick_Handler(void);
-
-WEAK_ALIAS void Default_Intr_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr0_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr1_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr2_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr4_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr5_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr6_Handler(void);
-WEAK_ALIAS void CM0P_CpuIntr7_Handler(void);
-WEAK_ALIAS void ETH_IRQHandler(void);
-
-void CM0P_CpuIntr3_Handler(void) {
-	ETH_IRQHandler();
-}
-
-__attribute__((section(".vectors"))) void (*const tab[16 + 16])(void) = {
-	_estack,
-	Reset_Handler,
-	NMI_Handler,
-	HardFault_Handler,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	SVCall_Handler,
-	0,
-	0,
-	PendSV_Handler,
-	SysTick_Handler,
-	CM0P_CpuIntr0_Handler,
-	CM0P_CpuIntr1_Handler,
-	CM0P_CpuIntr2_Handler,
-	CM0P_CpuIntr3_Handler,
-	CM0P_CpuIntr4_Handler,
-	CM0P_CpuIntr5_Handler,
-	CM0P_CpuIntr6_Handler,
-	CM0P_CpuIntr7_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler,
-	Default_Intr_Handler
-};
-
-__attribute__((naked, noreturn)) void Reset_Handler(void) {
-  // Clear BSS section, and copy data section from flash to RAM
-  extern long _sbss, _ebss, _sdata, _edata, _sidata;
-  for (long *src = &_sbss; src < &_ebss; src++) *src = 0;
-  for (long *src = &_sdata, *dst = &_sidata; src < &_edata;) *src++ = *dst++;
-
-  SCB->VTOR = (uint32_t) &tab;
-  SystemInit();
-
-  // Call main()
-  extern void main(void);
-  main();
-  for (;;) (void) 0;  // Infinite loop
-}
-
-void Default_Handler(void) {
-  for (;;) (void) 0;
-}

examples/modbus-dashboard/certs

@@ -1 +0,0 @@
-../device-dashboard/certs

examples/modbus-dashboard/mongoose.c

@@ -1 +0,0 @@
-../../mongoose.c

examples/modbus-dashboard/mongoose.h

@@ -1 +0,0 @@
-../../mongoose.h

examples/modbus-dashboard/web_root/main.css

@@ -1 +0,0 @@
-/*! tailwindcss v3.3.5 | MIT License | https://tailwindcss.com*/*,:after,:before{box-sizing:border-box;border:0 solid #e5e7eb}:after,:before{--tw-content:""}html{line-height:1.5;-webkit-text-size-adjust:100%;-moz-tab-size:4;-o-tab-size:4;tab-size:4;font-family:Inter var,Helvetica,sans-serif;font-feature-settings:"cv11","ss01";font-variation-settings:"opsz" 32}body{margin:0;line-height:inherit}hr{height:0;color:inherit;border-top-width:1px}abbr:where([title]){-webkit-text-decoration:underline dotted;text-decoration:underline dotted}h1,h2,h3,h4,h5,h6{font-size:inherit;font-weight:inherit}a{color:inherit;text-decoration:inherit}b,strong{font-weight:bolder}code,kbd,pre,samp{font-family:ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,Liberation Mono,Courier New,monospace;font-size:1em}small{font-size:80%}sub,sup{font-size:75%;line-height:0;position:relative;vertical-align:initial}sub{bottom:-.25em}sup{top:-.5em}table{text-indent:0;border-color:inherit;border-collapse:collapse}button,input,optgroup,select,textarea{font-family:inherit;font-feature-settings:inherit;font-variation-settings:inherit;font-size:100%;font-weight:inherit;line-height:inherit;color:inherit;margin:0;padding:0}button,select{text-transform:none}[type=button],[type=reset],[type=submit],button{-webkit-appearance:button;background-color:initial;background-image:none}:-moz-focusring{outline:auto}:-moz-ui-invalid{box-shadow:none}progress{vertical-align:initial}::-webkit-inner-spin-button,::-webkit-outer-spin-button{height:auto}[type=search]{-webkit-appearance:textfield;outline-offset:-2px}::-webkit-search-decoration{-webkit-appearance:none}::-webkit-file-upload-button{-webkit-appearance:button;font:inherit}summary{display:list-item}blockquote,dd,dl,figure,h1,h2,h3,h4,h5,h6,hr,p,pre{margin:0}fieldset{margin:0}fieldset,legend{padding:0}menu,ol,ul{list-style:none;margin:0;padding:0}dialog{padding:0}textarea{resize:vertical}input::-moz-placeholder,textarea::-moz-placeholder{opacity:1;color:#9ca3af}input::placeholder,textarea::placeholder{opacity:1;color:#9ca3af}[role=button],button{cursor:pointer}:disabled{cursor:default}audio,canvas,embed,iframe,img,object,svg,video{display:block;vertical-align:middle}img,video{max-width:100%;height:auto}[hidden]{display:none}*,::backdrop,:after,:before{--tw-border-spacing-x:0;--tw-border-spacing-y:0;--tw-translate-x:0;--tw-translate-y:0;--tw-rotate:0;--tw-skew-x:0;--tw-skew-y:0;--tw-scale-x:1;--tw-scale-y:1;--tw-pan-x: ;--tw-pan-y: ;--tw-pinch-zoom: ;--tw-scroll-snap-strictness:proximity;--tw-gradient-from-position: ;--tw-gradient-via-position: ;--tw-gradient-to-position: ;--tw-ordinal: ;--tw-slashed-zero: ;--tw-numeric-figure: ;--tw-numeric-spacing: ;--tw-numeric-fraction: ;--tw-ring-inset: ;--tw-ring-offset-width:0px;--tw-ring-offset-color:#fff;--tw-ring-color:#3b82f680;--tw-ring-offset-shadow:0 0 #0000;--tw-ring-shadow:0 0 #0000;--tw-shadow:0 0 #0000;--tw-shadow-colored:0 0 #0000;--tw-blur: ;--tw-brightness: ;--tw-contrast: ;--tw-grayscale: ;--tw-hue-rotate: ;--tw-invert: ;--tw-saturate: ;--tw-sepia: ;--tw-drop-shadow: ;--tw-backdrop-blur: ;--tw-backdrop-brightness: ;--tw-backdrop-contrast: ;--tw-backdrop-grayscale: ;--tw-backdrop-hue-rotate: ;--tw-backdrop-invert: ;--tw-backdrop-opacity: ;--tw-backdrop-saturate: ;--tw-backdrop-sepia: }.sr-only{position:absolute;width:1px;height:1px;padding:0;margin:-1px;overflow:hidden;clip:rect(0,0,0,0);white-space:nowrap;border-width:0}.pointer-events-none{pointer-events:none}.pointer-events-auto{pointer-events:auto}.fixed{position:fixed}.absolute{position:absolute}.relative{position:relative}.sticky{position:sticky}.inset-0{inset:0}.bottom-0{bottom:0}.left-0{left:0}.right-auto{right:auto}.top-0{top:0}.z-10{z-index:10}.z-\[48\]{z-index:48}.z-\[60\]{z-index:60}.m-4{margin:1rem}.my-0{margin-top:0;margin-bottom:0}.my-1{margin-top:.25rem;margin-bottom:.25rem}.my-2{margin-top:.5rem;margin-bottom:.5rem}.mb-1{margin-bottom:.25rem}.ml-3{margin-left:.75rem}.ml-4{margin-left:1rem}.mr-2{margin-right:.5rem}.mt-1{margin-top:.25rem}.mt-2{margin-top:.5rem}.mt-3{margin-top:.75rem}.inline-block{display:inline-block}.flex{display:flex}.inline-flex{display:inline-flex}.grid{display:grid}.hidden{display:none}.h-10{height:2.5rem}.h-12{height:3rem}.h-5{height:1.25rem}.h-6{height:1.5rem}.h-full{height:100%}.max-h-64{max-height:16rem}.min-h-screen{min-height:100vh}.w-0{width:0}.w-11{width:2.75rem}.w-4{width:1rem}.w-5{width:1.25rem}.w-6{width:1.5rem}.w-72{width:18rem}.w-full{width:100%}.max-w-sm{max-width:24rem}.flex-1{flex:1 1 0%}.flex-shrink-0,.shrink-0{flex-shrink:0}.grow-0{flex-grow:0}.basis-\[30px\]{flex-basis:30px}.-translate-x-full{--tw-translate-x:-100%}.-translate-x-full,.translate-x-0{transform:translate(var(--tw-translate-x),var(--tw-translate-y)) rotate(var(--tw-rotate)) skewX(var(--tw-skew-x)) skewY(var(--tw-skew-y)) scaleX(var(--tw-scale-x)) scaleY(var(--tw-scale-y))}.translate-x-0{--tw-translate-x:0px}.translate-x-5{--tw-translate-x:1.25rem}.translate-x-5,.translate-y-0{transform:tranLine truncated

examples/mqtt-dashboard/dashboard/Makefile

@@ -1,14 +0,0 @@
-all:
-	make -C ../../../tutorials/http/http-server ARGS="-d $(CURDIR)"
-
-# Bundle JS libraries (preact, preact-router, ...) into a single file
-bundle.js:
-	curl -s https://npm.reversehttp.com/preact,preact/hooks,htm/preact,preact-router -o $@
-
-# Create optimised CSS. Prerequisite: npm -g i tailwindcss tailwindcss-font-inter
-NPX ?= npx
-main.css: index.html $(wildcard *.js)
-	$(NPX) tailwindcss -o $@ --minify
-
-clean:
-	true

examples/mqtt-dashboard/dashboard/main.css

@@ -1 +0,0 @@
-/*! tailwindcss v3.3.2 | MIT License | https://tailwindcss.com*/*,:after,:before{box-sizing:border-box;border:0 solid #e5e7eb}:after,:before{--tw-content:""}html{line-height:1.5;-webkit-text-size-adjust:100%;-moz-tab-size:4;-o-tab-size:4;tab-size:4;font-family:Inter var,Helvetica,sans-serif;font-feature-settings:"cv11","ss01";font-variation-settings:"opsz" 32}body{margin:0;line-height:inherit}hr{height:0;color:inherit;border-top-width:1px}abbr:where([title]){-webkit-text-decoration:underline dotted;text-decoration:underline dotted}h1,h2,h3,h4,h5,h6{font-size:inherit;font-weight:inherit}a{color:inherit;text-decoration:inherit}b,strong{font-weight:bolder}code,kbd,pre,samp{font-family:ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,Liberation Mono,Courier New,monospace;font-size:1em}small{font-size:80%}sub,sup{font-size:75%;line-height:0;position:relative;vertical-align:initial}sub{bottom:-.25em}sup{top:-.5em}table{text-indent:0;border-color:inherit;border-collapse:collapse}button,input,optgroup,select,textarea{font-family:inherit;font-size:100%;font-weight:inherit;line-height:inherit;color:inherit;margin:0;padding:0}button,select{text-transform:none}[type=button],[type=reset],[type=submit],button{-webkit-appearance:button;background-color:initial;background-image:none}:-moz-focusring{outline:auto}:-moz-ui-invalid{box-shadow:none}progress{vertical-align:initial}::-webkit-inner-spin-button,::-webkit-outer-spin-button{height:auto}[type=search]{-webkit-appearance:textfield;outline-offset:-2px}::-webkit-search-decoration{-webkit-appearance:none}::-webkit-file-upload-button{-webkit-appearance:button;font:inherit}summary{display:list-item}blockquote,dd,dl,figure,h1,h2,h3,h4,h5,h6,hr,p,pre{margin:0}fieldset{margin:0}fieldset,legend{padding:0}menu,ol,ul{list-style:none;margin:0;padding:0}textarea{resize:vertical}input::-moz-placeholder,textarea::-moz-placeholder{opacity:1;color:#9ca3af}input::placeholder,textarea::placeholder{opacity:1;color:#9ca3af}[role=button],button{cursor:pointer}:disabled{cursor:default}audio,canvas,embed,iframe,img,object,svg,video{display:block;vertical-align:middle}img,video{max-width:100%;height:auto}[hidden]{display:none}*,::backdrop,:after,:before{--tw-border-spacing-x:0;--tw-border-spacing-y:0;--tw-translate-x:0;--tw-translate-y:0;--tw-rotate:0;--tw-skew-x:0;--tw-skew-y:0;--tw-scale-x:1;--tw-scale-y:1;--tw-pan-x: ;--tw-pan-y: ;--tw-pinch-zoom: ;--tw-scroll-snap-strictness:proximity;--tw-gradient-from-position: ;--tw-gradient-via-position: ;--tw-gradient-to-position: ;--tw-ordinal: ;--tw-slashed-zero: ;--tw-numeric-figure: ;--tw-numeric-spacing: ;--tw-numeric-fraction: ;--tw-ring-inset: ;--tw-ring-offset-width:0px;--tw-ring-offset-color:#fff;--tw-ring-color:#3b82f680;--tw-ring-offset-shadow:0 0 #0000;--tw-ring-shadow:0 0 #0000;--tw-shadow:0 0 #0000;--tw-shadow-colored:0 0 #0000;--tw-blur: ;--tw-brightness: ;--tw-contrast: ;--tw-grayscale: ;--tw-hue-rotate: ;--tw-invert: ;--tw-saturate: ;--tw-sepia: ;--tw-drop-shadow: ;--tw-backdrop-blur: ;--tw-backdrop-brightness: ;--tw-backdrop-contrast: ;--tw-backdrop-grayscale: ;--tw-backdrop-hue-rotate: ;--tw-backdrop-invert: ;--tw-backdrop-opacity: ;--tw-backdrop-saturate: ;--tw-backdrop-sepia: }.pointer-events-none{pointer-events:none}.absolute{position:absolute}.relative{position:relative}.right-4{right:1rem}.top-0{top:0}.top-4{top:1rem}.my-1{margin-top:.25rem;margin-bottom:.25rem}.my-auto{margin-top:auto;margin-bottom:auto}.mb-4{margin-bottom:1rem}.mt-3{margin-top:.75rem}.inline-block{display:inline-block}.flex{display:flex}.inline-flex{display:inline-flex}.grid{display:grid}.hidden{display:none}.h-5{height:1.25rem}.h-6{height:1.5rem}.h-full{height:100%}.min-h-screen{min-height:100vh}.w-11{width:2.75rem}.w-24{width:6rem}.w-4{width:1rem}.w-5{width:1.25rem}.w-60{width:15rem}.w-64{width:16rem}.w-96{width:24rem}.w-full{width:100%}.max-w-md{max-width:28rem}.flex-1{flex:1 1 0%}.flex-shrink-0{flex-shrink:0}.flex-grow,.grow{flex-grow:1}.translate-x-0{--tw-translate-x:0px}.translate-x-0,.translate-x-5{transform:translate(var(--tw-translate-x),var(--tw-translate-y)) rotate(var(--tw-rotate)) skewX(var(--tw-skew-x)) skewY(var(--tw-skew-y)) scaleX(var(--tw-scale-x)) scaleY(var(--tw-scale-y))}.translate-x-5{--tw-translate-x:1.25rem}.transform{transform:translate(var(--tw-translate-x),var(--tw-translate-y)) rotate(var(--tw-rotate)) skewX(var(--tw-skew-x)) skewY(var(--tw-skew-y)) scaleX(var(--tw-scale-x)) scaleY(var(--tw-scale-y))}@keyframes spin{to{transform:rotate(1turn)}}.animate-spin{animation:spin 1s linear infinite}.cursor-pointer{cursor:pointer}.grid-cols-2{grid-template-columns:repeat(2,minmax(0,1fr))}.grid-cols-3{grid-template-columns:repeat(3,minmax(0,1fr))}.flex-col{flex-direction:column}.items-center{align-items:center}.justify-center{justify-content:center}.justify-between{justify-content:space-between}.gap-1{gap:.25rem}.gap-2{gap:.5rem}.gap-3{gap:.75rem}.gap-4{gap:1rem}.divide-y>:not([hidden])~:not([hidden]){--tw-divide-y-reverse:0;border-top-widtLine truncated

examples/mqtt-dashboard/dashboard/main.js

@@ -1,618 +0,0 @@
-'use strict';
-import {h, html, render, useEffect, useRef, useState} from './bundle.js';
-
-const Logo = props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" viewBox="0 0 12.87 12.85"><defs><style>.ll-cls-1{fill:none;stroke:#000;stroke-miterlimit:10;stroke-width:0.5px;}</style></defs><g id="Layer_2" data-name="Layer 2"><g id="Layer_1-2" data-name="Layer 1"><path class="ll-cls-1" d="M12.62,1.82V8.91A1.58,1.58,0,0,1,11,10.48H4a1.44,1.44,0,0,1-1-.37A.69.69,0,0,1,2.84,10l-.1-.12a.81.81,0,0,1-.15-.48V5.57a.87.87,0,0,1,.86-.86H4.73V7.28a.86.86,0,0,0,.86.85H9.42a.85.85,0,0,0,.85-.85V3.45A.86.86,0,0,0,10.13,3,.76.76,0,0,0,10,2.84a.29.29,0,0,0-.12-.1,1.49,1.49,0,0,0-1-.37H2.39V1.82A1.57,1.57,0,0,1,4,.25H11A1.57,1.57,0,0,1,12.62,1.82Z"/><path class="ll-cls-1" d="M10.48,10.48V11A1.58,1.58,0,0,1,8.9,12.6H1.82A1.57,1.57,0,0,1,.25,11V3.94A1.57,1.57,0,0,1,1.82,2.37H8.9a1.49,1.49,0,0,1,1,.37l.12.1a.76.76,0,0,1,.11.14.86.86,0,0,1,.14.47V7.28a.85.85,0,0,1-.85.85H8.13V5.57a.86.86,0,0,0-.85-.86H3.45a.87.87,0,0,0-.86.86V9.4a.81.81,0,0,0,.15.48l.1.12a.69.69,0,0,0,.13.11,1.44,1.44,0,0,0,1,.37Z"/></g></g></svg>`;
-const DefaultTopic = 'mg_mqtt_dashboard';
-const DefaultUrl = location.protocol == 'https:'
-  ? 'wss://broker.hivemq.com:8884/mqtt'
-  : 'ws://broker.hivemq.com:8000/mqtt';
-const DefaultDeviceConfig = {pin_map: [], pin_state: [], log_level: 0, pin_count: 0};
-const Delay = (ms, val) => new Promise(resolve => setTimeout(resolve, ms, val));
-const handleFetchError = r => r.ok || alert(`Error: ${r.statusText}`);
-const LabelClass = 'text-sm truncate text-gray-500 font-medium my-auto whitespace-nowrap';
-const BadgeClass = 'flex-inline text-sm rounded-md rounded px-2 py-0.5 ring-1 ring-inset';
-const InputClass = 'font-normal text-sm rounded w-full flex-1 py-0.5 px-2 text-gray-700 placeholder:text-gray-400 focus:outline-none disabled:cursor-not-allowed disabled:bg-gray-100 disabled:text-gray-500 rounded border';
-const TitleClass = 'font-semibold xuppercase xtext-gray-600';
-const Colors = {
-  green: 'bg-green-100 text-green-900 ring-green-300',
-  yellow: 'bg-yellow-100 text-yellow-900 ring-yellow-300',
-  info: 'bg-zinc-100 text-zinc-900 ring-zinc-300',
-  red: 'bg-red-100 text-red-900 ring-red-300',
-};
-
-let MqttClient;
-
-const Icons = {
-  logo: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="59.1" height="75.7"  viewBox="0 0 1514 1182"> <path style="fill: #2f409a;" d="m52.8 572h345.1v346.5h-345.1zm-10.9-434.2c-12.6 6.4-32.2 20.9-35.5 37.9 0 0-6.1 35.9-6.1 36.8-2.1 13.1 10.5 10 15.8 6.7 53.9-31.8 113.9-60.7 168.7-77.5 258.2-78.2 585.9-80.2 643.1 88.8 40.3 117.1-123.6 214.8-216.1 258.4-35.7 16.8-47.6 32.8-50 49.8-2 15.3 3.2 37.8 23.8 68.3 129.7 194.8 515 474 893.1 571.7 15.7 4.2 23.5 2.8 29.9-1.1 3.5-2 7.9-4.8 1.1-8.2-251.1-132.2-490.9-353.9-610.9-525.1-27.4-39.5-34.5-65.9-32.7-87.2 1.7-18.4 18.7-34.5 54.8-51.4 134.1-62.3 270.9-157.1 230-314.9-59.5-226.9-700.5-260.1-1109-53z"/></svg>`,
-  activity: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24" width="24" height="24"  fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><polyline points="22 12 18 12 15 21 9 3 6 12 2 12"></polyline></svg>`,
-  refresh: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24" width="24" height="24"  fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><polyline points="23 4 23 10 17 10"></polyline><polyline points="1 20 1 14 7 14"></polyline><path d="M3.51 9a9 9 0 0 1 14.85-3.36L23 10M1 14l4.64 4.36A9 9 0 0 0 20.49 15"></path></svg>`,
-  info: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24" width="24" height="24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><circle cx="12" cy="12" r="10"></circle><line x1="12" y1="8" x2="12" y2="12"></line><line x1="12" y1="16" x2="12.01" y2="16"></line></svg>`,
-  login: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><path d="M15 3h4a2 2 0 0 1 2 2v14a2 2 0 0 1-2 2h-4"></path><polyline points="10 17 15 12 10 7"></polyline><line x1="15" y1="12" x2="3" y2="12"></line></svg>`,
-  logout: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><path d="M9 21H5a2 2 0 0 1-2-2V5a2 2 0 0 1 2-2h4"></path><polyline points="16 17 21 12 16 7"></polyline><line x1="21" y1="12" x2="9" y2="12"></line></svg>`,
-  menu: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><line x1="3" y1="12" x2="21" y2="12"></line><line x1="3" y1="6" x2="21" y2="6"></line><line x1="3" y1="18" x2="21" y2="18"></line></svg>`,
-  upload: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><path d="M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4"></path><polyline points="17 8 12 3 7 8"></polyline><line x1="12" y1="3" x2="12" y2="15"></line></svg>`,
-  monitor: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><rect x="2" y="3" width="20" height="14" rx="2" ry="2"></rect><line x1="8" y1="21" x2="16" y2="21"></line><line x1="12" y1="17" x2="12" y2="21"></line></svg>`,
-  settings: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><circle cx="12" cy="12" r="3"></circle><path d="M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z"></path></svg>`,
-  download: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><path d="M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4"></path><polyline points="7 10 12 15 17 10"></polyline><line x1="12" y1="15" x2="12" y2="3"></line></svg>`,
-  file: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><path d="M13 2H6a2 2 0 0 0-2 2v16a2 2 0 0 0 2 2h12a2 2 0 0 0 2-2V9z"></path><polyline points="13 2 13 9 20 9"></polyline></svg>`,
-  check: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><polyline points="20 6 9 17 4 12"></polyline></svg>`,
-  rollback: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><polyline points="11 17 6 12 11 7"></polyline><polyline points="18 17 13 12 18 7"></polyline></svg>`,
-  save: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><path d="M19 21H5a2 2 0 0 1-2-2V5a2 2 0 0 1 2-2h11l5 5v11a2 2 0 0 1-2 2z"></path><polyline points="17 21 17 13 7 13 7 21"></polyline><polyline points="7 3 7 8 15 8"></polyline></svg>`,
-  bolt: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><polygon points="13 2 3 14 12 14 11 22 21 10 12 10 13 2"></polygon></svg>`,
-  delete: props => html`<svg class=${props.class} xmlns="http://www.w3.org/2000/svg" width="24" height="24" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round"><line x1="18" y1="6" x2="6" y2="18"></line><line x1="6" y1="6" x2="18" y2="18"></line></svg>`,
-};
-
-export function Button({title, onclick, disabled, extraClass, icon, ref, colors, hovercolor, disabledcolor}) {
-  const [spin, setSpin] = useState(false);
-  const cb = function(ev) {
-    const res = onclick ? onclick() : null;
-    if (res && typeof (res.catch) === 'function') {
-      setSpin(true);
-      res.catch(() => false).then(() => setSpin(false));
-    }
-  };
-  if (!colors) colors = 'bg-blue-600 hover:bg-blue-500 disabled:bg-blue-400';
-  return html`
-<button type="button" class="inline-flex justify-center items-center gap-2 rounded px-2.5 py-0.5 text-sm font-semibold text-white shadow-sm ${colors} ${extraClass}"
-  ref=${ref} onclick=${cb} disabled=${disabled || spin} >
-  ${title}
-  <${spin ? Icons.refresh : icon} class="w-4 ${spin ? 'animate-spin' : ''}" />
-<//>`
-};
-
-function UploadFileButton({oncomplete, onprogress, onfileselect, url, title, colors, accept, extraClass}) {
-  const btn = useRef(null);
-  const input = useRef(null);
-
-  // Send a large file chunk by chunk
-  const sendFileData = function(url, fileName, fileData, chunkSize) {
-    return new Promise(function(resolve, reject) {
-      const finish = ok => {
-        input.fn = null;
-        const res = oncomplete ? oncomplete(ok, fileName, fileData.length) : null;
-        if (res && typeof (res.catch) === 'function') {
-          res.catch(() => false).then(() => ok ? resolve() : reject());
-        } else {
-          ok ? resolve() : reject();
-        }
-      };
-      const sendChunk = function(offset) {
-        var chunk = fileData.subarray(offset, offset + chunkSize) || '';
-        var opts = {method: 'POST', body: chunk};
-        var fullUrl = url + '?offset=' + offset +
-          '&total=' + fileData.length  +
-          '&file=' + encodeURIComponent(fileName);
-        onprogress && onprogress(offset, fileData.length, fileName);
-        fetch(fullUrl, opts)
-          .then(function(res) {
-            if (!res.ok) {
-              finish(false);
-            } else if (offset >= fileData.length) {
-              finish(true);
-            } else {
-              sendChunk(offset + chunk.length);
-            }
-          });
-      };
-      sendChunk(0);
-    });
-  };
-
-  const onchange = function(ev) {
-    if (!ev.target.files[0]) return;
-    let r = new FileReader(), f = ev.target.files[0];
-    if (onfileselect && !onfileselect(f.name)) {
-      ev.target.value = '';
-      return;
-    }
-    r.readAsArrayBuffer(f);
-    r.onload = function() {
-      input.fn = sendFileData(url, f.name, new Uint8Array(r.result), 2048);
-      ev.target.value = '';
-      ev.preventDefault();
-      btn.current && btn.current.base.click();
-    };
-  };
-
-  const onclick = function(ev) {
-    //if (!input.fn) input.current.click();  // No upload in progress, show file dialog
-  };
-
-  return html`
-<div class="inline-flex flex-col ${extraClass}">
-  <input class="hidden" type="file" ref=${input} onchange=${onchange} accept=${accept} />
-  <${Button} title=${title} icon=${Icons.download} onclick=${onclick} ref=${btn} colors=${colors} />
-<//>`;
-};
-
-function Toggle({value, onclick, disabled}) {
-  const bg = !!value ? 'bg-blue-600' : 'bg-gray-200';
-  const tr = !!value ? 'translate-x-5' : 'translate-x-0';
-  return html`
-<button type="button" onclick=${onclick} disabled=${disabled}
-  class="${bg} inline-flex h-6 w-11 flex-shrink-0 cursor-pointer rounded-full border-2 border-transparent transition-colors duration-200 ease-in-out focus:outline-none focus:ring-0 ring-0"
-  role="switch" aria-checked=${!!value}>
-  <span aria-hidden="true" class="${tr} pointer-events-none inline-block h-5 w-5 transform rounded-full bg-white shadow ring-0 focus:ring-0 transition duration-200 ease-in-out"></span>
-</button>`;
-};
-
-function Header({topic, setTopic, url, setUrl, connected}) {
-  const forbiddenChars = ['$', '*', '+', '#', '/'];
-  const onClick = () => {
-    const isValidTopic = val => !forbiddenChars.some(char => val.includes(char));
-    if (isValidTopic(topic)) {
-      localStorage.setItem('topic', topic)
-      setTopic(topic);
-      window.location.reload();
-    } else {
-      setSaveResult('Error: The topic cannot contain these characters: ' + forbiddenChars);
-    }
-  };
-
-  return html`
-    <div class="top-0 py-2 border-b-2 bg-stone-100">
-      <div class="flex px-4">
-        <div class="flex grow gap-4">
-          <h1 class="text-2xl font-semibold">IoT Fleet Management Dashboard</h1>
-        <//>
-        <div class="flex gap-2 items-center">
-          <div class="flex w-96 align-center justify-between gap-2">
-            <span class=${LabelClass}>MQTT Server<//>
-            <input disabled=${!connected} value=${url}
-              onchange=${ev => setUrl(ev.target.value)} class=${InputClass} />
-          <//>
-          <div class="flex w-64 align-center justify-between gap-2">
-            <span class=${LabelClass}>Root Topic<//>
-            <input disabled=${!connected} value=${topic}
-              onchange=${ev => setTopic(ev.target.value)} class=${InputClass} />
-          <//>
-          <${Button} icon=${Icons.bolt} onclick=${onClick} title=${connected ? 'Disconnect' : 'Connect'} />
-        <//>
-      <//>
-    <//>`;
-};
-
-function Sidebar({devices, onclick}) {
-  const Td = props => html`
-    <td class="whitespace-nowrap border-b border-slate-200 py-2 px-4 pr-3 text-sm text-slate-900">${
-      props.text}</td>`;
-
-  const Device = ({d}) => html`
-    <div class="hover:bg-stone-100 cursor-pointer flex gap-3 px-4 py-2 justify-between"
-        onclick=${ev => onclick(d.id)}>
-      <span>${d.id}</span>
-      <span class="${BadgeClass} ${d.online ? Colors.green : Colors.red}"> ${d.online ? 'online' : 'offline'} <//>
-    <//>`;
-
-  return html`
-    <div class="overflow-auto divide-y">
-      <div class="${TitleClass} flex items-center px-4 py-2 bg-stone-100">
-        Device List
-      <//>
-      ${(devices ? devices : []).map(d => h(Device, {d}))}
-    <//>`;
-};
-
-function FirmwareStatus({title, info, children}) {
-  const state =
-      ['UNAVAILABLE', 'FIRST_BOOT', 'NOT_COMMITTED',
-       'COMMITTED'][(info.status || 0) % 4];
-  const valid = info.status > 0;
-  return html`
-    <div class="bg-white divide-y border rounded">
-      <div class="${TitleClass} bg-white flex items-center px-4 py-2">
-        ${title}
-      <//>
-      <div class="px-4 py-2 relative">
-      <div class="my-1">Status: ${state}<//>
-      <div class="my-1">CRC32: ${valid ? info.crc32.toString(16) : 'n/a'}<//>
-      <div class="my-1">Size: ${valid ? info.size : 'n/a'}<//>
-      <div class="my-1">Flashed at: ${
-      valid ? new Date(info.timestamp * 1000).toLocaleString() : 'n/a'}<//>
-      ${children}
-      <//>
-    <//>`;
-};
-
-function FirmwareUpdatePanel({no, name, current, previous, updated_at, refresh}) {
-  const [color, setColor] = useState(Colors.green);
-  const [otaStatus, setOtaStatus] = useState('up-to-date');
-  const Descr = ({label, value}) => html`
-    <div class="flex items-center justify-between">
-      <span class=${LabelClass}>${label}<//>
-      <span class="text-sm">${value}<//>
-    <//>`;
-  const onprogress = (len, total) => {
-    setColor(Colors.info);
-    setOtaStatus(`uploading, ${parseInt(len * 100 /total)}% done...`);
-  }
-  const setparam = (key, val) => fetch('api/settings/set', {
-    method: 'POST',
-    body: JSON.stringify({key, val}),
-  }).then(handleFetchError);
-  const onupload = function(ok, fileName, fileLength) {
-    if (ok) {
-      return setparam(`ecu.${no}.new`, fileName).then(refresh);
-    } else {
-      setColor(Colors.red), setOtaStatus('upload failed');
-    }
-  };
-  const onfileselect = function(fileName, fileLength) {
-    const ok = fileName.startsWith(name);
-    if (!ok) alert(`Firmware file name must be ${name}.VERSION.BIN_OR_HEX`);
-    return ok;
-  }
-  const update = rollback => new Promise(function(resolve, reject) {
-    const opts = {method: 'POST', body: JSON.stringify({no, rollback})};
-    const fail = () => (reject(), setOtaStatus('update error'), setColor(Colors.red));
-    const finish = () => fetch('api/ecu/update/end', opts)
-      .then(r => r.ok ? resolve() : reject())
-      .then(refresh);
-    const write = () => fetch('api/ecu/update/write', opts).then(r => {
-      if (!r.ok) fail();
-      //if (r.ok) r.json().then(r => console.log('Goo', r));
-      if (r.ok) r.json().then(r => r == 1 ? write() : finish());
-    });
-    fetch('api/ecu/update/begin', opts).then(r => r.ok ? write() : fail());
-  });
-  const onflash = ev => update(false);
-  const onrollback = ev => update(true);
-
-  useEffect(function() {
-    //setOtaStatus(anew ? 'update pending' : 'up-to-date');
-    //setColor(anew ? Colors.yellow : Colors.green);
-  }, []);
-
-  return html`
-<div class="divide-y border rounded bg-white">
-  <div class="px-4 py-2 flex justify-between items-center rounded">
-    <span class="${TitleClass}">Firmware Update<//>
-    <div class="flex gap-2"><span class=${LabelClass}>Status:</span><span class="${BadgeClass} ${color}">${otaStatus}<//><//>
-  <//>
-  <div class="p-4 flex flex-col gap-1">
-    <${Descr} label="Current firmware:" value=${current || 'n/a'} />
-    <${Descr} label="Updated at:" value=${updated_at || 'n/a'} />
-    <div class="flex items-center justify-between whitespace-nowrap">
-      <span class=${LabelClass}>Previous firmware:<//>
-      <span class="flex gap-1 items-center">
-        <span class="text-sm">${previous}<//>
-        <${Button} title="rollback" icon=${Icons.bolt} onclick=${onrollback}
-          extraClass="w-24" disabled=${!previous} />
-      <//>
-    <//>
-    <div class="flex items-center justify-between">
-      <span class=${LabelClass}>New firmware:<//>
-      <span class="flex gap-1 align-center justify-between">
-        <${UploadFileButton} title="upload" url="api/fw/upload"
-          onfileselect=${onfileselect} 
-          onprogress=${onprogress} oncomplete=${onupload} />
-        <${Button} title="flash" icon=${Icons.bolt} onclick=${onflash}
-          extraClass="w-24" disabled=${!previous} />
-      <//>
-    <//>
-  <//>
-<//>`;
-};
-
-function DeviceSettingsPanel({device, publishFn, connected}) {
-  const [config, setConfig] = useState({});
-  const logOptions = [[0, 'Disable'], [1, 'Error'], [2, 'Info'], [3, 'Debug']];
-
-  const onSave = ev => publishFn('config.set', config).then(r => {
-    //setDeviceConfig(device.id, config);
-  }).catch(e => alert('Failure!'));
-
-  // To delete device, set an empty retained message
-  const onforget = function(ev) {
-    MqttClient.publish(device.topic, '', {retain: true});
-    location.reload();
-  };
-  const onloglevelchange = ev => setConfig(x => Object.assign({}, x, {log_level: parseInt(ev.target.value)}));
-  const onpinschange = ev => {
-    const pin_map = ev.target.value.split(/\s*,\s*/).map(x => parseInt(x));
-    setConfig(x => Object.assign({}, x, {
-      pin_map,                   // Send an updated pin map
-      pin_count: pin_map.length, // And pin count
-      pin_state:[]    // Remove pin_state from the request, as pin_map change can invalidate it
-    }));
-  }
-  //console.log('sp', device, config);
-
-  useEffect(() => setConfig(device.config) , [device]);
-
-  return html`
-<div class="divide-y border rounded bg-white">
-  <div class="px-4 py-2 flex justify-between items-center rounded ${TitleClass}">
-    <div class="flex gap-2 items-center"> Settings <//>
-  <//>
-  <div class="p-4 gap-3">
-    <div class="flex justify-between my-1">
-      <span class=${LabelClass}>Status<//>
-      <span class="${BadgeClass} ${device.online ? Colors.green : Colors.red}"> ${connected ? 'online' : 'offline'} <//>
-    <//>
-    <div class="flex justify-between my-1">
-      <span class=${LabelClass}>Device ID<//>
-      <span class="${LabelClass}">${device.id}<//>
-    <//>
-    <div class="grid grid-cols-2 my-1">
-      <span class="${LabelClass}">Log Level<//>
-      <select onchange=${onloglevelchange} class="w-full rounded font-normal border py-0.5 px-1 text-gray-600 focus:outline-none text-sm disabled:cursor-not-allowed" disabled=${!connected}>
-        ${logOptions.map(v => html`<option value=${v[0]} selected=${v[0] == config.log_level}>${v[1]}<//>`) }
-      <//>
-    <//>
-    <div class="grid grid-cols-2 my-1">
-      <span class="${LabelClass}">Show Pins<//>
-      <div class="flex w-full items-center">
-        <input disabled=${!connected} value=${config.pin_map}
-          onchange=${onpinschange} class=${InputClass}
-          placeholder="comma-separated pin numbers" />
-      <//>
-    <//>
-
-    <div class="mt-3 flex justify-between gap-2">
-      <${Button} title="Forget this device"
-        disabled=${device.online || !connected} icon=${Icons.delete}
-        onclick=${onforget}/>
-      <${Button} icon=${Icons.save} onclick=${onSave} title="Save Settings" disabled=${!device.online} />
-    <//>
-  <//>
-<//> `;
-};
-
-function DeviceControlPanel({device, config, setConfig, publishFn, connected}) {
-  const onclick = function(i) { // Send request to toggle pin i
-    let configCopy = Object.assign({}, config);
-    configCopy.pin_state[i] = !!configCopy.pin_state[i] ? 0 : 1;
-    return publishFn('config.set', configCopy).catch(e => alert('Failure!'));
-  };
-
-  const Pin = i =>  html`
-  <div class="inline-block my-1 bg-gray-100 rounded px-1 py-1">
-    <div class="flex align-center justify-between">
-      <span class="${LabelClass}">Pin ${config.pin_map[i]}<//>
-      <${Toggle} onclick=${ev => onclick(i)}
-        disabled=${!device.online || !connected}
-        value=${config.pin_state[i]} />
-    <//>
-  <//>`;
-
-  return html`
-<div class="divide-y border rounded bg-white xbg-slate-100 my-y">
-  <div class="px-4 py-2 flex justify-between items-center rounded ${TitleClass}">
-    <div class="flex gap-2 items-center">Pin Control Panel<//>
-  <//>
-  <div class="p-4 grid grid-cols-2 lg:grid-cols-3 gap-2">
-    ${(config.pin_map || []).map((_, i) => Pin(i))}
-   <div><//>
-  <//>
-<//> `;
-};
-
-function DeviceDashboard({device, setDeviceConfig, publishFn, connected}) {
-  const cfg = device && device.config ? device.config : DefaultDeviceConfig;
-  const [localConfig, setLocalConfig] = useState(cfg);
-  useEffect(() => setLocalConfig(cfg), [device]);
-
-  if (!device || !localConfig) {
-    return html`
-    <div class="flex grow text-gray-400 justify-center items-center text-xl">
-      No device selected. Click on a device on a sidebar
-    <//>`;
-  }
-
-  return html`
-  <div class="p-3 grid grid-cols-3 gap-2">
-    <${DeviceSettingsPanel} device=${device} config=${localConfig} setConfig=${setLocalConfig} publishFn=${publishFn} connected=${connected} />
-    <${DeviceControlPanel} device=${device} config=${localConfig} setConfig=${setLocalConfig} publishFn=${publishFn} connected=${connected} />
-    <${FirmwareUpdatePanel} deviceID=${device.id} publishFn=${publishFn}
-      disabled=${!device.online}
-      info=${[localConfig.crnt_fw, localConfig.prev_fw]} />
-  </div>`;
-}
-
-const App = function() {
-  const [devices, setDevices] = useState([]);
-  const [currentDevID, setCurrentDevID] = useState(localStorage.getItem('currentDevID') || '');
-  const [loading, setLoading] = useState(true);
-  const [url, setUrl] = useState(localStorage.getItem('url') || DefaultUrl);
-  const [topic, setTopic] = useState(localStorage.getItem('topic') || DefaultTopic);
-  const [error, setError] = useState(null);
-  const [connected, setConnected] = useState(false);
-  const responseHandlers = useRef({});
-
-  function addResponseHandler(correlationId, handler) {
-    responseHandlers[correlationId] = handler;
-  }
-
-  function removeResponseHandler(correlationId) {
-    delete responseHandlers[correlationId];
-  }
-
-  const onRefresh = ev => window.location.reload();
-
-  const initConn = () => {
-    MqttClient = mqtt.connect(url, {connectTimeout: 5000, reconnectPeriod: 0});
-
-    MqttClient.on('connect', () => {
-      //console.log('Connected to the broker');
-      setLoading(false);
-      setError(null);  // Reset error state upon successful connection
-      setConnected(true);
-
-      const statusTopic = topic + '/+/status'
-      const txTopic = topic + '/+/tx'
-
-      const subscribe = (topic) => {
-        MqttClient.subscribe(topic, (err) => {
-          if (err) {
-            console.error('Error subscribing to topic:', err);
-            setError('Error subscribing to topic');
-          } else {
-            //console.log('Successfully subscribed to ', topic);
-          }
-        });
-      };
-
-      subscribe(statusTopic);
-      subscribe(txTopic);
-    });
-
-    MqttClient.on('message', (topic, message) => {
-      // console.log(`Received message from ${topic}: ${message.toString()}`);
-      if (message.length == 0) return;
-      let response;
-      try {
-        response = JSON.parse(message.toString());
-      } catch (err) {
-        console.error(err);
-        return;
-      }
-
-      if (topic.endsWith('/status')) {
-        let device = {topic: topic, id: topic.split('/')[1], config: DefaultDeviceConfig};
-        const params = response.params;
-        if (!params) {
-          console.error('Invalid response');
-          return;
-        }
-        device.online = params.status === 'online';
-        //setConnected(device.online);
-        if (device.online) {
-          device.config = params;
-          if (!device.config.pins) device.config.pins = [];
-        }
-        setDevice(device)
-      } else if (topic.endsWith('/tx')) {
-        if (!response.id) {
-          console.error('Invalid response');
-          return;
-        }
-        const handler = responseHandlers[response.id];
-        if (handler) {
-          handler(response);
-          removeResponseHandler(response.id);
-        }
-      }
-    });
-
-    MqttClient.on('error', (err) => {
-      console.error('Connection error:', err);
-      setError('Connection cannot be established.');
-    });
-
-    MqttClient.on('close', () => {
-      if (!connected) {
-        console.error('Failed to connect to the broker.');
-        setError('Connection cannot be established.');
-        setLoading(false);
-      }
-    });
-  };
-
-  useEffect(() => initConn(), []);
-
-  const handlePublish = (methodName, parameters, timeout = 5000) => {
-    return new Promise((resolve, reject) => {
-      const randomIdGenerator = function(length) {
-        return Math.random().toString(36).substring(2, length + 2);
-      };
-      const randomID = randomIdGenerator(40);
-      const timeoutID = setTimeout(() => {
-        removeResponseHandler(randomID);
-        reject(new Error('Request timed out'));
-      }, timeout);
-
-      addResponseHandler(randomID, (messageData) => {
-        clearTimeout(timeoutID);
-        resolve(messageData);
-      });
-
-      if (currentDevID) {
-        const rxTopic = topic + `/${currentDevID}/rx`;
-        const rpcPayload = {method: methodName, id: randomID};
-        if (parameters) {
-          rpcPayload.params = parameters;
-        }
-        MqttClient.publish(rxTopic, JSON.stringify(rpcPayload));
-      }
-    });
-  };
-
-  const getDeviceByID = (deviceID) => devices.find(d => d.id === deviceID);
-
-  const setDevice = (devData) => {
-    setDevices(prevDevices => {
-      const devIndex =
-          prevDevices.findIndex(device => device.id === devData.id);
-      if (devIndex !== -1) {
-        if (!devData.online && !devData.config) {
-          const updatedDevices = [...prevDevices];
-          updatedDevices[devIndex].online = false;
-          return updatedDevices;
-        } else {
-          return prevDevices.map(device => device.id === devData.id ? devData : device);
-        }
-      } else {
-        return [...prevDevices, devData];
-      }
-    });
-  };
-
-  const setDeviceConfig = (deviceID, config) => {
-    setDevices(prevDevices => {
-      return prevDevices.map(device => {
-        if (device.id === deviceID) {
-          return {...device, config: config};
-        }
-        return device;
-      });
-    });
-  };
-
-  const onDeviceClick = (deviceID) => {
-    const device = getDeviceByID(deviceID);
-    if (device) {
-      setCurrentDevID(device.id);
-      localStorage.setItem('currentDevID', device.id);
-    }
-  };
-
-  if (error) {
-    return html`
-    <div class="min-h-screen bg-slate-100 flex flex-col">
-      <${Header}/>
-      <div class="flex-grow flex items-center justify-center">
-        <div class="bg-slate-300 p-8 rounded-lg shadow-md w-full max-w-md">
-          <h1 class="text-2xl font-bold text-gray-700 mb-4 text-center">Connection Error</h1>
-          <p class="text-gray-600 text-center mb-4">
-            Unable to connect to the MQTT broker.
-          </p>
-          <div class="text-center relative">
-            <${Button} title="Retry" onclick=${onRefresh}
-              icon=${Icons.refresh} class="absolute top-4 right-4" />
-          </div>
-        </div>
-      </div>
-    </div>`;
-  }
-
-  return html`
-  <div class="h-full flex flex-col">
-    <${Header}
-      topic=${topic} setTopic=${setTopic} url=${url}
-      setUrl=${setUrl} connected=${connected}
-    />
-    <div class="flex grow overflow-auto">
-      <div class="w-60 overflow-auto">
-        <${Sidebar} devices=${devices} onclick=${onDeviceClick} />
-      <//>
-      <div class="grow bg-gray-200">
-        <${DeviceDashboard}
-          device=${getDeviceByID(currentDevID)} connected=${connected}
-          setDeviceConfig=${setDeviceConfig} publishFn=${handlePublish} />
-      <//>
-    <//>
-  <//>`;
-};
-
-window.onload = () => render(h(App), document.body);

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/.cproject

@@ -1,727 +0,0 @@
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-				<externalSettings/>
-				<extensions>
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-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
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-					<folderInfo id="com.crt.advproject.config.exe.debug.1734776104." name="/" resourcePath="">
-						<toolChain id="com.crt.advproject.toolchain.exe.debug.1314174334" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
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-								<option id="com.crt.advproject.link.cpp.scriptdir.321354453" name="Script path" superClass="com.crt.advproject.link.cpp.scriptdir"/>
-								<option id="com.crt.advproject.link.cpp.crpenable.28733158" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.cpp.crpenable"/>
-								<option id="com.crt.advproject.link.cpp.flashconfigenable.191702633" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.cpp.flashconfigenable" value="true" valueType="boolean"/>
-								<option id="com.crt.advproject.link.cpp.ecrp.746927503" name="Enhanced CRP" superClass="com.crt.advproject.link.cpp.ecrp"/>
-								<option id="com.crt.advproject.link.cpp.hdrlib.518184354" name="Library" superClass="com.crt.advproject.link.cpp.hdrlib" value="com.crt.advproject.cpp.link.hdrlib.newlibnano.nohost" valueType="enumerated"/>
-								<option id="com.crt.advproject.link.cpp.nanofloat.617671751" name="Enable printf float " superClass="com.crt.advproject.link.cpp.nanofloat"/>
-								<option id="com.crt.advproject.link.cpp.nanofloat.scanf.956936851" name="Enable scanf float " superClass="com.crt.advproject.link.cpp.nanofloat.scanf"/>
-								<option id="com.crt.advproject.link.cpp.toram.979053468" name="Link application to RAM" superClass="com.crt.advproject.link.cpp.toram"/>
-								<option id="com.crt.advproject.link.memory.load.image.cpp.1374002335" name="Plain load image" superClass="com.crt.advproject.link.memory.load.image.cpp"/>
-								<option id="com.crt.advproject.link.memory.heapAndStack.style.cpp.170403685" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style.cpp"/>
-								<option id="com.crt.advproject.link.cpp.stackOffset.164787023" name="Stack offset" superClass="com.crt.advproject.link.cpp.stackOffset"/>
-								<option id="com.crt.advproject.link.memory.heapAndStack.cpp.1453885365" name="Heap and Stack options" superClass="com.crt.advproject.link.memory.heapAndStack.cpp"/>
-								<option id="com.crt.advproject.link.memory.data.cpp.541005693" name="Global data placement" superClass="com.crt.advproject.link.memory.data.cpp"/>
-								<option id="com.crt.advproject.link.memory.sections.cpp.30290797" name="Extra linker script input sections" superClass="com.crt.advproject.link.memory.sections.cpp"/>
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-								<option id="com.crt.advproject.link.cpp.multicore.master.userobjs.1885576571" name="Slave Objects (not visible)" superClass="com.crt.advproject.link.cpp.multicore.master.userobjs"/>
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-								<option id="com.crt.advproject.link.cpp.sgstubenable.1081286904" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.sgstubenable"/>
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-							</tool>
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-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.other.442353422" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" valueType="stringList">
-									<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
-									<listOptionValue builtIn="false" value="--gc-sections"/>
-									<listOptionValue builtIn="false" value="-print-memory-usage"/>
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-								<option id="com.crt.advproject.link.gcc.lto.1172603322" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.gcc.lto"/>
-								<option id="com.crt.advproject.link.gcc.lto.optmization.level.654522082" name="Link-time optimization level" superClass="com.crt.advproject.link.gcc.lto.optmization.level"/>
-								<option id="com.crt.advproject.link.fpu.1804104837" name="Floating point" superClass="com.crt.advproject.link.fpu" value="com.crt.advproject.link.fpu.fpv5sp.hard" valueType="enumerated"/>
-								<option id="com.crt.advproject.link.manage.1894077431" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
-								<option id="com.crt.advproject.link.script.691898559" name="Linker script" superClass="com.crt.advproject.link.script" value="frdm-mcxn947-xpresso-baremetal-builtin_Release.ld" valueType="string"/>
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-								<option id="com.crt.advproject.link.gcc.hdrlib.259676509" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.nohost" valueType="enumerated"/>
-								<option id="com.crt.advproject.link.gcc.nanofloat.1561655442" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat"/>
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-								<option id="com.crt.advproject.link.toram.1828994601" name="Link application to RAM" superClass="com.crt.advproject.link.toram"/>
-								<option id="com.crt.advproject.link.stackOffset.1818645382" name="Stack offset" superClass="com.crt.advproject.link.stackOffset"/>
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-								<option id="com.crt.advproject.link.config.2064476725" name="Obsolete (Config)" superClass="com.crt.advproject.link.config"/>
-								<option id="com.crt.advproject.link.store.508441126" name="Obsolete (Store)" superClass="com.crt.advproject.link.store"/>
-								<option id="com.crt.advproject.link.securestate.1645164466" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate"/>
-								<option id="com.crt.advproject.link.sgstubs.placement.706699166" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement"/>
-								<option id="com.crt.advproject.link.sgstubenable.1965856152" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable"/>
-								<option id="com.crt.advproject.link.nonsecureobject.1839814088" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject"/>
-								<option id="com.crt.advproject.link.inimplib.1977566246" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
-								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.512781588" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
-									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-								</inputType>
-							</tool>
-							<tool id="com.crt.advproject.tool.debug.release.972200988" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.release">
-								<option id="com.crt.advproject.miscellaneous.end_of_heap.1396717893" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
-								<option id="com.crt.advproject.miscellaneous.pvHeapStart.2102828751" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart"/>
-								<option id="com.crt.advproject.miscellaneous.pvHeapLimit.1915381700" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit"/>
-								<option id="com.crt.advproject.debugger.security.nonsecureimageenable.1262271839" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
-								<option id="com.crt.advproject.debugger.security.nonsecureimage.484959140" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage"/>
-							</tool>
-						</toolChain>
-					</folderInfo>
-					<sourceEntries>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
-					</sourceEntries>
-				</configuration>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="MCXN947_Project.null.989825020" name="MCXN947_Project" projectType="com.crt.advproject.projecttype.exe"/>
-	</storageModule>
-	<storageModule moduleId="scannerConfiguration">
-		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.35465113;com.crt.advproject.config.exe.release.35465113.;com.crt.advproject.gcc.exe.release.1904868820;com.crt.advproject.compiler.input.940240308">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1734776104;com.crt.advproject.config.exe.debug.1734776104.;com.crt.advproject.gas.exe.debug.1614523105;com.crt.advproject.assembler.input.2024140897">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.35465113;com.crt.advproject.config.exe.release.35465113.;com.crt.advproject.gas.exe.release.276067731;com.crt.advproject.assembler.input.1156309321">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1734776104;com.crt.advproject.config.exe.debug.1734776104.;com.crt.advproject.gcc.exe.debug.198183371;com.crt.advproject.compiler.input.322056344">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
-		<sdkName>SDK_2.x_FRDM-MCXN947</sdkName>
-		<sdkVersion>2.14.0</sdkVersion>
-		<sdkComponents>middleware.baremetal.MCXN947;platform.drivers.reset.MCXN947;platform.drivers.clock.MCXN947;platform.drivers.lpflexcomm_lpuart.MCXN947;platform.drivers.port.MCXN947;platform.drivers.gpio.MCXN947;platform.drivers.mcx_spc.MCXN947;platform.drivers.lpflexcomm.MCXN947;platform.drivers.common.MCXN947;platform.devices.MCXN947_system.MCXN947;CMSIS_Include_core_cm.MCXN947;platform.devices.MCXN947_CMSIS.MCXN947;utility.debug_console.MCXN947;component.lpuart_adapter.MCXN947;component.serial_manager_uart.MCXN947;component.serial_manager.MCXN947;platform.utilities.assert.MCXN947;component.lists.MCXN947;project_template.frdmmcxn947.MCXN947;platform.devices.MCXN947_startup.MCXN947;</sdkComponents>
-		<boardId>frdmmcxn947</boardId>
-		<package>MCXN947VDF</package>
-		<core>cm33</core>
-		<coreId>cm33_core0_MCXN947</coreId>
-	</storageModule>
-	<storageModule moduleId="com.crt.config">
-		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;
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-&lt;Properties property_3="NXP" property_4="MCXN947" property_count="5" version="100300"/&gt;
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-&lt;info chip="MCXN947" name="MCXN947"&gt;
-&lt;chip&gt;
-&lt;name&gt;MCXN947&lt;/name&gt;
-&lt;family&gt;MCXN9XX&lt;/family&gt;
-&lt;vendor&gt;NXP&lt;/vendor&gt;
-&lt;memory can_program="true" id="Flash" is_ro="true" size="2048" type="Flash"/&gt;
-&lt;memory id="RAM" size="512" type="RAM"/&gt;
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-&lt;memoryInstance derived_from="RAM" edited="true" id="SRAMX" location="0x4000000" size="0x18000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="SRAMH" location="0x20060000" size="0x8000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x400ba000" size="0x1000"/&gt;
-&lt;/chip&gt;
-&lt;processor&gt;
-&lt;name gcc_name="cortex-m33"&gt;Cortex-M33&lt;/name&gt;
-&lt;family&gt;Cortex-M&lt;/family&gt;
-&lt;/processor&gt;
-&lt;processor&gt;
-&lt;name gcc_name="cortex-m33-nodsp"&gt;Cortex-M33 (No DSP)&lt;/name&gt;
-&lt;family&gt;Cortex-M&lt;/family&gt;
-&lt;/processor&gt;
-&lt;/info&gt;
-&lt;/infoList&gt;
-&lt;/TargetConfig&gt;</projectStorage>
-	</storageModule>
-	<storageModule moduleId="refreshScope"/>
-	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="openCmsis"/>
-</cproject>

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/board.c

@@ -1,245 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include "fsl_common.h"
-#include "fsl_debug_console.h"
-#include "board.h"
-#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
-#include "fsl_lpi2c.h"
-#endif /* SDK_I2C_BASED_COMPONENT_USED */
-#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
-#include "fsl_lpflexcomm.h"
-#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
-#include "fsl_spc.h"
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-/* Initialize debug console. */
-void BOARD_InitDebugConsole(void)
-{
-    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
-    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
-
-    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
-
-    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
-
-#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
-    LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART);
-#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
-
-    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
-}
-
-void BOARD_InitDebugConsole_Core1(void)
-{
-    /* attach 12 MHz clock to FLEXCOMM1 (debug console) */
-    //    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
-
-    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
-
-    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
-
-    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
-                    uartClkSrcFreq);
-}
-
-#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
-void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
-{
-    lpi2c_master_config_t lpi2cConfig = {0};
-
-    /*
-     * lpi2cConfig.debugEnable = false;
-     * lpi2cConfig.ignoreAck = false;
-     * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
-     * lpi2cConfig.baudRate_Hz = 100000U;
-     * lpi2cConfig.busIdleTimeout_ns = 0;
-     * lpi2cConfig.pinLowTimeout_ns = 0;
-     * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
-     * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
-     */
-    LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
-    LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
-}
-
-status_t BOARD_LPI2C_Send(LPI2C_Type *base,
-                          uint8_t deviceAddress,
-                          uint32_t subAddress,
-                          uint8_t subAddressSize,
-                          uint8_t *txBuff,
-                          uint8_t txBuffSize)
-{
-    lpi2c_master_transfer_t xfer;
-
-    xfer.flags          = kLPI2C_TransferDefaultFlag;
-    xfer.slaveAddress   = deviceAddress;
-    xfer.direction      = kLPI2C_Write;
-    xfer.subaddress     = subAddress;
-    xfer.subaddressSize = subAddressSize;
-    xfer.data           = txBuff;
-    xfer.dataSize       = txBuffSize;
-
-    return LPI2C_MasterTransferBlocking(base, &xfer);
-}
-
-status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
-                             uint8_t deviceAddress,
-                             uint32_t subAddress,
-                             uint8_t subAddressSize,
-                             uint8_t *rxBuff,
-                             uint8_t rxBuffSize)
-{
-    lpi2c_master_transfer_t xfer;
-
-    xfer.flags          = kLPI2C_TransferDefaultFlag;
-    xfer.slaveAddress   = deviceAddress;
-    xfer.direction      = kLPI2C_Read;
-    xfer.subaddress     = subAddress;
-    xfer.subaddressSize = subAddressSize;
-    xfer.data           = rxBuff;
-    xfer.dataSize       = rxBuffSize;
-
-    return LPI2C_MasterTransferBlocking(base, &xfer);
-}
-
-status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
-                              uint8_t deviceAddress,
-                              uint32_t subAddress,
-                              uint8_t subAddressSize,
-                              uint8_t *txBuff,
-                              uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
-}
-
-status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
-                                 uint8_t deviceAddress,
-                                 uint32_t subAddress,
-                                 uint8_t subAddressSize,
-                                 uint8_t *rxBuff,
-                                 uint8_t rxBuffSize)
-{
-    status_t status;
-    lpi2c_master_transfer_t xfer;
-
-    xfer.flags          = kLPI2C_TransferDefaultFlag;
-    xfer.slaveAddress   = deviceAddress;
-    xfer.direction      = kLPI2C_Write;
-    xfer.subaddress     = subAddress;
-    xfer.subaddressSize = subAddressSize;
-    xfer.data           = NULL;
-    xfer.dataSize       = 0;
-
-    status = LPI2C_MasterTransferBlocking(base, &xfer);
-
-    if (kStatus_Success == status)
-    {
-        xfer.subaddressSize = 0;
-        xfer.direction      = kLPI2C_Read;
-        xfer.data           = rxBuff;
-        xfer.dataSize       = rxBuffSize;
-
-        status = LPI2C_MasterTransferBlocking(base, &xfer);
-    }
-
-    return status;
-}
-
-void BOARD_Accel_I2C_Init(void)
-{
-    BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
-}
-
-status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
-{
-    uint8_t data = (uint8_t)txBuff;
-
-    return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
-}
-
-status_t BOARD_Accel_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
-}
-
-void BOARD_Codec_I2C_Init(void)
-{
-    BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
-}
-
-status_t BOARD_Codec_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
-                            txBuffSize);
-}
-
-status_t BOARD_Codec_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
-}
-
-void BOARD_Camera_I2C_Init(void)
-{
-    LP_FLEXCOMM_Init(BOARD_CAMERA_I2C_INSTANCE, LP_FLEXCOMM_PERIPH_LPI2C);
-    BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
-}
-
-status_t BOARD_Camera_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
-                            txBuffSize);
-}
-
-status_t BOARD_Camera_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
-                               rxBuffSize);
-}
-
-status_t BOARD_Camera_I2C_SendSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
-                                txBuffSize);
-}
-
-status_t BOARD_Camera_I2C_ReceiveSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
-                                   rxBuffSize);
-}
-
-#endif /* SDK_I2C_BASED_COMPONENT_USED */
-
-/* Update Active mode voltage for OverDrive mode. */
-void BOARD_PowerMode_OD(void)
-{
-    spc_active_mode_dcdc_option_t opt = {
-        .DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
-        .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
-    };
-    SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
-
-    spc_sram_voltage_config_t cfg = {
-        .operateVoltage       = kSPC_sramOperateAt1P2V,
-        .requestVoltageUpdate = true,
-    };
-    SPC_SetSRAMOperateVoltage(SPC0, &cfg);
-}

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/board.h

@@ -1,261 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include "clock_config.h"
-#include "fsl_gpio.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief The board name */
-#define BOARD_NAME "FRDM-MCXN947"
-
-/*! @brief The UART to use for debug messages. */
-#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
-#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) LPUART4
-#define BOARD_DEBUG_UART_INSTANCE   4U
-#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
-#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4
-#define BOARD_DEBUG_UART_RST        kFC4_RST_SHIFT_RSTn
-#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_FlexComm4
-#define BOARD_UART_IRQ_HANDLER      LP_FLEXCOMM4_IRQHandler
-#define BOARD_UART_IRQ              LP_FLEXCOMM4_IRQn
-
-#define BOARD_DEBUG_UART_TYPE_CORE1       kSerialPort_Uart
-#define BOARD_DEBUG_UART_BASEADDR_CORE1   (uint32_t) USART1
-#define BOARD_DEBUG_UART_INSTANCE_CORE1   1U
-#define BOARD_DEBUG_UART_CLK_FREQ_CORE1   12000000U
-#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
-#define BOARD_DEBUG_UART_RST_CORE1        kFC1_RST_SHIFT_RSTn
-#define BOARD_DEBUG_UART_CLKSRC_CORE1     kCLOCK_Flexcomm1
-#define BOARD_UART_IRQ_HANDLER_CORE1      FLEXCOMM1_IRQHandler
-#define BOARD_UART_IRQ_CORE1              FLEXCOMM1_IRQn
-
-#ifndef BOARD_DEBUG_UART_BAUDRATE
-#define BOARD_DEBUG_UART_BAUDRATE 115200U
-#endif /* BOARD_DEBUG_UART_BAUDRATE */
-
-#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
-#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
-#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
-
-/*! @brief The UART to use for Bluetooth M.2 interface. */
-#define BOARD_BT_UART_INSTANCE   2
-#define BOARD_BT_UART_BAUDRATE   3000000
-#define BOARD_BT_UART_CLK_FREQ   12000000U
-#define BOARD_BT_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM2
-
-/*! @brief The ENET PHY address. */
-#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */
-
-/*! @brief Memory ranges not usable by the ENET DMA. */
-#ifndef BOARD_ENET_NON_DMA_MEMORY_ARRAY
-#define BOARD_ENET_NON_DMA_MEMORY_ARRAY                                                     \
-    {                                                                                       \
-        {0x00000000U, 0x0007FFFFU}, {0x10000000U, 0x17FFFFFFU}, {0x80000000U, 0xDFFFFFFFU}, \
-            {0x00000000U, 0x00000000U},                                                     \
-    }
-#endif /* BOARD_ENET_NON_DMA_MEMORY_ARRAY */
-
-#define BOARD_ACCEL_I2C_BASEADDR   LPI2C2
-#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
-
-#define BOARD_CODEC_I2C_BASEADDR   LPI2C2
-#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
-#define BOARD_CODEC_I2C_INSTANCE   2
-
-/*! @brief Indexes of the TSI channels for on-board electrodes */
-#ifndef BOARD_TSI_ELECTRODE_1
-#define BOARD_TSI_ELECTRODE_1 3U
-#endif
-
-/*! @brief Indexes of the TSI mutual channels for FRDM-TOUCH board */
-#define BOARD_TSI_MUTUAL_TX_ELECTRODE_1 0U
-#define BOARD_TSI_MUTUAL_RX_ELECTRODE_1 14U
-
-#ifndef BOARD_LED_RED_GPIO
-#define BOARD_LED_RED_GPIO GPIO0
-#endif
-#ifndef BOARD_LED_RED_GPIO_PIN
-#define BOARD_LED_RED_GPIO_PIN 10U
-#endif
-
-#ifndef BOARD_LED_BLUE_GPIO
-#define BOARD_LED_BLUE_GPIO GPIO1
-#endif
-#ifndef BOARD_LED_BLUE_GPIO_PIN
-#define BOARD_LED_BLUE_GPIO_PIN 2U
-#endif
-
-#ifndef BOARD_LED_GREEN_GPIO
-#define BOARD_LED_GREEN_GPIO GPIO0
-#endif
-#ifndef BOARD_LED_GREEN_GPIO_PIN
-#define BOARD_LED_GREEN_GPIO_PIN 27U
-#endif
-
-#ifndef BOARD_SW2_GPIO
-#define BOARD_SW2_GPIO GPIO0
-#endif
-#ifndef BOARD_SW2_GPIO_PIN
-#define BOARD_SW2_GPIO_PIN 23U
-#endif
-#define BOARD_SW2_NAME        "SW2"
-#define BOARD_SW2_IRQ         GPIO00_IRQn
-#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler
-
-#ifndef BOARD_SW3_GPIO
-#define BOARD_SW3_GPIO GPIO0
-#endif
-#ifndef BOARD_SW3_GPIO_PIN
-#define BOARD_SW3_GPIO_PIN 6U
-#endif
-#define BOARD_SW3_NAME        "SW3"
-#define BOARD_SW3_IRQ         GPIO00_IRQn
-#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler
-
-/* USB PHY condfiguration */
-#define BOARD_USB_PHY_D_CAL     (0x04U)
-#define BOARD_USB_PHY_TXCAL45DP (0x07U)
-#define BOARD_USB_PHY_TXCAL45DM (0x07U)
-
-#define BOARD_HAS_NO_CTIMER_OUTPUT_PIN_CONNECTED_TO_LED (1)
-
-/* Board led color mapping */
-#define LOGIC_LED_ON  0U
-#define LOGIC_LED_OFF 1U
-
-#define LED_RED_INIT(output)                                           \
-    GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
-    BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN)                         /*!< Enable target LED_RED */
-#define LED_RED_ON()     GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN)  /*!< Turn on target LED_RED */
-#define LED_RED_OFF()    GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN)    /*!< Turn off target LED_RED */
-#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
-
-#define LED_BLUE_INIT(output)                                            \
-    GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
-    BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN)                       /*!< Enable target LED_BLUE */
-#define LED_BLUE_ON()     GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN)  /*!< Turn on target LED_BLUE */
-#define LED_BLUE_OFF()    GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN)    /*!< Turn off target LED_BLUE */
-#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
-
-#define LED_GREEN_INIT(output)                                             \
-    GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
-    BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
-#define LED_GREEN_ON()     GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN)  /*!< Turn on target LED_GREEN */
-#define LED_GREEN_OFF()    GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN)    /*!< Turn off target LED_GREEN */
-#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
-
-/* Display. */
-#define BOARD_LCD_DC_GPIO      GPIO0
-#define BOARD_LCD_DC_GPIO_PORT 0U
-#define BOARD_LCD_DC_GPIO_PIN  10U
-
-/* Camera */
-#define BOARD_CAMERA_I2C_BASEADDR         LPI2C7
-#define BOARD_CAMERA_I2C_INSTANCE         7
-#define BOARD_CAMERA_I2C_CLOCK_FREQ       CLOCK_GetLPFlexCommClkFreq(BOARD_CAMERA_I2C_INSTANCE)
-
-/* Serial MWM WIFI */
-#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
-#define BOARD_SERIAL_MWM_PORT          USART2
-#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
-#define BOARD_SERIAL_MWM_RST_WRITE(output)
-
-/*! @brief The EMVSIM SMARTCARD PHY configuration. */
-#define BOARD_SMARTCARD_MODULE                (EMVSIM0)      /*!< SMARTCARD communicational module instance */
-#define BOARD_SMARTCARD_MODULE_IRQ            (EMVSIM0_IRQn) /*!< SMARTCARD communicational module IRQ handler */
-#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetEmvsimClkFreq(0U))
-#define BOARD_SMARTCARD_CLOCK_VALUE           (4000000U) /*!< SMARTCARD clock frequency */
-
-/* ERPC LPSPI configuration */
-#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1)
-#define ERPC_BOARD_LPSPI_BASEADDR             LPSPI3
-#define ERPC_BOARD_LPSPI_BAUDRATE             500000U
-#define ERPC_BOARD_LPSPI_CLKSRC               kCLOCK_Flexcomm3
-#define ERPC_BOARD_LPSPI_CLK_FREQ             12000000 // CLOCK_GetFlexCommClkFreq(1)
-#define ERPC_BOARD_LPSPI_INT_GPIO             GPIO0
-#define ERPC_BOARD_LPSPI_INT_PIN              16U
-#define ERPC_BOARD_LPSPI_INT_PIN_IRQ          PIN_INT0_IRQn
-#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER  PIN_INT0_IRQHandler
-
-/* ERPC LPI2C configuration */
-#define ERPC_BOARD_LPI2C_BASEADDR            LPI2C0_BASE
-#define ERPC_BOARD_LPI2C_BAUDRATE            100000U
-#define ERPC_BOARD_LPI2C_CLKSRC              kCLOCK_Flexcomm0
-#define ERPC_BOARD_LPI2C_CLK_FREQ            12000000 // CLOCK_GetFlexCommClkFreq(2)
-#define ERPC_BOARD_LPI2C_INT_GPIO            GPIO1
-#define ERPC_BOARD_LPI2C_INT_PIN             0U
-#define ERPC_BOARD_LPI2C_INT_PIN_IRQ         PIN_INT1_IRQn
-#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-void BOARD_InitDebugConsole(void);
-void BOARD_InitDebugConsole_Core1(void);
-#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
-void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
-status_t BOARD_LPI2C_Send(LPI2C_Type *base,
-                          uint8_t deviceAddress,
-                          uint32_t subAddress,
-                          uint8_t subaddressSize,
-                          uint8_t *txBuff,
-                          uint8_t txBuffSize);
-status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
-                             uint8_t deviceAddress,
-                             uint32_t subAddress,
-                             uint8_t subaddressSize,
-                             uint8_t *rxBuff,
-                             uint8_t rxBuffSize);
-status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
-                              uint8_t deviceAddress,
-                              uint32_t subAddress,
-                              uint8_t subaddressSize,
-                              uint8_t *txBuff,
-                              uint8_t txBuffSize);
-status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
-                                 uint8_t deviceAddress,
-                                 uint32_t subAddress,
-                                 uint8_t subaddressSize,
-                                 uint8_t *rxBuff,
-                                 uint8_t rxBuffSize);
-void BOARD_Accel_I2C_Init(void);
-status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
-status_t BOARD_Accel_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-void BOARD_Codec_I2C_Init(void);
-status_t BOARD_Codec_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
-status_t BOARD_Codec_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-void BOARD_Camera_I2C_Init(void);
-status_t BOARD_Camera_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
-status_t BOARD_Camera_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-
-status_t BOARD_Camera_I2C_SendSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
-status_t BOARD_Camera_I2C_ReceiveSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-#endif /* SDK_I2C_BASED_COMPONENT_USED */
-
-void BOARD_PowerMode_OD(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-#endif /* _BOARD_H_ */

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/clock_config.c

@@ -1,354 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v11.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.13.10
-board: FRDM-MCXN947
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_clock.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(12000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: RunPowerMode, value: OD}
-- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(48000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 36 MHz}
-- {id: System_clock.outFreq, value: 144 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: RunPowerMode, value: OD}
-- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
-- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(144000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(150000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(100000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
-

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/clock_config.h

@@ -1,177 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
-

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/peripherals.h

@@ -1,23 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _PERIPHERALS_H_
-#define _PERIPHERALS_H_
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /*_cplusplus. */
-/*******************************************************************************
- * BOARD_InitBootPeripherals function
- ******************************************************************************/
-void BOARD_InitBootPeripherals(void);
-
-#if defined(__cplusplus)
-}
-#endif /*_cplusplus. */
-
-#endif /* _PERIPHERALS_H_ */

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/pin_mux.c

@@ -1,705 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v14.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.14.19
-board: FRDM-MCXN947
-expansion_headers:
-- id: micro_bus
-  name: mikroBUS(TM)
-  connectors:
-  - id: C1
-    name: J6
-    pins:
-    - {id: 1, name: AN, pin_num: T2, pin_signal: ADC1_A0}
-    - {id: 2, name: RST, pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1}
-    - {id: 3, name: CS, pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1}
-    - {id: 4, name: SCK, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
-    - {id: 5, name: MISO, pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1}
-    - {id: 6, name: MOSI, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
-  - id: C2
-    name: J5
-    pins:
-    - {id: 1, name: PWM, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
-    - {id: 2, name: INT, pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15}
-    - {id: 3, name: RX, pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16}
-    - {id: 4, name: TX, pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17}
-    - {id: 5, name: SCL, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
-    - {id: 6, name: SDA, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
-- id: frdm_arduino
-  name: LPCXpresso V3 (Arduino compatible)
-  connectors:
-  - id: C1
-    name: J3
-    pins:
-    - {id: 1, pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK}
-    - {id: 2, pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3}
-    - {id: 3, pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22}
-    - {id: 5, pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0}
-    - {id: 6, pin_num: F3, pin_signal: RESET_B}
-    - {id: 7, pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0}
-    - {id: 9, pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1}
-    - {id: 11, pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1}
-    - {id: 13, pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS}
-    - {id: 15, pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK}
-  - id: C2
-    name: J2
-    pins:
-    - {id: 1, pin_num: T3, pin_signal: ADC1_B0}
-    - {id: 2, pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20}
-    - {id: 3, pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10}
-    - {id: 4, pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10}
-    - {id: 5, pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11}
-    - {id: 6, pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19}
-    - {id: 7, pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12}
-    - {id: 8, pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16}
-    - {id: 9, pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1}
-    - {id: 10, pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18}
-    - {id: 11, pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10}
-    - {id: 12, pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17}
-    - {id: 13, pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11}
-    - {id: 15, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
-    - {id: 17, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
-    - {id: 18, pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3}
-    - {id: 20, pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1}
-  - id: C3
-    name: J1
-    pins:
-    - {id: 1, pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK}
-    - {id: 2, pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N}
-    - {id: 3, pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5}
-    - {id: 4, pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N}
-    - {id: 5, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
-    - {id: 6, pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21}
-    - {id: 7, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
-    - {id: 8, pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23}
-    - {id: 9, pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK}
-    - {id: 10, pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22}
-    - {id: 11, pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS}
-    - {id: 12, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
-    - {id: 13, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
-    - {id: 14, pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0}
-    - {id: 15, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
-    - {id: 16, pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23}
-  - id: C4
-    name: J4
-    pins:
-    - {id: 1, pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5}
-    - {id: 2, pin_num: P3, pin_signal: ADC0_A0}
-    - {id: 3, pin_num: U6, pin_signal: OPAMP0_INN}
-    - {id: 4, pin_num: R3, pin_signal: ADC0_B0}
-    - {id: 5, pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6}
-    - {id: 6, pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14}
-    - {id: 7, pin_num: U8, pin_signal: OPAMP1_INN}
-    - {id: 8, pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2}
-    - {id: 9, pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6}
-    - {id: 10, pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15}
-    - {id: 11, pin_num: U10, pin_signal: OPAMP2_INN}
-    - {id: 12, pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2}
-- {id: frdm_arduino, name: LPCXpressoV2/V3 Expansion Header}
-- {id: micro_bus, name: mikroBUS Click Header}
-external_user_signals: {}
-pin_labels:
-- {pin_num: A1, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8, label: 'P1_8/J9[32]',
-  identifier: DEBUG_UART_RX}
-- {pin_num: B1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9, label: 'P1_9/J9[30]', identifier: DEBUG_UART_TX}
-- {pin_num: D1, pin_signal: PIO1_13/TRIG_IN3/FC4_P5/FC3_P1/CT2_MAT3/SCT0_OUT5/FLEXIO0_D21/PLU_OUT3/ENET0_RXDV/CAN1_TXD/TSI0_CH22/ADC1_A13, label: 'P1_13/J9[27]'}
-- {pin_num: F1, pin_signal: PIO1_30/TRIG_OUT3/CT_INP16/SCT0_OUT8/SAI0_MCLK/XTAL48M, label: 'P1_30/XTAL/Y1[1]'}
-- {pin_num: H1, pin_signal: PIO2_1/TRACE_CLK/SDHC0_D4/SCT0_IN1/PWM1_B3/FLEXIO0_D9/FLEXSPI0_B_DQS/SINC0_MCLK_OUT0/SAI0_RX_FS, label: 'P2_1/TP27/J12[9]'}
-- {pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1, label: 'P2_5/TP25/J12[3]/J3[9]/SJ6[3]'}
-- {pin_num: M1, pin_signal: PIO2_9/TRACE_DATA1/SDHC0_D6/SCT0_IN3/PWM1_X1/FLEXIO0_D17/FLEXSPI0_B_DATA5/SINC0_MBIT3/SAI1_RXD0, label: 'P2_9/J8[14]'}
-- {pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3, label: 'P4_0/J8[4]/SJ14[1]'}
-- {pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N, label: 'P4_2/J1[4]'}
-- {pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N, label: 'P4_3/J1[2]'}
-- {pin_num: A2, pin_signal: PIO1_7/WUU0_IN9/TRIG_OUT2/FC5_P3/CT_INP7/SCT0_IN1/FLEXIO0_D15/PLU_CLK/ENET0_TXD1/SAI1_RX_FS/CAN1_RXD/TSI0_CH7/ADC0_A23, label: 'P1_7/J9[9]'}
-- {pin_num: B2, pin_signal: PIO1_6/TRIG_IN2/FC3_P6/FC5_P2/CT_INP6/SCT0_IN0/FLEXIO0_D14/ENET0_TXD0/SAI1_RX_BCLK/CAN1_TXD/TSI0_CH6/ADC0_A22, label: 'P1_6/J9[10]'}
-- {pin_num: D2, pin_signal: PIO1_12/WUU0_IN12/TRACE_CLK/FC4_P4/FC3_P0/CT2_MAT2/SCT0_OUT4/FLEXIO0_D20/PLU_OUT2/ENET0_RXER/CAN1_RXD/TSI0_CH21/ADC1_A12, label: 'P1_12/J2[11]/J9[28]'}
-- {pin_num: F2, pin_signal: PIO1_31/TRIG_IN4/CT_INP17/SCT0_OUT9/EXTAL48M, label: 'P1_31/EXTAL/Y1[3]'}
-- {pin_num: G2, pin_signal: VSS0, label: GND}
-- {pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK, label: 'P2_0/J3[1]/SJ8[3]'}
-- {pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK, label: 'P2_6/TP24/J12[2]/J3[15]/SJ1[3]'}
-- {pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS, label: 'P2_7/TP23/J12[1]/J3[13]/SJ3[3]'}
-- {pin_num: M2, pin_signal: PIO2_8/TRACE_DATA0/SDHC0_D7/SCT0_IN2/PWM1_X0/FLEXIO0_D16/FLEXSPI0_B_DATA4/SINC0_MCLK3/SAI1_TXD0, label: 'P2_8/J8[13]'}
-- {pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1, label: 'P4_1/J8[3]/SJ15[1]'}
-- {pin_num: T2, pin_signal: ADC1_A0, label: 'ANA_4/ADC1_A0/J6[1]'}
-- {pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3, label: 'ANA_6/ADC0_A3/J3[2]'}
-- {pin_num: B3, pin_signal: PIO1_5/FREQME_CLK_IN1/FC3_P5/FC5_P1/CT1_MAT3/SCT0_OUT1/FLEXIO0_D13/ENET0_TXEN/SAI0_RXD1/TSI0_CH5/ADC0_A21/CMP0_IN3, label: 'P1_5/J9[7]'}
-- {pin_num: C3, pin_signal: PIO1_10/TRACE_DATA2/FC4_P2/FC5_P6/CT2_MAT0/SCT0_IN2/FLEXIO0_D18/PLU_IN0/ENET0_TXER/CAN0_TXD/TSI0_CH19/ADC1_A10, label: 'P1_10/SJ20[3]/SJ16[2]'}
-- {pin_num: D3, pin_signal: PIO1_11/WUU0_IN11/TRACE_DATA3/FC4_P3/CT2_MAT1/SCT0_IN3/FLEXIO0_D19/PLU_IN1/ENET0_RX_CLK/I3C1_PUR/CAN0_RXD/TSI0_CH20/ADC1_A11, label: 'P1_11/SJ26[2]'}
-- {pin_num: F3, pin_signal: RESET_B, label: 'RESET_B/J23[10]/D16[1]/SW1[3]/SW1[4]/J3[6]', identifier: SW1}
-- {pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0, label: 'P2_2/TP5/J12[8]/J3[7]/SJ7[3]'}
-- {pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0, label: 'P2_3/TP4/J12[7]/J3[5]/SJ4[3]'}
-- {pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1, label: 'P2_4/TP26/J12[5]/J3[11]/SJ5[3]'}
-- {pin_num: M3, pin_signal: PIO2_10/TRACE_DATA2/SCT0_IN4/PWM1_X2/FLEXIO0_D18/FLEXSPI0_B_DATA6/SINC0_MCLK4/SAI1_RXD1, label: 'P2_10/J8[15]'}
-- {pin_num: P3, pin_signal: ADC0_A0, label: 'ADC0_A0/ARD_A0/J4[2]'}
-- {pin_num: R3, pin_signal: ADC0_B0, label: 'ADC0_B0/ARD_A1/J4[4]'}
-- {pin_num: T3, pin_signal: ADC1_B0, label: 'ADC1_B0/MC_BEMF_A/J2[1]'}
-- {pin_num: A4, pin_signal: PIO1_4/WUU0_IN8/FREQME_CLK_IN0/FC3_P4/FC5_P0/CT1_MAT2/SCT0_OUT0/FLEXIO0_D12/ENET0_TX_CLK/SAI0_TXD1/TSI0_CH4/ADC0_A20/CMP0_IN2, label: 'P1_4/SJ27[2]'}
-- {pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1, label: 'P1_3/J6[2]'}
-- {pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0, label: 'P1_2/SJ4[1]',
-  identifier: LED_BLUE}
-- {pin_num: D4, pin_signal: PIO1_14/FC4_P6/FC3_P2/CT_INP10/SCT0_IN4/FLEXIO0_D22/PLU_IN2/ENET0_RXD0/TSI0_CH23/ADC1_A14, label: 'P1_14/J9[2]'}
-- {pin_num: E4, pin_signal: PIO1_15/WUU0_IN13/FC3_P3/CT_INP11/SCT0_IN5/FLEXIO0_D23/PLU_IN3/ENET0_RXD1/I3C1_PUR/TSI0_CH24/ADC1_A15, label: 'P1_15/J9[1]'}
-- {pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17, label: 'P1_17/SJ15[3]/J5[4]/J9[3]'}
-- {pin_num: G4, pin_signal: PIO1_18/FREQME_CLK_IN0/FC5_P2/FC3_P6/CT3_MAT0/SCT0_IN6/FLEXIO0_D26/PLU_IN4/ENET0_COL/CAN0_TXD/ADC1_A18, label: 'P1_18/J9[6]'}
-- {pin_num: J4, pin_signal: VSS1, label: GND}
-- {pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22, label: 'P1_22/J9[24]/J3[3]/SJ9[3]'}
-- {pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23, label: 'P1_23/J9[23]/SJ1[1]'}
-- {pin_num: N4, pin_signal: PIO2_11/TRACE_DATA3/SCT0_IN5/PWM1_X3/FLEXIO0_D19/FLEXSPI0_B_DATA7/SINC0_MBIT4/SAI1_TXD1, label: 'P2_11/J8[16]'}
-- {pin_num: P4, pin_signal: VDD_P40, label: VDD_P4}
-- {pin_num: R4, pin_signal: VDD_ANA, label: 'VDD_ANA/J2[16]'}
-- {pin_num: T4, pin_signal: PIO4_7/CT_INP19, label: 'P4_7/J8[7]'}
-- {pin_num: U4, pin_signal: VREFO/ADC0_A7/ADC1_A7, label: VREFO/TP1}
-- {pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0, label: 'P1_1/J5[5]/J2[15]'}
-- {pin_num: E5, pin_signal: VSS3, label: GND}
-- {pin_num: G5, pin_signal: PIO1_19/WUU0_IN15/FREQME_CLK_IN1/FC5_P3/CT3_MAT1/SCT0_IN7/FLEXIO0_D27/PLU_IN5/ENET0_CRS/CAN0_RXD/ADC1_A19, label: 'P1_19/J9[5]'}
-- {pin_num: H5, pin_signal: VSS2, label: GND}
-- {pin_num: K5, pin_signal: PIO1_20/TRIG_IN2/FC5_P4/FC4_P0/CT3_MAT2/SCT0_OUT8/FLEXIO0_D28/PLU_OUT6/ENET0_MDC/CAN1_TXD/ADC1_A20/CMP1_IN3, label: P1_20}
-- {pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3, label: 'P1_21/SJ3[1]/J1[7]'}
-- {pin_num: N5, pin_signal: VDD_P41, label: VDD_P4}
-- {pin_num: R5, pin_signal: VREFH, label: VREFH}
-- {pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17, label: 'P0_25/J2[12]'}
-- {pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16, label: 'P0_24/SJ7[1]'}
-- {pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0, label: 'P1_0/J5[6]/J2[17]'}
-- {pin_num: N13, pin_signal: VSS4, label: GND}
-- {pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16, label: 'P1_16/SJ14[3]/J5[3]/J9[4]'}
-- {pin_num: H6, pin_signal: VDD1, label: VDD_P0/1}
-- {pin_num: K6, pin_signal: VDD_LDO_CORE, label: VDD_LDO_CORE_IN}
-- {pin_num: M6, pin_signal: PIO4_4/FC2_P4/CT_INP14/PLU_IN4/SINC0_MCLK4, label: 'P4_4/J9[26]'}
-- {pin_num: P6, pin_signal: VSS_P41, label: GND}
-- {pin_num: R6, pin_signal: VREFL, label: AGND}
-- {pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5, label: 'P4_12/SJ25[1]/J8[17]'}
-- {pin_num: U6, pin_signal: OPAMP0_INN, label: 'OPAMP0_INN/RSHUNT_CURA_N/SJ24[1]'}
-- {pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, label: 'P0_23/SJ9[1]/SW2[3]/SW2[4]', identifier: SW2}
-- {pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23, label: 'P0_31/J1[16]'}
-- {pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22, label: 'P0_30/SJ2[1]'}
-- {pin_num: G7, pin_signal: VDD0, label: VDD_P0/1}
-- {pin_num: L7, pin_signal: VDD_P20, label: VDD_P2}
-- {pin_num: N7, pin_signal: PIO4_6/TRIG_OUT4/FC2_P6/CT_INP18/PLU_CLK, label: 'P4_6/J8[5]'}
-- {pin_num: P7, pin_signal: VSS_P42, label: GND}
-- {pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5, label: 'P4_13/SJ10[1]/SJ2[3]/J8[18]'}
-- {pin_num: A8, pin_signal: PIO0_21/FC0_P5/FC1_P1/CT_INP1/FLEXIO0_D5/I3C0_SCL/TSI0_CH16/ADC0_A13, label: 'P0_21/SJ25[3]'}
-- {pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2, label: 'P0_22/J4[8]/SJ18[3]'}
-- {pin_num: C8, pin_signal: PIO0_20/WUU0_IN4/FC0_P4/FC1_P0/CT_INP0/FLEXIO0_D4/I3C0_SDA/TSI0_CH15/ADC0_A12, label: 'P0_20/SJ24[3]/J7[2]'}
-- {pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20, label: 'P0_28/J2[2]'}
-- {pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21, label: 'P0_29/J1[6]'}
-- {pin_num: H8, pin_signal: VDD2, label: VDD_P0/1}
-- {pin_num: H13, pin_signal: VSS10, label: GND}
-- {pin_num: K8, pin_signal: VDD_P21, label: VDD_P2}
-- {pin_num: M8, pin_signal: PIO4_5/FC2_P5/CT_INP15/PLU_IN5/SINC0_MBIT4, label: 'P4_5/SJ11[3]/J8[6]'}
-- {pin_num: N8, pin_signal: PIO4_14/CT4_MAT2/FLEXIO0_D22/PLU_OUT2, label: 'P4_14/J8[19]'}
-- {pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6, label: 'P4_16/SJ23[1]/J8[21]'}
-- {pin_num: T8, pin_signal: PIO4_15/WUU0_IN21/TRIG_OUT4/USB1_VBUS_DIG/CT4_MAT3/FLEXIO0_D23/PLU_OUT3/SINC0_MCLK_OUT0/CAN1_RXD/OPAMP0_OUT/ADC0_A1/CMP0_IN4P, label: 'P4_15/J8[20]'}
-- {pin_num: U8, pin_signal: OPAMP1_INN, label: 'OPAMP1_INN/RSHUNT_CURB_N/SJ22[1]'}
-- {pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11, label: 'P0_19/J2[13]/J7[1]'}
-- {pin_num: D6, pin_signal: VSS5, label: GND}
-- {pin_num: E13, pin_signal: VSS8, label: GND}
-- {pin_num: J14, pin_signal: VSS13, label: GND}
-- {pin_num: P9, pin_signal: VSS_P40, label: GND}
-- {pin_num: R9, pin_signal: PIO4_17/TRIG_IN9/FC2_P3/USB1_OTG_OC/CT3_MAT1/FLEXIO0_D25/PLU_OUT5/SINC0_MBIT1/OPAMP1_INP1/ADC0_B6, label: 'P4_17/J8[22]'}
-- {pin_num: A10, pin_signal: PIO0_17/FC0_P1/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1/PDM0_DATA0/I3C0_SCL/TSI0_CH12/ADC0_A9, label: 'P0_17/J7[7]'}
-- {pin_num: B10, pin_signal: PIO0_16/WUU0_IN2/FC0_P0/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0/PDM0_CLK/I3C0_SDA/TSI0_CH11/ADC0_A8, label: 'P0_16/J7[3]'}
-- {pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10, label: 'P0_18/SJ23[3]/J7[5]'}
-- {pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, label: 'P0_27/SJ6[1]', identifier: LED_GREEN}
-- {pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18, label: 'P0_26/J2[10]'}
-- {pin_num: H10, pin_signal: VDD_P31, label: VDD_P3}
-- {pin_num: J8, pin_signal: VSS11, label: GND}
-- {pin_num: K10, pin_signal: VDD_CORE/VOUT_CORE, label: 'VDD_CORE/L2[2]'}
-- {pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10, label: 'P5_2/SJ19[1]'}
-- {pin_num: N10, pin_signal: PIO4_18/CT3_MAT2/FLEXIO0_D26/PLU_OUT6, label: 'P4_18/J8[23]'}
-- {pin_num: R10, pin_signal: PIO4_19/TRIG_OUT5/CT3_MAT3/FLEXIO0_D27/PLU_OUT7/SINC0_MCLK_OUT1/OPAMP1_OUT/ADC0_B1/CMP1_IN4P, label: 'P4_19/J8[24]'}
-- {pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6, label: 'P4_20/SJ21[1]/J8[25]'}
-- {pin_num: U10, pin_signal: OPAMP2_INN, label: 'OPAMP2_INN/RSHUNT_CURC_N/SJ20[1]'}
-- {pin_num: B11, pin_signal: PIO0_11/CT0_MAT1/FLEXIO0_D3/HSCMP2_OUT/ADC0_B11, label: 'P0_11/J9[18]'}
-- {pin_num: D11, pin_signal: PIO0_12/FC1_P4/FC0_P0/CT0_MAT2/FLEXIO0_D4/ADC0_B12, label: 'P0_12/J8[9]'}
-- {pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14, label: 'P0_14/J4[6]/SJ19[3]'}
-- {pin_num: G11, pin_signal: VDD_P30, label: VDD_P3}
-- {pin_num: L11, pin_signal: VDD_CORE, label: 'VDD_CORE/L2[2]'}
-- {pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11, label: 'P5_3/SJ18[1]'}
-- {pin_num: P11, pin_signal: USB1_ID, label: 'HS_USB_ID/Q1[2]'}
-- {pin_num: T11, pin_signal: PIO4_21/TRIG_IN9/FC2_P5/CT2_MAT1/FLEXIO0_D29/SINC0_MBIT2/OPAMP2_INP1/ADC1_B6, label: 'P4_21/J8[26]'}
-- {pin_num: A12, pin_signal: PIO0_9/FC0_P5/CT_INP1/FLEXIO0_D1/ADC0_B9, label: 'P0_9/J8[10]'}
-- {pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, label: 'P0_10/SJ5[1]', identifier: LED_RED}
-- {pin_num: C12, pin_signal: PIO0_8/FC0_P4/CT_INP0/FLEXIO0_D0/ADC0_B8, label: 'P0_8/J8[11]'}
-- {pin_num: D9, pin_signal: VSS6, label: GND}
-- {pin_num: F12, pin_signal: PIO0_13/FC1_P5/FC0_P1/CT0_MAT3/FLEXIO0_D5/ADC0_B13, label: 'P0_13/J8[12]'}
-- {pin_num: H12, pin_signal: VDD_P42, label: VDD_P3}
-- {pin_num: K12, pin_signal: PIO5_5/TRIG_IN10/LPTMR0_ALT2/TAMPER3/ADC1_B13, label: 'P5_5/SJ17[3]'}
-- {pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12, label: 'P5_4/J2[7]'}
-- {pin_num: P14, pin_signal: VDD3, label: GND}
-- {pin_num: R12, pin_signal: VDD_USB, label: VDD_USB}
-- {pin_num: T12, pin_signal: PIO4_22/CT2_MAT2/FLEXIO0_D30, label: 'P4_22/J8[27]'}
-- {pin_num: U12, pin_signal: PIO4_23/TRIG_OUT5/FC2_P6/CT2_MAT3/FLEXIO0_D31/SINC0_MCLK_OUT2/OPAMP2_OUT/ADC0_A2/ADC0_B2/ADC1_B3/CMP2_IN4P, label: 'P4_23/J8[28]'}
-- {pin_num: C13, pin_signal: PIO0_7/WUU0_IN1/FC0_P3/CT_INP3/CMP2_IN1, label: 'P0_7/J8[8]'}
-- {pin_num: D12, pin_signal: VSS7, label: GND}
-- {pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15, label: 'P0_15/SJ8[1]'}
-- {pin_num: H9, pin_signal: VSS9, label: GND}
-- {pin_num: K13, pin_signal: PIO5_6/TRIG_OUT6/LPTMR1_ALT2/TAMPER4/ADC1_B14, label: 'P5_6/SJ13[1]'}
-- {pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15, label: 'P5_7/J5[2]'}
-- {pin_num: R13, pin_signal: USB1_DP, label: 'MCX_USB1_DP/L13[3]'}
-- {pin_num: A14, pin_signal: PIO0_5/EWM0_OUT_b/FC0_P1/FC1_P5/CT0_MAT3/UTICK_CAP3/PDM0_DATA0/TSI0_CH9, label: 'P0_5/SJ13[3]/J9[15]/SJ21[3]'}
-- {pin_num: B14, pin_signal: PIO0_4/WUU0_IN0/EWM0_IN/FC0_P0/FC1_P4/CT0_MAT2/UTICK_CAP2/HSCMP1_OUT/PDM0_CLK/TSI0_CH8, label: 'P0_4/SJ12[3]/J9[17]/SJ22[3]'}
-- {pin_num: C14, pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, label: 'P0_6/J23[7]/SW3[3]/SW3[4]', identifier: SW3}
-- {pin_num: D14, pin_signal: PIO3_7/FC6_P6/FC7_P1/CT4_MAT3/PWM0_B1/FLEXIO0_D15/FLEXSPI0_A_SCLK/SIM0_VCCEN/SAI0_MCLK, label: 'P3_7/TP18/U8[6]/U7[B2]'}
-- {pin_num: E14, pin_signal: PIO3_8/WUU0_IN23/FC6_P4/FC7_P0/CT_INP4/PWM0_A2/FLEXIO0_D16/FLEXSPI0_A_DATA0/SIM0_PD/SAI0_TX_BCLK, label: 'P3_8/TP16/U8[5]/U7[D3]'}
-- {pin_num: F14, pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, label: 'P3_4/J9[12]'}
-- {pin_num: G14, pin_signal: PIO3_5/FC7_P3/CT_INP19/PWM0_X3/FLEXIO0_D13/SIM1_IO, label: 'P3_5/J9[11]'}
-- {pin_num: J10, pin_signal: VSS12, label: GND}
-- {pin_num: L14, pin_signal: PIO5_8/TRIG_OUT7/TAMPER6/ADC1_B16, label: 'P5_8/U9[19]/J9[31]'}
-- {pin_num: M14, pin_signal: PIO5_9/TAMPER7/ADC1_B17, label: 'P5_9/J9[29]'}
-- {pin_num: N14, pin_signal: VDD_SYS, label: VDD_SYS}
-- {pin_num: T16, pin_signal: VDD4, label: GND}
-- {pin_num: R14, pin_signal: USB1_DM, label: 'MCX_USB1_DM/L13[2]'}
-- {pin_num: T14, pin_signal: USB0_DM/WUU0_IN28, label: TP2}
-- {pin_num: U14, pin_signal: USB1_VBUS, label: MCX_USB1_VBUS}
-- {pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1, label: 'P0_3/J23[8]/D16[3]/SJ17[1]'}
-- {pin_num: C15, pin_signal: PIO3_1/TRIG_IN1/FC6_P0/FC7_P6/CT_INP17/PWM0_B0/FLEXIO0_D9/FLEXSPI0_A_SS1_b/FREQME_CLK_OUT0, label: P3_1/TP31}
-- {pin_num: D15, pin_signal: PIO3_2/FC7_P0/CT4_MAT0/PWM0_X0/FLEXIO0_D10/SIM1_PD, label: 'P3_2/J9[20]/J7[8]'}
-- {pin_num: F15, pin_signal: PIO3_9/FC6_P5/FC7_P2/CT_INP5/PWM0_B2/FLEXIO0_D17/FLEXSPI0_A_DATA1/SIM0_RST/SAI0_TX_FS, label: 'P3_9/TP15/U8[2]/U7[D2]'}
-- {pin_num: H15, pin_signal: PIO3_15/FC8_P1/CT_INP7/PWM1_B1/FLEXIO0_D23/FLEXSPI0_A_DATA7/SAI0_RX_FS, label: 'P3_15/TP9/U7[E1]'}
-- {pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK, label: 'P3_16/SJ11[1]'}
-- {pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS, label: 'P3_17/J1[11]/SJ10[3]'}
-- {pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1, label: 'P3_23/J6[3]'}
-- {pin_num: P15, pin_signal: VDD_LDO_SYS/VOUT_SYS, label: VDD_LDO_SYS_IN}
-- {pin_num: R15, pin_signal: VDD_DCDC, label: VDD_DCDC}
-- {pin_num: T15, pin_signal: USB0_DP/WUU0_IN29, label: TP3}
-- {pin_num: A16, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, label: 'P0_1/SWCLK/J23[4]/D16[5]/J22[2]', identifier: DEBUG_SWD_SWDCLK}
-- {pin_num: B16, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, label: 'P0_2/SWO/J23[6]/D16[4]', identifier: DEBUG_SWD_SWO}
-- {pin_num: D16, pin_signal: PIO3_3/FC7_P1/CT4_MAT1/PWM0_X1/FLEXIO0_D11/SIM1_RST, label: 'P3_3/J9[19]/SJ12[1]'}
-- {pin_num: F16, pin_signal: PIO3_11/WUU0_IN24/FC6_P3/FC7_P5/CT1_MAT1/PWM0_B3/FLEXIO0_D19/FLEXSPI0_A_DATA3/SIM0_IO/SAI0_RXD0, label: 'P3_11/TP14/U8[7]/U7[D4]'}
-- {pin_num: G16, pin_signal: PIO3_12/FC7_P4/FC6_P4/CT1_MAT2/PWM1_A0/FLEXIO0_D20/FLEXSPI0_A_DATA4/SAI0_RXD1, label: 'P3_12/TP17/U7[D5]'}
-- {pin_num: H16, pin_signal: PIO3_13/FC7_P5/FC6_P5/CT1_MAT3/PWM1_B0/FLEXIO0_D21/FLEXSPI0_A_DATA5/SAI0_TXD1, label: 'P3_13/TP11/U7[E3]'}
-- {pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK, label: 'P3_18/J1[9]'}
-- {pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0, label: 'P3_21/J6[4]/J1[15]'}
-- {pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1, label: 'P3_22/J6[5]'}
-- {pin_num: P16, pin_signal: VSS_DCDC, label: GND}
-- {pin_num: U16, pin_signal: PIO5_0/TRIG_IN10/LPTMR0_ALT2/EXTAL32K/ADC1_B8, label: 'P5_0/EXTAL32K/Y2[2]'}
-- {pin_num: A17, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, label: 'P0_0/SWDIO/J23[2]/D16[6]', identifier: DEBUG_SWD_SWDIO}
-- {pin_num: B17, pin_signal: PIO3_0/WUU0_IN22/TRIG_IN0/FC7_P3/CT_INP16/PWM0_A0/FLEXIO0_D8/FLEXSPI0_A_SS0_b, label: 'P3_0/TP12/U8[1]/U7[C2]/U7[A3]'}
-- {pin_num: D17, pin_signal: PIO3_6/CLKOUT/FC6_P1/CT4_MAT2/PWM0_A1/FLEXIO0_D14/FLEXSPI0_A_DQS/SIM1_VCCEN/SAI1_MCLK/FREQME_CLK_OUT1, label: 'P3_6/TP8/U7[C3]'}
-- {pin_num: F17, pin_signal: PIO3_10/FC6_P2/FC7_P4/CT1_MAT0/PWM0_A3/FLEXIO0_D18/FLEXSPI0_A_DATA2/SIM0_CLK/SAI0_TXD0, label: 'P3_10/TP13/U8[3]/U7[C4]'}
-- {pin_num: H17, pin_signal: PIO3_14/WUU0_IN25/FC8_P0/CT_INP6/PWM1_A1/FLEXIO0_D22/FLEXSPI0_A_DATA6/SAI0_RX_BCLK, label: 'P3_14/TP10/U7[E2]'}
-- {pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS, label: 'P3_19/J5[1]/J1[13]'}
-- {pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0, label: 'P3_20/J6[6]/J1[5]'}
-- {pin_num: P17, pin_signal: DCDC_LX, label: DCDC_LX}
-- {pin_num: T17, pin_signal: VDD_BAT, label: 'VDD_BAT/J27[2]'}
-- {pin_num: U17, pin_signal: PIO5_1/TRIG_OUT6/LPTMR1_ALT2/XTAL32K/ADC1_B9, label: 'P5_1/XTAL32K/Y2[1]'}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "fsl_gpio.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitDEBUG_UARTPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitDEBUG_UARTPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitDEBUG_UARTPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitDEBUG_UARTPins(void)
-{
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-    const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
-                                             kPORT_PullDisable,
-                                             /* Low internal pull resistor value is selected. */
-                                             kPORT_LowPullResistor,
-                                             /* Fast slew rate is configured */
-                                             kPORT_FastSlewRate,
-                                             /* Passive input filter is disabled */
-                                             kPORT_PassiveFilterDisable,
-                                             /* Open drain output is disabled */
-                                             kPORT_OpenDrainDisable,
-                                             /* Low drive strength is configured */
-                                             kPORT_LowDriveStrength,
-                                             /* Pin is configured as FC4_P0 */
-                                             kPORT_MuxAlt2,
-                                             /* Digital input enabled */
-                                             kPORT_InputBufferEnable,
-                                             /* Digital input is not inverted */
-                                             kPORT_InputNormal,
-                                             /* Pin Control Register fields [15:0] are not locked */
-                                             kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
-
-    const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
-                                             kPORT_PullDisable,
-                                             /* Low internal pull resistor value is selected. */
-                                             kPORT_LowPullResistor,
-                                             /* Fast slew rate is configured */
-                                             kPORT_FastSlewRate,
-                                             /* Passive input filter is disabled */
-                                             kPORT_PassiveFilterDisable,
-                                             /* Open drain output is disabled */
-                                             kPORT_OpenDrainDisable,
-                                             /* Low drive strength is configured */
-                                             kPORT_LowDriveStrength,
-                                             /* Pin is configured as FC4_P1 */
-                                             kPORT_MuxAlt2,
-                                             /* Digital input enabled */
-                                             kPORT_InputBufferEnable,
-                                             /* Digital input is not inverted */
-                                             kPORT_InputNormal,
-                                             /* Pin Control Register fields [15:0] are not locked */
-                                             kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitSWD_DEBUGPins:
-- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A16, peripheral: SWD, signal: SWCLK, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down,
-    pull_enable: enable, input_buffer: enable, invert_input: normal}
-  - {pin_num: A17, peripheral: SWD, signal: SWDIO, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high, pull_select: up,
-    pull_enable: enable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B16, peripheral: SWD, signal: SWO, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, drive_strength: high,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitSWD_DEBUGPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitSWD_DEBUGPins(void)
-{
-    /* Enables the clock for PORT0 controller: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */
-                                               kPORT_PullUp,
-                                               /* Low internal pull resistor value is selected. */
-                                               kPORT_LowPullResistor,
-                                               /* Fast slew rate is configured */
-                                               kPORT_FastSlewRate,
-                                               /* Passive input filter is disabled */
-                                               kPORT_PassiveFilterDisable,
-                                               /* Open drain output is disabled */
-                                               kPORT_OpenDrainDisable,
-                                               /* High drive strength is configured */
-                                               kPORT_HighDriveStrength,
-                                               /* Pin is configured as SWDIO */
-                                               kPORT_MuxAlt1,
-                                               /* Digital input enabled */
-                                               kPORT_InputBufferEnable,
-                                               /* Digital input is not inverted */
-                                               kPORT_InputNormal,
-                                               /* Pin Control Register fields [15:0] are not locked */
-                                               kPORT_UnlockRegister};
-    /* PORT0_0 (pin A17) is configured as SWDIO */
-    PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO);
-
-    const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */
-                                                kPORT_PullDown,
-                                                /* Low internal pull resistor value is selected. */
-                                                kPORT_LowPullResistor,
-                                                /* Fast slew rate is configured */
-                                                kPORT_FastSlewRate,
-                                                /* Passive input filter is disabled */
-                                                kPORT_PassiveFilterDisable,
-                                                /* Open drain output is disabled */
-                                                kPORT_OpenDrainDisable,
-                                                /* Low drive strength is configured */
-                                                kPORT_LowDriveStrength,
-                                                /* Pin is configured as SWCLK */
-                                                kPORT_MuxAlt1,
-                                                /* Digital input enabled */
-                                                kPORT_InputBufferEnable,
-                                                /* Digital input is not inverted */
-                                                kPORT_InputNormal,
-                                                /* Pin Control Register fields [15:0] are not locked */
-                                                kPORT_UnlockRegister};
-    /* PORT0_1 (pin A16) is configured as SWCLK */
-    PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK);
-
-    const port_pin_config_t DEBUG_SWD_SWO = {/* Internal pull-up/down resistor is disabled */
-                                             kPORT_PullDisable,
-                                             /* Low internal pull resistor value is selected. */
-                                             kPORT_LowPullResistor,
-                                             /* Fast slew rate is configured */
-                                             kPORT_FastSlewRate,
-                                             /* Passive input filter is disabled */
-                                             kPORT_PassiveFilterDisable,
-                                             /* Open drain output is disabled */
-                                             kPORT_OpenDrainDisable,
-                                             /* High drive strength is configured */
-                                             kPORT_HighDriveStrength,
-                                             /* Pin is configured as SWO */
-                                             kPORT_MuxAlt1,
-                                             /* Digital input enabled */
-                                             kPORT_InputBufferEnable,
-                                             /* Digital input is not inverted */
-                                             kPORT_InputNormal,
-                                             /* Pin Control Register fields [15:0] are not locked */
-                                             kPORT_UnlockRegister};
-    /* PORT0_2 (pin B16) is configured as SWO */
-    PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, &DEBUG_SWD_SWO);
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitLEDsPins:
-- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: C4, peripheral: GPIO1, signal: 'GPIO, 2', pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0,
-    direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B12, peripheral: GPIO0, signal: 'GPIO, 10', pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, direction: OUTPUT, slew_rate: fast, open_drain: disable,
-    drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: E10, peripheral: GPIO0, signal: 'GPIO, 27', pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitLEDsPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitLEDsPins(void)
-{
-    /* Enables the clock for GPIO0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Gpio0);
-    /* Enables the clock for GPIO1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Gpio1);
-    /* Enables the clock for PORT0 controller: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-    gpio_pin_config_t LED_RED_config = {
-        .pinDirection = kGPIO_DigitalOutput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_10 (pin B12)  */
-    GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
-
-    gpio_pin_config_t LED_GREEN_config = {
-        .pinDirection = kGPIO_DigitalOutput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_27 (pin E10)  */
-    GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
-
-    gpio_pin_config_t LED_BLUE_config = {
-        .pinDirection = kGPIO_DigitalOutput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO1_2 (pin C4)  */
-    GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
-
-    const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
-                                       kPORT_PullDisable,
-                                       /* Low internal pull resistor value is selected. */
-                                       kPORT_LowPullResistor,
-                                       /* Fast slew rate is configured */
-                                       kPORT_FastSlewRate,
-                                       /* Passive input filter is disabled */
-                                       kPORT_PassiveFilterDisable,
-                                       /* Open drain output is disabled */
-                                       kPORT_OpenDrainDisable,
-                                       /* Low drive strength is configured */
-                                       kPORT_LowDriveStrength,
-                                       /* Pin is configured as PIO0_10 */
-                                       kPORT_MuxAlt0,
-                                       /* Digital input enabled */
-                                       kPORT_InputBufferEnable,
-                                       /* Digital input is not inverted */
-                                       kPORT_InputNormal,
-                                       /* Pin Control Register fields [15:0] are not locked */
-                                       kPORT_UnlockRegister};
-    /* PORT0_10 (pin B12) is configured as PIO0_10 */
-    PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED);
-
-    const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
-                                         kPORT_PullDisable,
-                                         /* Low internal pull resistor value is selected. */
-                                         kPORT_LowPullResistor,
-                                         /* Fast slew rate is configured */
-                                         kPORT_FastSlewRate,
-                                         /* Passive input filter is disabled */
-                                         kPORT_PassiveFilterDisable,
-                                         /* Open drain output is disabled */
-                                         kPORT_OpenDrainDisable,
-                                         /* Low drive strength is configured */
-                                         kPORT_LowDriveStrength,
-                                         /* Pin is configured as PIO0_27 */
-                                         kPORT_MuxAlt0,
-                                         /* Digital input enabled */
-                                         kPORT_InputBufferEnable,
-                                         /* Digital input is not inverted */
-                                         kPORT_InputNormal,
-                                         /* Pin Control Register fields [15:0] are not locked */
-                                         kPORT_UnlockRegister};
-    /* PORT0_27 (pin E10) is configured as PIO0_27 */
-    PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN);
-
-    const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
-                                        kPORT_PullDisable,
-                                        /* Low internal pull resistor value is selected. */
-                                        kPORT_LowPullResistor,
-                                        /* Fast slew rate is configured */
-                                        kPORT_FastSlewRate,
-                                        /* Passive input filter is disabled */
-                                        kPORT_PassiveFilterDisable,
-                                        /* Open drain output is disabled */
-                                        kPORT_OpenDrainDisable,
-                                        /* Low drive strength is configured */
-                                        kPORT_LowDriveStrength,
-                                        /* Pin is configured as PIO1_2 */
-                                        kPORT_MuxAlt0,
-                                        /* Digital input enabled */
-                                        kPORT_InputBufferEnable,
-                                        /* Digital input is not inverted */
-                                        kPORT_InputNormal,
-                                        /* Pin Control Register fields [15:0] are not locked */
-                                        kPORT_UnlockRegister};
-    /* PORT1_2 (pin C4) is configured as PIO1_2 */
-    PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE);
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitBUTTONsPins:
-- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: C14, peripheral: GPIO0, signal: 'GPIO, 6', pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, direction: INPUT,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBUTTONsPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBUTTONsPins(void)
-{
-    /* Enables the clock for GPIO0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Gpio0);
-    /* Enables the clock for PORT0 controller: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    gpio_pin_config_t SW3_config = {
-        .pinDirection = kGPIO_DigitalInput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_6 (pin C14)  */
-    GPIO_PinInit(BOARD_INITBUTTONSPINS_SW3_GPIO, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3_config);
-
-    gpio_pin_config_t SW2_config = {
-        .pinDirection = kGPIO_DigitalInput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_23 (pin B7)  */
-    GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config);
-
-    const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
-                                   kPORT_PullDisable,
-                                   /* Low internal pull resistor value is selected. */
-                                   kPORT_LowPullResistor,
-                                   /* Fast slew rate is configured */
-                                   kPORT_FastSlewRate,
-                                   /* Passive input filter is disabled */
-                                   kPORT_PassiveFilterDisable,
-                                   /* Open drain output is disabled */
-                                   kPORT_OpenDrainDisable,
-                                   /* Low drive strength is configured */
-                                   kPORT_LowDriveStrength,
-                                   /* Pin is configured as PIO0_23 */
-                                   kPORT_MuxAlt0,
-                                   /* Digital input enabled */
-                                   kPORT_InputBufferEnable,
-                                   /* Digital input is not inverted */
-                                   kPORT_InputNormal,
-                                   /* Pin Control Register fields [15:0] are not locked */
-                                   kPORT_UnlockRegister};
-    /* PORT0_23 (pin B7) is configured as PIO0_23 */
-    PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2);
-
-    const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
-                                   kPORT_PullUp,
-                                   /* Low internal pull resistor value is selected. */
-                                   kPORT_LowPullResistor,
-                                   /* Fast slew rate is configured */
-                                   kPORT_FastSlewRate,
-                                   /* Passive input filter is disabled */
-                                   kPORT_PassiveFilterDisable,
-                                   /* Open drain output is disabled */
-                                   kPORT_OpenDrainDisable,
-                                   /* Low drive strength is configured */
-                                   kPORT_LowDriveStrength,
-                                   /* Pin is configured as PIO0_6 */
-                                   kPORT_MuxAlt0,
-                                   /* Digital input enabled */
-                                   kPORT_InputBufferEnable,
-                                   /* Digital input is not inverted */
-                                   kPORT_InputNormal,
-                                   /* Pin Control Register fields [15:0] are not locked */
-                                   kPORT_UnlockRegister};
-    /* PORT0_6 (pin C14) is configured as PIO0_6 */
-    PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/board/pin_mux.h

@@ -1,184 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*! @name PORT1_8 (coord A1), P1_8/J9[32]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT1               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 8U                   /*!<@brief PORT pin number */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 8U)      /*!<@brief PORT pin mask */
-                                                                        /* @} */
-
-/*! @name PORT1_9 (coord B1), P1_9/J9[30]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT1               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 9U                   /*!<@brief PORT pin number */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 9U)      /*!<@brief PORT pin mask */
-                                                                        /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitDEBUG_UARTPins(void);
-
-/*! @name PORT0_1 (coord A16), P0_1/SWCLK/J23[4]/D16[5]/J22[2]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U                   /*!<@brief PORT pin number */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U)      /*!<@brief PORT pin mask */
-                                                                          /* @} */
-
-/*! @name PORT0_0 (coord A17), P0_0/SWDIO/J23[2]/D16[6]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U                   /*!<@brief PORT pin number */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U)      /*!<@brief PORT pin mask */
-                                                                         /* @} */
-
-/*! @name PORT0_2 (coord B16), P0_2/SWO/J23[6]/D16[4]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 2U                   /*!<@brief PORT pin number */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 2U)      /*!<@brief PORT pin mask */
-                                                                       /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitSWD_DEBUGPins(void);
-
-/*! @name PORT1_2 (coord C4), P1_2/SJ4[1]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO1               /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 2U              /*!<@brief GPIO pin number */
-#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT1               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_BLUE_PIN 2U                   /*!<@brief PORT pin number */
-#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 2U)      /*!<@brief PORT pin mask */
-                                                             /* @} */
-
-/*! @name PORT0_10 (coord B12), P0_10/SJ5[1]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO0                /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 10U              /*!<@brief GPIO pin number */
-#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 10U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITLEDSPINS_LED_RED_PORT PORT0                /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_RED_PIN 10U                   /*!<@brief PORT pin number */
-#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 10U)      /*!<@brief PORT pin mask */
-                                                             /* @} */
-
-/*! @name PORT0_27 (coord E10), P0_27/SJ6[1]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO0                /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 27U              /*!<@brief GPIO pin number */
-#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 27U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT0                /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_GREEN_PIN 27U                   /*!<@brief PORT pin number */
-#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 27U)      /*!<@brief PORT pin mask */
-                                                               /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitLEDsPins(void);
-
-/*! @name PORT0_6 (coord C14), P0_6/J23[7]/SW3[3]/SW3[4]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO0               /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 6U              /*!<@brief GPIO pin number */
-#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITBUTTONSPINS_SW3_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW3_PIN 6U                   /*!<@brief PORT pin number */
-#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 6U)      /*!<@brief PORT pin mask */
-                                                           /* @} */
-
-/*! @name PORT0_23 (coord B7), P0_23/SJ9[1]/SW2[3]/SW2[4]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIO0                /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN 23U              /*!<@brief GPIO pin number */
-#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN_MASK (1U << 23U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITBUTTONSPINS_SW2_PORT PORT0                /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW2_PIN 23U                   /*!<@brief PORT pin number */
-#define BOARD_INITBUTTONSPINS_SW2_PIN_MASK (1U << 23U)      /*!<@brief PORT pin mask */
-                                                            /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitBUTTONsPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/device/system_MCXN947_cm33_core0.c

@@ -1,130 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          MCXN947VDF_cm33_core0
-**                          MCXN947VNL_cm33_core0
-**
-**     Compilers:           GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**                          Keil ARM C/C++ Compiler
-**                          MCUXpresso Compiler
-**
-**     Reference manual:    MCXNx4x Reference Manual
-**     Version:             rev. 2.0, 2023-02-01
-**     Build:               b231219
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
-**     SPDX-License-Identifier: BSD-3-Clause
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-**     Revisions:
-**     - rev. 1.0 (2022-10-01)
-**         Initial version
-**     - rev. 2.0 (2023-02-01)
-**         Initial version based on Rev. 2 Draft B
-**
-** ###################################################################
-*/
-
-/*!
- * @file MCXN947_cm33_core0
- * @version 2.0
- * @date 2023-02-01
- * @brief Device specific configuration file for MCXN947_cm33_core0
- *        (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "fsl_device_registers.h"
-
-
-
-
-
-
-/* ----------------------------------------------------------------------------
-   -- Core clock
-   ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
-   -- SystemInit()
-   ---------------------------------------------------------------------------- */
-
-__attribute__ ((weak)) void SystemInit (void) {
-#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
-  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
-  #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
-
-
-  SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
-#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-  SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
-
-  SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */
-
-  SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */
-
-#if defined(__MCUXPRESSO)
-    extern void(*const g_pfnVectors[]) (void);
-    SCB->VTOR = (uint32_t) &g_pfnVectors;
-#else
-    extern void *__Vectors;
-    SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-    /* enable the flash cache LPCAC */
-    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
-
-    /* Disable aGDET trigger the CHIP_RESET */
-    ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
-    ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
-    /* Disable aGDET interrupt and reset */
-    SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
-    SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
-    SPC0->GLITCH_DETECT_SC = 0x3C;
-    SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
-
-    /* Disable dGDET trigger the CHIP_RESET */
-    ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
-    ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
-    GDET0->GDET_ENABLE1 = 0;
-    GDET1->GDET_ENABLE1 = 0;
-
-  SystemInitHook();
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemCoreClockUpdate()
-   ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-
-
-
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemInitHook()
-   ---------------------------------------------------------------------------- */
-
-__attribute__ ((weak)) void SystemInitHook (void) {
-  /* Void implementation of the weak function. */
-}

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_gpio.c

@@ -1,440 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019, 2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_gpio.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.gpio"
-#endif
-
-#if defined(GPIO_RSTS)
-#define GPIO_RESETS_ARRAY GPIO_RSTS
-#endif
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
-static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
-#endif
-
-#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
-
-#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Array to map FGPIO instance number to clock name. */
-static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
-
-#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
-
-#if defined(GPIO_RESETS_ARRAY)
-/* Reset array */
-static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
-#endif
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * @brief Gets the GPIO instance according to the GPIO base
- *
- * @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
- * @retval GPIO instance
- */
-static uint32_t GPIO_GetInstance(GPIO_Type *base);
-#endif
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
-static uint32_t GPIO_GetInstance(GPIO_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
-    {
-        if (s_gpioBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_gpioBases));
-
-    return instance;
-}
-#endif
-/*!
- * brief Initializes a GPIO pin used by the board.
- *
- * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
- * Then, call the GPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration.
- * code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * endcode
- *
- * param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param pin    GPIO port pin number
- * param config GPIO pin configuration pointer
- */
-void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
-{
-    assert(NULL != config);
-
-#if defined(GPIO_RESETS_ARRAY)
-    RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
-#endif
-
-    if (config->pinDirection == kGPIO_DigitalInput)
-    {
-        base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
-    }
-    else
-    {
-        GPIO_PinWrite(base, pin, config->outputLogic);
-        base->PDDR |= GPIO_FIT_REG((1UL << pin));
-    }
-}
-
-#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
-void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
-{
-    info->feature = (uint16_t)base->VERID;
-    info->minor   = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT);
-    info->major   = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * brief Reads the GPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
-{
-    uint8_t instance;
-    PORT_Type *portBase;
-    instance = (uint8_t)GPIO_GetInstance(base);
-    portBase = s_portBases[instance];
-    return portBase->ISFR;
-}
-#else
-/*!
- * brief Read the GPIO interrupt status flags.
- *
- * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * return The current GPIO's interrupt status flag.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)
-{
-    return base->ISFR[0];
-}
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
- * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- *
- * return The current GPIO's interrupt status flag based on the selected interrupt channel.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)
-{
-    assert(channel < 2U);
-    return base->ISFR[channel];
-}
-#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
-/*!
- * brief Read individual pin's interrupt status flag.
- *
- * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
- * param pin GPIO specific pin number.
- * return The current selected pin's interrupt status flag.
- */
-uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
-{
-    return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT);
-}
-#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * brief Clears multiple GPIO pin interrupt status flags.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param mask GPIO pin number macro
- */
-void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
-{
-    uint8_t instance;
-    PORT_Type *portBase;
-    instance       = (uint8_t)GPIO_GetInstance(base);
-    portBase       = s_portBases[instance];
-    portBase->ISFR = mask;
-}
-#else
-/*!
- * brief Clears GPIO pin interrupt status flags.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param mask GPIO pin number macro
- */
-void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)
-{
-    base->ISFR[0] = GPIO_FIT_REG(mask);
-}
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param mask GPIO pin number macro
- * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- */
-void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)
-{
-    assert(channel < 2U);
-    base->ISFR[channel] = GPIO_FIT_REG(mask);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
-/*!
- * brief Clear GPIO individual pin's interrupt status flag.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
- * param pin GPIO specific pin number.
- */
-void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)
-{
-    base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U));
-}
-#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
-
-#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
- * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
- * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
- * endian data convention.
- *
- * param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param attribute GPIO checker attribute
- */
-void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
-{
-#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
-    base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT);
-#else
-    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
-                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
-#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */
-}
-#endif
-
-#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
-#endif
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * @brief Gets the FGPIO instance according to the GPIO base
- *
- * @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
- * @retval FGPIO instance
- */
-static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
-#endif
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
-    {
-        if (s_fgpioBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_fgpioBases));
-
-    return instance;
-}
-#endif
-#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
-/*!
- * brief Initializes the FGPIO peripheral.
- *
- * This function ungates the FGPIO clock.
- *
- * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- */
-void FGPIO_PortInit(FGPIO_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Ungate FGPIO periphral clock */
-    CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
-
-/*!
- * brief Initializes a FGPIO pin used by the board.
- *
- * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
- * Then, call the FGPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration:
- * code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * endcode
- *
- * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * param pin    FGPIO port pin number
- * param config FGPIO pin configuration pointer
- */
-void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
-{
-    assert(NULL != config);
-
-    if (config->pinDirection == kGPIO_DigitalInput)
-    {
-        base->PDDR &= ~(1UL << pin);
-    }
-    else
-    {
-        FGPIO_PinWrite(base, pin, config->outputLogic);
-        base->PDDR |= (1UL << pin);
-    }
-}
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * brief Reads the FGPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level-sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base)
-{
-    uint8_t instance;
-    instance = (uint8_t)FGPIO_GetInstance(base);
-    PORT_Type *portBase;
-    portBase = s_portBases[instance];
-    return portBase->ISFR;
-}
-
-/*!
- * brief Clears the multiple FGPIO pin interrupt status flag.
- *
- * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * param mask FGPIO pin number macro
- */
-void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask)
-{
-    uint8_t instance;
-    instance = (uint8_t)FGPIO_GetInstance(base);
-    PORT_Type *portBase;
-    portBase       = s_portBases[instance];
-    portBase->ISFR = mask;
-}
-#endif
-#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
- * words. Each 32-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
- * bytes in the GACR follow a standard little endian
- * data convention.
- *
- * param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * param attribute FGPIO checker attribute
- */
-void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
-{
-    base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) |
-                 ((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT);
-}
-#endif
-
-#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_gpio.h

@@ -1,799 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FSL_GPIO_H_
-#define FSL_GPIO_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup gpio
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief GPIO driver version. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
-/*@}*/
-
-#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
-#define GPIO_FIT_REG(value) \
-    ((uint8_t)(value)) /*!< For some platforms with 8-bit register width, cast the type to uint8_t */
-#else
-#define GPIO_FIT_REG(value) ((uint32_t)(value))
-#endif /*FSL_FEATURE_GPIO_REGISTERS_WIDTH*/
-
-/*! @brief GPIO direction definition */
-typedef enum _gpio_pin_direction
-{
-    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
-    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
-} gpio_pin_direction_t;
-
-#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
-/*! @brief GPIO checker attribute */
-typedef enum _gpio_checker_attribute
-{
-    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
-        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
-        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
-        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
-        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
-        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
-        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
-        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
-    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
-        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
-    kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
-} gpio_checker_attribute_t;
-#endif
-
-/*!
- * @brief The GPIO pin configuration structure.
- *
- * Each pin can only be configured as either an output pin or an input pin at a time.
- * If configured as an input pin, leave the outputConfig unused.
- * Note that in some use cases, the corresponding port property should be configured in advance
- *        with the PORT_SetPinConfig().
- */
-typedef struct _gpio_pin_config
-{
-    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
-    /* Output configurations; ignore if configured as an input pin */
-    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
-} gpio_pin_config_t;
-
-#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \
-     !(defined(FSL_FEATURE_SOC_PORT_COUNT))
-/*! @brief Configures the interrupt generation condition. */
-typedef enum _gpio_interrupt_config
-{
-    kGPIO_InterruptStatusFlagDisabled   = 0x0U,  /*!< Interrupt status flag is disabled. */
-    kGPIO_DMARisingEdge                 = 0x1U,  /*!< ISF flag and DMA request on rising edge. */
-    kGPIO_DMAFallingEdge                = 0x2U,  /*!< ISF flag and DMA request on falling edge. */
-    kGPIO_DMAEitherEdge                 = 0x3U,  /*!< ISF flag and DMA request on either edge. */
-    kGPIO_FlagRisingEdge                = 0x05U, /*!< Flag sets on rising edge. */
-    kGPIO_FlagFallingEdge               = 0x06U, /*!< Flag sets on falling edge. */
-    kGPIO_FlagEitherEdge                = 0x07U, /*!< Flag sets on either edge. */
-    kGPIO_InterruptLogicZero            = 0x8U,  /*!< Interrupt when logic zero. */
-    kGPIO_InterruptRisingEdge           = 0x9U,  /*!< Interrupt on rising edge. */
-    kGPIO_InterruptFallingEdge          = 0xAU,  /*!< Interrupt on falling edge. */
-    kGPIO_InterruptEitherEdge           = 0xBU,  /*!< Interrupt on either edge. */
-    kGPIO_InterruptLogicOne             = 0xCU,  /*!< Interrupt when logic one. */
-    kGPIO_ActiveHighTriggerOutputEnable = 0xDU,  /*!< Enable active high-trigger output. */
-    kGPIO_ActiveLowTriggerOutputEnable  = 0xEU,  /*!< Enable active low-trigger output. */
-} gpio_interrupt_config_t;
-#endif
-
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*! @brief Configures the selection of interrupt/DMA request/trigger output. */
-typedef enum _gpio_interrupt_selection
-{
-    kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
-    kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
-} gpio_interrupt_selection_t;
-#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
-
-#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
-/*! @brief GPIO version information. */
-typedef struct _gpio_version_info
-{
-    uint16_t feature; /*!< Feature Specification Number. */
-    uint8_t minor;    /*!< Minor Version Number. */
-    uint8_t major;    /*!< Major Version Number. */
-} gpio_version_info_t;
-#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
-
-#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
-/*! @brief GPIO pin and interrupt control. */
-typedef enum
-{
-    kGPIO_PinControlNonSecure          = 0x01U, /*!< Pin Control Non-Secure. */
-    kGPIO_InterruptControlNonSecure    = 0x02U, /*!< Interrupt Control Non-Secure. */
-    kGPIO_PinControlNonPrivilege       = 0x04U, /*!< Pin Control Non-Privilege. */
-    kGPIO_InterruptControlNonPrivilege = 0x08U, /*!< Interrupt Control Non-Privilege. */
-} gpio_pin_interrupt_control_t;
-#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
-
-/*! @} */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @addtogroup gpio_driver
- * @{
- */
-
-/*! @name GPIO Configuration */
-/*@{*/
-
-/*!
- * @brief Initializes a GPIO pin used by the board.
- *
- * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
- * Then, call the GPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration.
- * @code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * @endcode
- *
- * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin    GPIO port pin number
- * @param config GPIO pin configuration pointer
- */
-void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
-
-#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
-/*!
- * @brief Get GPIO version information.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param info GPIO version information
- */
-void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info);
-#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
-
-#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
-/*!
- * @brief lock or unlock secure privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask pin or interrupt macro
- */
-static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)
-{
-    base->LOCK |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Enable Pin Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNS |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Pin Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNS &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Enable Pin Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNP |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Pin Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNP &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Enable Interrupt Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNS |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Interrupt Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNS &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Enable Interrupt Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNP |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Interrupt Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNP &= GPIO_FIT_REG(~mask);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
-
-#if defined(FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL
-/*!
- * @brief Enable port input.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)
-{
-    base->PIDR &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Disable port input.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
-{
-    base->PIDR |= GPIO_FIT_REG(mask);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
-
-/*@}*/
-
-/*! @name GPIO Output Operations */
-/*@{*/
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
- *
- * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin number
- * @param output  GPIO pin output logic level.
- *        - 0: corresponding pin output low-logic level.
- *        - 1: corresponding pin output high-logic level.
- */
-static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    if (output == 0U)
-    {
-        base->PCOR = GPIO_FIT_REG(1UL << pin);
-    }
-    else
-    {
-        base->PSOR = GPIO_FIT_REG(1UL << pin);
-    }
-#else
-    if (output == 0U)
-    {
-        base->PDOR |= GPIO_FIT_REG(1UL << pin);
-    }
-    else
-    {
-        base->PDOR &= ~GPIO_FIT_REG(1UL << pin);
-    }
-#endif
-}
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 1.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    base->PSOR = GPIO_FIT_REG(mask);
-#else
-    base->PDOR |= GPIO_FIT_REG(mask);
-#endif
-}
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 0.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    base->PCOR = GPIO_FIT_REG(mask);
-#else
-    base->PDOR &= ~GPIO_FIT_REG(mask);
-#endif
-}
-
-/*!
- * @brief Reverses the current output logic of the multiple GPIO pins.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    base->PTOR = GPIO_FIT_REG(mask);
-#else
-    base->PDOR ^= GPIO_FIT_REG(mask);
-#endif
-}
-
-/*@}*/
-
-/*! @name GPIO Input Operations */
-/*@{*/
-
-/*!
- * @brief Reads the current input value of the GPIO port.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin number
- * @retval GPIO port input value
- *        - 0: corresponding pin input low-logic level.
- *        - 1: corresponding pin input high-logic level.
- */
-static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
-{
-    return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
-}
-
-/*@}*/
-
-/*! @name GPIO Interrupt */
-/*@{*/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * @brief Reads the GPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base);
-
-/*!
- * @brief Clears multiple GPIO pin interrupt status flags.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask);
-#else
-/*!
- * @brief Configures the gpio pin interrupt/DMA request.
- *
- * @param base    GPIO peripheral base pointer.
- * @param pin     GPIO pin number.
- * @param config  GPIO pin interrupt configuration.
- *        - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
- *        - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- *        - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- *        - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- *        - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- *        - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- *        - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- *        - #kGPIO_InterruptLogicZero  : Interrupt when logic zero.
- *        - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- *        - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- *        - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
- *        - #kGPIO_InterruptLogicOne   : Interrupt when logic one.
- *        - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- *        - #kGPIO_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
- */
-static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)
-{
-    assert(base);
-
-    base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config));
-}
-
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * @brief Configures the gpio pin interrupt/DMA request/trigger output channel selection.
- *
- * @param base    GPIO peripheral base pointer.
- * @param pin     GPIO pin number.
- * @param selection  GPIO pin interrupt output selection.
- *        - #kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
- *        - #kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.
- */
-static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)
-{
-    assert(base);
-
-    base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQS_MASK) | GPIO_ICR_IRQS(selection));
-}
-#endif
-/*!
- * @brief Read the GPIO interrupt status flags.
- *
- * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * @return The current GPIO's interrupt status flag.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base);
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * @brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
- *
- * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- * @return The current GPIO's interrupt status flag based on the selected interrupt channel.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel);
-#endif
-/*!
- * @brief Read individual pin's interrupt status flag.
- *
- * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
- * @param pin GPIO specific pin number.
- * @return The current selected pin's interrupt status flag.
- */
-uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin);
-
-/*!
- * @brief Clears GPIO pin interrupt status flags.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask);
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * @brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- */
-void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel);
-#endif
-/*!
- * @brief Clear GPIO individual pin's interrupt status flag.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
- * @param pin GPIO specific pin number.
- */
-void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin);
-
-/*!
- * @brief Reads the GPIO DMA request flags.
- *        The corresponding flag will be cleared automatically at the completion of the requested
- *        DMA transfer
- */
-static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base)
-{
-    assert(base);
-    return (base->ISFR[1]);
-}
-
-/*!
- * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins.
- *
- * @param base   GPIO peripheral base pointer.
- * @param mask   GPIO pin number macro.
- * @param config  GPIO pin interrupt configuration.
- *        - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
- *        - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- *        - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- *        - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- *        - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- *        - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- *        - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- *        - #kGPIO_InterruptLogicZero  : Interrupt when logic zero.
- *        - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- *        - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- *        - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
- *        - #kGPIO_InterruptLogicOne   : Interrupt when logic one.
- *        - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- *        - #kGPIO_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
- */
-static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)
-{
-    assert(base);
-
-    if (0UL != (mask & 0xffffUL))
-    {
-        base->GICLR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
-    }
-    mask = mask >> 16U;
-    if (mask != 0UL)
-    {
-        base->GICHR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
-    }
-}
-#endif
-
-#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
- * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
- * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
- * endian data convention.
- *
- * @param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param attribute GPIO checker attribute
- */
-void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
-#endif
-
-/*@}*/
-/*! @} */
-
-/*!
- * @addtogroup fgpio_driver
- * @{
- */
-
-/*
- * Introduces the FGPIO feature.
- *
- * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
- * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
- * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
- */
-
-#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
-
-/*! @name FGPIO Configuration */
-/*@{*/
-
-#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
-/*!
- * @brief Initializes the FGPIO peripheral.
- *
- * This function ungates the FGPIO clock.
- *
- * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- */
-void FGPIO_PortInit(FGPIO_Type *base);
-#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
-
-/*!
- * @brief Initializes a FGPIO pin used by the board.
- *
- * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
- * Then, call the FGPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration:
- * @code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * @endcode
- *
- * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param pin    FGPIO port pin number
- * @param config FGPIO pin configuration pointer
- */
-void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
-
-/*@}*/
-
-/*! @name FGPIO Output Operations */
-/*@{*/
-
-/*!
- * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
- *
- * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param pin     FGPIO pin number
- * @param output  FGPIOpin output logic level.
- *        - 0: corresponding pin output low-logic level.
- *        - 1: corresponding pin output high-logic level.
- */
-static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output)
-{
-    if (output == 0U)
-    {
-        base->PCOR = 1UL << pin;
-    }
-    else
-    {
-        base->PSOR = 1UL << pin;
-    }
-}
-
-/*!
- * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask)
-{
-    base->PSOR = mask;
-}
-
-/*!
- * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask)
-{
-    base->PCOR = mask;
-}
-
-/*!
- * @brief Reverses the current output logic of the multiple FGPIO pins.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
-{
-    base->PTOR = mask;
-}
-/*@}*/
-
-/*! @name FGPIO Input Operations */
-/*@{*/
-
-/*!
- * @brief Reads the current input value of the FGPIO port.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param pin  FGPIO pin number
- * @retval FGPIO port input value
- *        - 0: corresponding pin input low-logic level.
- *        - 1: corresponding pin input high-logic level.
- */
-static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
-{
-    return (((base->PDIR) >> pin) & 0x01U);
-}
-/*@}*/
-
-/*! @name FGPIO Interrupt */
-/*@{*/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-
-/*!
- * @brief Reads the FGPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level-sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base);
-
-/*!
- * @brief Clears the multiple FGPIO pin interrupt status flag.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
-#endif
-#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
- * words. Each 32-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
- * bytes in the GACR follow a standard little endian
- * data convention.
- *
- * @param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param attribute FGPIO checker attribute
- */
-void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
-#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
-
-/*@}*/
-
-#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-
-#endif /* FSL_GPIO_H_*/

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_lpflexcomm.c

@@ -1,380 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_common.h"
-#include "fsl_lpflexcomm.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm"
-#endif
-
-/*!
- * @brief Used for conversion between `void*` and `uint32_t`.
- */
-typedef union pvoid_to_u32
-{
-    void *pvoid;
-    uint32_t u32;
-} pvoid_to_u32_t;
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*! @brief check whether lpflexcomm supports peripheral type */
-static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph);
-
-/*! @brief Changes LP_FLEXCOMM mode. */
-static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock);
-
-/*! @brief Common LPFLEXCOMM IRQhandle. */
-static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance);
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Array to map LP_FLEXCOMM instance number to base address. */
-static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS;
-
-/*! @brief Array to map LP_FLEXCOMM instance PTRS. */
-static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS;
-
-/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
-static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
-
-/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
-static void *s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
-
-/*! @brief Array to map LP_FLEXCOMM instance number to IRQ number. */
-IRQn_Type const kFlexcommIrqs[] = LP_FLEXCOMM_IRQS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief IDs of clock for each LP_FLEXCOMM module */
-static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
-/*! @brief Pointers to LP_FLEXCOMM resets for each instance. */
-static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS;
-#endif
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* check whether lpflexcomm supports peripheral type */
-static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph)
-{
-    if (periph == LP_FLEXCOMM_PERIPH_NONE)
-    {
-        return true;
-    }
-    else if (periph <= LP_FLEXCOMM_PERIPH_LPI2C)
-    {
-        return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
-    }
-    else if (periph == LP_FLEXCOMM_PERIPH_LPI2CAndLPUART)
-    {
-        return true;
-    }
-    else
-    {
-        return false;
-    }
-}
-
-/*! @brief Returns for LP_FLEXCOMM base address. */
-uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance)
-{
-    if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs))
-    {
-        return s_lpflexcommBaseAddrs[instance];
-    }
-    return 0U;
-}
-
-/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
-uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance)
-{
-    LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
-    return base->ISTAT;
-}
-
-/* Get the index corresponding to the LP_FLEXCOMM */
-/*! brief Returns instance number for LP_FLEXCOMM module with given base address. */
-uint32_t LP_FLEXCOMM_GetInstance(void *base)
-{
-    uint32_t i;
-    pvoid_to_u32_t BaseAddr;
-    BaseAddr.pvoid = base;
-
-    for (i = 0U; i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs); i++)
-    {
-        if (BaseAddr.u32 == s_lpflexcommBaseAddrs[i])
-        {
-            break;
-        }
-    }
-
-    assert(i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
-    return i;
-}
-
-/* Changes LP_FLEXCOMM mode */
-static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock)
-{
-    assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART);
-    LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
-
-    /* Check whether peripheral type is present */
-    if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph))
-    {
-        return kStatus_OutOfRange;
-    }
-
-    /* Flexcomm is locked to different peripheral type than expected  */
-    if (((base->PSELID & LP_FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
-        ((base->PSELID & LP_FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
-    {
-        return kStatus_Fail;
-    }
-
-    /* Check if we are asked to lock */
-    if (lock != 0)
-    {
-        base->PSELID = (uint32_t)periph | LP_FLEXCOMM_PSELID_LOCK_MASK;
-    }
-    else
-    {
-        base->PSELID = (uint32_t)periph;
-    }
-
-    return kStatus_Success;
-}
-
-/*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
-status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
-{
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the peripheral clock */
-    CLOCK_EnableClock(s_lpflexcommClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
-    /* Reset the LP_FLEXCOMM module before configuring it.*/
-    RESET_ClearPeripheralReset(s_lpflexcommResets[instance]);
-#endif
-    /* Set the LP_FLEXCOMM to given peripheral */
-    return LP_FLEXCOMM_SetPeriph(instance, periph, 0);
-}
-
-/*! brief Deinitializes LP_FLEXCOMM. */
-void LP_FLEXCOMM_Deinit(uint32_t instance)
-{
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the peripheral clock */
-    CLOCK_DisableClock(s_lpflexcommClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-    RESET_SetPeripheralReset(s_lpflexcommResets[instance]);
-}
-
-/*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
- * LP_FLEXCOMM mode */
-void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
-                               lpflexcomm_irq_handler_t handler,
-                               void *lpflexcommHandle,
-                               LP_FLEXCOMM_PERIPH_T periph)
-{
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
-    /* Clear handler first to avoid execution of the handler with wrong handle */
-    s_lpflexcommIrqHandler[periph][instance] = NULL;
-    s_lpflexcommHandle[periph][instance]     = lpflexcommHandle;
-    s_lpflexcommIrqHandler[periph][instance] = handler;
-}
-
-static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance)
-{
-    uint32_t interruptStat;
-
-    interruptStat = LP_FLEXCOMM_GetInterruptStatus(instance);
-    if ((interruptStat &
-         ((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag | (uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U)
-    {
-        if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance] != NULL)
-        {
-            s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance](
-                instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C][instance]);
-        }
-    }
-    if ((interruptStat & ((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag | (uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U)
-    {
-        if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance] != NULL)
-        {
-            s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance](
-                instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPUART][instance]);
-        }
-    }
-    if (((interruptStat & (uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U)
-    {
-        if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance] != NULL)
-        {
-            s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance](
-                instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPSPI][instance]);
-        }
-    }
-    SDK_ISR_EXIT_BARRIER;
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-#if defined(LP_FLEXCOMM0)
-void LP_FLEXCOMM0_DriverIRQHandler(void);
-void LP_FLEXCOMM0_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(0U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM1)
-void LP_FLEXCOMM1_DriverIRQHandler(void);
-void LP_FLEXCOMM1_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(1U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM2)
-void LP_FLEXCOMM2_DriverIRQHandler(void);
-void LP_FLEXCOMM2_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(2U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM3)
-void LP_FLEXCOMM3_DriverIRQHandler(void);
-void LP_FLEXCOMM3_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(3U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM4)
-void LP_FLEXCOMM4_DriverIRQHandler(void);
-void LP_FLEXCOMM4_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(4U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM5)
-void LP_FLEXCOMM5_DriverIRQHandler(void);
-void LP_FLEXCOMM5_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(5U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM6)
-void LP_FLEXCOMM6_DriverIRQHandler(void);
-void LP_FLEXCOMM6_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(6U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM7)
-void LP_FLEXCOMM7_DriverIRQHandler(void);
-void LP_FLEXCOMM7_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(7U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM8)
-void LP_FLEXCOMM8_DriverIRQHandler(void);
-void LP_FLEXCOMM8_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(8U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM9)
-void LP_FLEXCOMM9_DriverIRQHandler(void);
-void LP_FLEXCOMM9_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(9U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM10)
-void LP_FLEXCOMM10_DriverIRQHandler(void);
-void LP_FLEXCOMM10_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(10U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM11)
-void LP_FLEXCOMM11_DriverIRQHandler(void);
-void LP_FLEXCOMM11_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(11U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM12)
-void LP_FLEXCOMM12_DriverIRQHandler(void);
-void LP_FLEXCOMM12_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(12U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM13)
-void LP_FLEXCOMM13_DriverIRQHandler(void);
-void LP_FLEXCOMM13_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(13U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM17)
-void LP_FLEXCOMM17_DriverIRQHandler(void);
-void LP_FLEXCOMM17_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(17U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM18)
-void LP_FLEXCOMM18_DriverIRQHandler(void);
-void LP_FLEXCOMM18_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(18U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM19)
-void LP_FLEXCOMM19_DriverIRQHandler(void);
-void LP_FLEXCOMM19_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(19U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM20)
-void LP_FLEXCOMM20_DriverIRQHandler(void);
-void LP_FLEXCOMM20_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(20U);
-}
-#endif

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_lpflexcomm.h

@@ -1,88 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef FSL_LP_FLEXCOMM_H_
-#define FSL_LP_FLEXCOMM_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpflexcomm_driver
- * @{
- */
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief FlexCOMM driver version. */
-#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
-/*@}*/
-
-/*! @brief LP_FLEXCOMM peripheral modes. */
-typedef enum
-{
-    LP_FLEXCOMM_PERIPH_NONE,               /*!< No peripheral */
-    LP_FLEXCOMM_PERIPH_LPUART,             /*!< LPUART peripheral */
-    LP_FLEXCOMM_PERIPH_LPSPI,              /*!< LPSPI Peripheral */
-    LP_FLEXCOMM_PERIPH_LPI2C,              /*!< LPI2C Peripheral */
-    LP_FLEXCOMM_PERIPH_LPI2CAndLPUART = 7, /*!< LPI2C and LPUART Peripheral */
-} LP_FLEXCOMM_PERIPH_T;
-
-/*! @brief LP_FLEXCOMM interrupt source flags. */
-enum _lpflexcomm_interrupt_flag
-{
-    kLPFLEXCOMM_I2cSlaveInterruptFlag  = LP_FLEXCOMM_ISTAT_I2CS_MASK,   /* LPI2C slave interrupt. */
-    kLPFLEXCOMM_I2cMasterInterruptFlag = LP_FLEXCOMM_ISTAT_I2CM_MASK,   /* LPI2C master interrupt. */
-    kLPFLEXCOMM_SpiInterruptFlag       = LP_FLEXCOMM_ISTAT_SPI_MASK,    /* LPSPI interrupt. */
-    kLPFLEXCOMM_UartRxInterruptFlag    = LP_FLEXCOMM_ISTAT_UARTRX_MASK, /* LPUART RX interrupt. */
-    kLPFLEXCOMM_UartTxInterruptFlag    = LP_FLEXCOMM_ISTAT_UARTTX_MASK, /* LPUART TX interrupt. */
-
-    kLPFLEXCOMM_AllInterruptFlag = kLPFLEXCOMM_I2cSlaveInterruptFlag | kLPFLEXCOMM_I2cMasterInterruptFlag |
-                                   kLPFLEXCOMM_SpiInterruptFlag | kLPFLEXCOMM_UartRxInterruptFlag |
-                                   kLPFLEXCOMM_UartTxInterruptFlag,
-};
-
-/*! @brief Typedef for interrupt handler. */
-typedef void (*lpflexcomm_irq_handler_t)(uint32_t instance, void *handle);
-
-/*! @brief Array with IRQ number for each LP_FLEXCOMM module. */
-extern IRQn_Type const kFlexcommIrqs[];
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */
-uint32_t LP_FLEXCOMM_GetInstance(void *base);
-
-/*! @brief Returns for LP_FLEXCOMM base address. */
-uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance);
-
-/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
-uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance);
-
-/*! @brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
-status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph);
-
-/*! @brief Deinitializes LP_FLEXCOMM. */
-void LP_FLEXCOMM_Deinit(uint32_t instance);
-
-/*! @brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
- * LP_FLEXCOMM mode */
-void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
-                               lpflexcomm_irq_handler_t handler,
-                               void *lpflexcommHandle,
-                               LP_FLEXCOMM_PERIPH_T periph);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*@}*/
-
-#endif /* FSL_LP_FLEXCOMM_H_*/

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_port.h

@@ -1,679 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef FSL_PORT_H_
-#define FSL_PORT_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup port
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.port"
-#endif
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief PORT driver version. */
-#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
-
-#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
-/*! @brief Internal resistor pull feature selection */
-enum _port_pull
-{
-    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
-    kPORT_PullDown    = 2U, /*!< Internal pull-down resistor is enabled. */
-    kPORT_PullUp      = 3U, /*!< Internal pull-up resistor is enabled. */
-};
-#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
-
-#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
-/*! @brief Internal resistor pull value selection */
-enum _port_pull_value
-{
-    kPORT_LowPullResistor  = 0U, /*!< Low internal pull resistor value is selected. */
-    kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */
-};
-#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
-
-#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
-/*! @brief Slew rate selection */
-enum _port_slew_rate
-{
-    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
-    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
-};
-#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
-
-#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-/*! @brief Open Drain feature enable/disable */
-enum _port_open_drain_enable
-{
-    kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
-    kPORT_OpenDrainEnable  = 1U, /*!< Open drain output is enabled. */
-};
-#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
-
-#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
-/*! @brief Passive filter feature enable/disable */
-enum _port_passive_filter_enable
-{
-    kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
-    kPORT_PassiveFilterEnable  = 1U, /*!< Passive input filter is enabled. */
-};
-#endif
-
-#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
-/*! @brief Configures the drive strength. */
-enum _port_drive_strength
-{
-    kPORT_LowDriveStrength  = 0U, /*!< Low-drive strength is configured. */
-    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
-};
-#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
-
-#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
-/*! @brief Configures the drive strength1. */
-enum _port_drive_strength1
-{
-    kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */
-    kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */
-};
-#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
-
-#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
-/*! @brief input buffer disable/enable. */
-enum _port_input_buffer
-{
-    kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */
-    kPORT_InputBufferEnable  = 1U, /*!< Digital input is enabled */
-};
-#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
-
-#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
-/*! @brief Digital input is not inverted or it is inverted. */
-enum _port_invet_input
-{
-    kPORT_InputNormal = 0U, /*!< Digital input is not inverted */
-    kPORT_InputInvert = 1U, /*!< Digital input is inverted */
-};
-#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
-
-#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
-/*! @brief Unlock/lock the pin control register field[15:0] */
-enum _port_lock_register
-{
-    kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
-    kPORT_LockRegister   = 1U, /*!< Pin Control Register fields [15:0] are locked. */
-};
-#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
-
-#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
-/*! @brief Pin mux selection */
-typedef enum _port_mux
-{
-    kPORT_PinDisabledOrAnalog = 0U,  /*!< Corresponding pin is disabled, but is used as an analog pin. */
-    kPORT_MuxAsGpio           = 1U,  /*!< Corresponding pin is configured as GPIO. */
-    kPORT_MuxAlt0             = 0U,  /*!< Chip-specific */
-    kPORT_MuxAlt1             = 1U,  /*!< Chip-specific */
-    kPORT_MuxAlt2             = 2U,  /*!< Chip-specific */
-    kPORT_MuxAlt3             = 3U,  /*!< Chip-specific */
-    kPORT_MuxAlt4             = 4U,  /*!< Chip-specific */
-    kPORT_MuxAlt5             = 5U,  /*!< Chip-specific */
-    kPORT_MuxAlt6             = 6U,  /*!< Chip-specific */
-    kPORT_MuxAlt7             = 7U,  /*!< Chip-specific */
-    kPORT_MuxAlt8             = 8U,  /*!< Chip-specific */
-    kPORT_MuxAlt9             = 9U,  /*!< Chip-specific */
-    kPORT_MuxAlt10            = 10U, /*!< Chip-specific */
-    kPORT_MuxAlt11            = 11U, /*!< Chip-specific */
-    kPORT_MuxAlt12            = 12U, /*!< Chip-specific */
-    kPORT_MuxAlt13            = 13U, /*!< Chip-specific */
-    kPORT_MuxAlt14            = 14U, /*!< Chip-specific */
-    kPORT_MuxAlt15            = 15U, /*!< Chip-specific */
-} port_mux_t;
-#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
-/*! @brief Configures the interrupt generation condition. */
-typedef enum _port_interrupt
-{
-    kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
-#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT)
-    kPORT_DMARisingEdge  = 0x1U, /*!< DMA request on rising edge. */
-    kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
-    kPORT_DMAEitherEdge  = 0x3U, /*!< DMA request on either edge. */
-#endif
-#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT)
-    kPORT_FlagRisingEdge  = 0x05U, /*!< Flag sets on rising edge. */
-    kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
-    kPORT_FlagEitherEdge  = 0x07U, /*!< Flag sets on either edge. */
-#endif
-    kPORT_InterruptLogicZero   = 0x8U, /*!< Interrupt when logic zero. */
-    kPORT_InterruptRisingEdge  = 0x9U, /*!< Interrupt on rising edge. */
-    kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
-    kPORT_InterruptEitherEdge  = 0xBU, /*!< Interrupt on either edge. */
-    kPORT_InterruptLogicOne    = 0xCU, /*!< Interrupt when logic one. */
-#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT)
-    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
-    kPORT_ActiveLowTriggerOutputEnable  = 0xEU, /*!< Enable active low-trigger output. */
-#endif
-} port_interrupt_t;
-#endif
-
-#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
-/*! @brief Digital filter clock source selection */
-typedef enum _port_digital_filter_clock_source
-{
-    kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
-    kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
-} port_digital_filter_clock_source_t;
-
-/*! @brief PORT digital filter feature configuration definition */
-typedef struct _port_digital_filter_config
-{
-    uint32_t digitalFilterWidth;                    /*!< Set digital filter width */
-    port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
-} port_digital_filter_config_t;
-#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
-
-#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
-/*! @brief PORT pin configuration structure */
-typedef struct _port_pin_config
-{
-#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
-    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
-#else
-    uint16_t : 2;
-#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
-
-#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
-    uint16_t pullValueSelect : 1; /*!< Pull value select */
-#endif                            /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
-
-#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
-    uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
-
-#if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE)
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
-
-#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
-    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
-
-#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
-
-#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
-    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
-#else
-    uint16_t : 1;
-#endif
-
-#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
-    uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
-
-#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
-    uint16_t mux : 3; /*!< Pin mux Configure */
-    uint16_t : 1;
-#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
-    uint16_t mux : 4; /*!< Pin mux Configure */
-#else
-    uint16_t : 4;
-#endif
-
-#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
-    uint16_t inputBuffer : 1; /*!< Input Buffer Configure */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
-
-#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
-    uint16_t invertInput : 1; /*!< Invert Input Configure */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
-
-    uint16_t : 1;
-
-#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
-    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
-#else
-    uint16_t : 1;
-#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
-} port_pin_config_t;
-#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
-
-#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
-/*! @brief PORT version information. */
-typedef struct _port_version_info
-{
-    uint16_t feature; /*!< Feature Specification Number. */
-    uint8_t minor;    /*!< Minor Version Number. */
-    uint8_t major;    /*!< Major Version Number. */
-} port_version_info_t;
-#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
-
-#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
-/*! @brief PORT voltage range. */
-typedef enum _port_voltage_range
-{
-    kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */
-    kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */
-} port_voltage_range_t;
-#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
-/*! @name Configuration */
-/*@{*/
-
-#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
-/*!
- * @brief Get PORT version information.
- *
- * @param base PORT peripheral base pointer
- * @param info PORT version information
- */
-static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)
-{
-    uint32_t verid = base->VERID;
-    info->feature  = (uint16_t)verid;
-    info->minor    = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT);
-    info->major    = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT);
-}
-#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
-
-#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
-/*!
- * @brief Get PORT version information.
- *
- * @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and
- *         PORTC_CONFIG[RANGE] does not take effect.
- *
- * @param base PORT peripheral base pointer
- * @param range port voltage range
- */
-static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)
-{
-    base->CONFIG = (uint32_t)range;
-}
-#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
-
-/*!
- * @brief Sets the port PCR register.
- *
- * This is an example to define an input pin or output pin PCR configuration.
- * @code
- * // Define a digital input pin PCR configuration
- * port_pin_config_t config = {
- *      kPORT_PullUp,
- *      kPORT_FastSlewRate,
- *      kPORT_PassiveFilterDisable,
- *      kPORT_OpenDrainDisable,
- *      kPORT_LowDriveStrength,
- *      kPORT_MuxAsGpio,
- *      kPORT_UnLockRegister,
- * };
- * @endcode
- *
- * @param base   PORT peripheral base pointer.
- * @param pin    PORT pin number.
- * @param config PORT PCR register configuration structure.
- */
-static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
-{
-    assert(config);
-    uint32_t addr                = (uint32_t)&base->PCR[pin];
-    *(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config);
-}
-
-/*!
- * @brief Sets the port PCR register for multiple pins.
- *
- * This is an example to define input pins or output pins PCR configuration.
- * @code
- * Define a digital input pin PCR configuration
- * port_pin_config_t config = {
- *      kPORT_PullUp ,
- *      kPORT_PullEnable,
- *      kPORT_FastSlewRate,
- *      kPORT_PassiveFilterDisable,
- *      kPORT_OpenDrainDisable,
- *      kPORT_LowDriveStrength,
- *      kPORT_MuxAsGpio,
- *      kPORT_UnlockRegister,
- * };
- * @endcode
- *
- * @param base   PORT peripheral base pointer.
- * @param mask   PORT pin number macro.
- * @param config PORT PCR register configuration structure.
- */
-static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
-{
-    assert(config);
-
-    uint16_t pcrl = *((const uint16_t *)(const void *)config);
-
-    if (0U != (mask & 0xffffU))
-    {
-        base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
-    }
-    if (0U != (mask >> 16))
-    {
-        base->GPCHR = (mask & 0xffff0000U) | pcrl;
-    }
-}
-
-#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
-/*!
- * @brief Sets the port interrupt configuration in PCR register for multiple pins.
- *
- * @param base   PORT peripheral base pointer.
- * @param mask   PORT pin number macro.
- * @param config  PORT pin interrupt configuration.
- *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
- *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
- *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
- *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
- *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
- *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
- *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
- */
-static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
-{
-    assert(config);
-
-    if (0U != ((uint32_t)mask & 0xffffU))
-    {
-        base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
-    }
-    mask = mask >> 16;
-    if (0U != mask)
-    {
-        base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
-    }
-}
-#endif
-
-/*!
- * @brief Configures the pin muxing.
- *
- * @param base  PORT peripheral base pointer.
- * @param pin   PORT pin number.
- * @param mux   pin muxing slot selection.
- *        - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
- *        - #kPORT_MuxAsGpio          : Set as GPIO.
- *        - #kPORT_MuxAlt2            : chip-specific.
- *        - #kPORT_MuxAlt3            : chip-specific.
- *        - #kPORT_MuxAlt4            : chip-specific.
- *        - #kPORT_MuxAlt5            : chip-specific.
- *        - #kPORT_MuxAlt6            : chip-specific.
- *        - #kPORT_MuxAlt7            : chip-specific.
- * @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
- *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
- *         reset to zero : kPORT_PinDisabledOrAnalog).
- *        This function is recommended to use to reset the pin mux
- *
- */
-static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
-{
-    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
-}
-#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
-
-#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
-
-/*!
- * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
- *
- * @param base    PORT peripheral base pointer.
- * @param mask    PORT pin number macro.
- * @param enable  PORT digital filter configuration.
- */
-static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
-{
-    if (enable == true)
-    {
-        base->DFER |= mask;
-    }
-    else
-    {
-        base->DFER &= ~mask;
-    }
-}
-
-/*!
- * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
- *
- * @param base   PORT peripheral base pointer.
- * @param config PORT digital filter configuration structure.
- */
-static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
-{
-    assert(config);
-
-    base->DFCR = PORT_DFCR_CS(config->clockSource);
-    base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
-}
-
-#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
-/*@}*/
-
-/*! @name Interrupt */
-/*@{*/
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
-/*!
- * @brief Configures the port pin interrupt/DMA request.
- *
- * @param base    PORT peripheral base pointer.
- * @param pin     PORT pin number.
- * @param config  PORT pin interrupt configuration.
- *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
- *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
- *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
- *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
- *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
- *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
- *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
- */
-static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
-{
-    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
-}
-#endif
-
-#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
-/*!
- * @brief Configures the port pin drive strength.
- *
- * @param base      PORT peripheral base pointer.
- * @param pin       PORT pin number.
- * @param strength  PORT pin drive strength
- *        - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
- *        - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
- */
-static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)
-{
-    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
-}
-#endif
-
-#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
-/*!
- * @brief Enables the port pin double drive strength.
- *
- * @param base      PORT peripheral base pointer.
- * @param pin       PORT pin number.
- * @param enable  PORT pin drive strength configuration.
- */
-static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)
-{
-    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable);
-}
-#endif
-
-#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
-/*!
- * @brief Configures the port pin pull value.
- *
- * @param base      PORT peripheral base pointer.
- * @param pin       PORT pin number.
- * @param value  PORT pin pull value
- *        - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.
- *        - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.
- */
-static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)
-{
-    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value);
-}
-#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
-/*!
- * @brief Reads the whole port status flag.
- *
- * If a pin is configured to generate the DMA request,  the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * @param base PORT peripheral base pointer.
- * @return Current port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 16 have the interrupt.
- */
-static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
-{
-    return base->ISFR;
-}
-
-/*!
- * @brief Clears the multiple pin interrupt status flag.
- *
- * @param base PORT peripheral base pointer.
- * @param mask PORT pin number macro.
- */
-static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
-{
-    base->ISFR = mask;
-}
-#endif
-
-#if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT
-/*!
- * @brief Get EFT detect flags.
- *
- * @param base PORT peripheral base pointer
- * @return EFT detect flags
- */
-static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)
-{
-    return base->EDFR;
-}
-
-/*!
- * @brief Enable EFT detect interrupts.
- *
- * @param base PORT peripheral base pointer
- * @param interrupt EFT detect interrupt
- */
-static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
-{
-    base->EDIER |= interrupt;
-}
-
-/*!
- * @brief Disable EFT detect interrupts.
- *
- * @param base PORT peripheral base pointer
- * @param interrupt EFT detect interrupt
- */
-static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
-{
-    base->EDIER &= ~interrupt;
-}
-
-/*!
- * @brief Clear all low EFT detector.
- *
- * @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the
- * PORTB_EDCR does not take effect.
- * @param base PORT peripheral base pointer
- * @param interrupt EFT detect interrupt
- */
-static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)
-{
-    base->EDCR |= PORT_EDCR_EDLC_MASK;
-    base->EDCR &= ~PORT_EDCR_EDLC_MASK;
-}
-
-/*!
- * @brief Clear all high EFT detector.
- *
- * @param base PORT peripheral base pointer
- * @param interrupt EFT detect interrupt
- */
-static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
-{
-    base->EDCR |= PORT_EDCR_EDHC_MASK;
-    base->EDCR &= ~PORT_EDCR_EDHC_MASK;
-}
-#endif /* FSL_FEATURE_PORT_SUPPORT_EFT */
-
-/*@}*/
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* FSL_PORT_H_ */

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_reset.c

@@ -1,102 +0,0 @@
-/*
- * Copyright 2022, NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_common.h"
-#include "fsl_reset.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.reset"
-#endif
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
-/*!
- * brief Assert reset to peripheral.
- *
- * Asserts reset signal to specified peripheral module.
- *
- * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
-{
-    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
-    const uint32_t bitPos   = ((uint32_t)peripheral & 0x0000FFFFu);
-    const uint32_t bitMask  = 1UL << bitPos;
-    volatile uint32_t *pResetCtrl;
-
-    assert(bitPos < 32u);
-
-    /* reset register is in SYSCON */
-    /* set bit */
-    SYSCON->PRESETCTRLSET[regIndex] = bitMask;
-    /* wait until it reads 0b1 */
-    pResetCtrl = &(SYSCON->PRESETCTRL0);
-    while (0u == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask))
-    {
-    }
-}
-
-/*!
- * brief Clear reset to peripheral.
- *
- * Clears reset signal to specified peripheral module, allows it to operate.
- *
- * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
-{
-    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
-    const uint32_t bitPos   = ((uint32_t)peripheral & 0x0000FFFFu);
-    const uint32_t bitMask  = 1UL << bitPos;
-    volatile uint32_t *pResetCtrl;
-
-    assert(bitPos < 32u);
-
-    /* reset register is in SYSCON */
-
-    /* clear bit */
-    SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
-    /* wait until it reads 0b0 */
-    pResetCtrl = &(SYSCON->PRESETCTRL0);
-    while (bitMask == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask))
-    {
-    }
-}
-
-/*!
- * brief Reset peripheral module.
- *
- * Reset peripheral module.
- *
- * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_PeripheralReset(reset_ip_name_t peripheral)
-{
-    RESET_SetPeripheralReset(peripheral);
-    RESET_ClearPeripheralReset(peripheral);
-}
-
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/drivers/fsl_reset.h

@@ -1,261 +0,0 @@
-/*
- * Copyright 2022, NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _FSL_RESET_H_
-#define _FSL_RESET_H_
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-#include "fsl_device_registers.h"
-
-/*!
- * @addtogroup reset
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief reset driver version 2.4.0 */
-#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
-/*@}*/
-
-/*!
- * @brief Enumeration for peripheral reset control bits
- *
- * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
- */
-typedef enum _SYSCON_RSTn
-{
-    kFMU_RST_SHIFT_RSTn     = 0 | 9U,  /**< Flash management unit reset control */
-    kFLEXSPI_RST_SHIFT_RSTn = 0 | 11U, /**< FLEXSPI reset control */
-    kMUX_RST_SHIFT_RSTn     = 0 | 12U, /**< Input mux reset control */
-    kPORT0_RST_SHIFT_RSTn   = 0 | 13U, /**< PORT0 reset control */
-    kPORT1_RST_SHIFT_RSTn   = 0 | 14U, /**< PORT1 reset control */
-    kPORT2_RST_SHIFT_RSTn   = 0 | 15U, /**< PORT2 reset control */
-    kPORT3_RST_SHIFT_RSTn   = 0 | 16U, /**< PORT3 reset control */
-    kPORT4_RST_SHIFT_RSTn   = 0 | 17U, /**< PORT4 reset control */
-    kGPIO0_RST_SHIFT_RSTn   = 0 | 19U, /**< GPIO0 reset control */
-    kGPIO1_RST_SHIFT_RSTn   = 0 | 20U, /**< GPIO1 reset control */
-    kGPIO2_RST_SHIFT_RSTn   = 0 | 21U, /**< GPIO2 reset control */
-    kGPIO3_RST_SHIFT_RSTn   = 0 | 22U, /**< GPIO3 reset control */
-    kGPIO4_RST_SHIFT_RSTn   = 0 | 23U, /**< GPIO4 reset control */
-    kPINT_RST_SHIFT_RSTn    = 0 | 25U, /**< Pin interrupt (PINT) reset control */
-    kDMA0_RST_SHIFT_RSTn    = 0 | 26U, /**< DMA0 reset control */
-    kCRC_RST_SHIFT_RSTn     = 0 | 27U, /**< CRC reset control */
-    kMAILBOX_RST_SHIFT_RSTn = 0 | 31U, /**< Mailbox reset control */
-
-    kMRT_RST_SHIFT_RSTn         = 65536 | 0U,  /**< Multi-rate timer (MRT) reset control */
-    kOSTIMER_RST_SHIFT_RSTn     = 65536 | 1U,  /**< OSTimer reset control */
-    kSCT_RST_SHIFT_RSTn         = 65536 | 2U,  /**< SCTimer/PWM(SCT) reset control */
-    kADC0_RST_SHIFT_RSTn        = 65536 | 3U,  /**< ADC0 reset control */
-    kADC1_RST_SHIFT_RSTn        = 65536 | 4U,  /**< ADC1 reset control */
-    kDAC0_RST_SHIFT_RSTn        = 65536 | 5U,  /**< DAC0 reset control */
-    kEVSIM0_RST_SHIFT_RSTn      = 65536 | 8U,  /**< EVSIM0 reset control */
-    kEVSIM1_RST_SHIFT_RSTn      = 65536 | 9U,  /**< EVSIM1 reset control */
-    kUTICK_RST_SHIFT_RSTn       = 65536 | 10U, /**< Micro-tick timer reset control */
-    kFC0_RST_SHIFT_RSTn         = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
-    kFC1_RST_SHIFT_RSTn         = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
-    kFC2_RST_SHIFT_RSTn         = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
-    kFC3_RST_SHIFT_RSTn         = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
-    kFC4_RST_SHIFT_RSTn         = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
-    kFC5_RST_SHIFT_RSTn         = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
-    kFC6_RST_SHIFT_RSTn         = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
-    kFC7_RST_SHIFT_RSTn         = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
-    kFC8_RST_SHIFT_RSTn         = 65536 | 19U, /**< Flexcomm Interface 8 reset control */
-    kFC9_RST_SHIFT_RSTn         = 65536 | 20U, /**< MICFIL reset control */
-    kMICFIL_RST_SHIFT_RSTn      = 65536 | 21U, /**< Flexcomm Interface 7 reset control */
-    kCTIMER2_RST_SHIFT_RSTn     = 65536 | 22U, /**< CTimer 2 reset control */
-    kUSB0_RAM_RST_SHIFT_RSTn    = 65536 | 23U, /**< USB0 RAM reset control */
-    kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */
-    kUSB0_FS_RST_SHIFT_RSTn     = 65536 | 25U, /**< USB0-FS reset control */
-    kCTIMER0_RST_SHIFT_RSTn     = 65536 | 26U, /**< CTimer 0 reset control */
-    kCTIMER1_RST_SHIFT_RSTn     = 65536 | 27U, /**< CTimer 1 reset control */
-    kSMART_DMA_RST_SHIFT_RSTn   = 65536 | 31U, /**< SmartDMA reset control */
-
-    kDMA1_RST_SHIFT_RSTn       = 131072 | 1U,  /**< DMA1 reset control */
-    kENET_RST_SHIFT_RSTn       = 131072 | 2U,  /**< Ethernet reset control */
-    kUSDHC_RST_SHIFT_RSTn      = 131072 | 3U,  /**< uSDHC reset control */
-    kFLEXIO_RST_SHIFT_RSTn     = 131072 | 4U,  /**< FLEXIO reset control */
-    kSAI0_RST_SHIFT_RSTn       = 131072 | 5U,  /**< SAI0 reset control */
-    kSAI1_RST_SHIFT_RSTn       = 131072 | 6U,  /**< SAI1 reset control */
-    kTRO_RST_SHIFT_RSTn        = 131072 | 7U,  /**< TRO reset control */
-    kFREQME_RST_SHIFT_RSTn     = 131072 | 8U,  /**< FREQME reset control */
-    kTRNG_RST_SHIFT_RSTn       = 131072 | 13U, /**< TRNG reset control */
-    kFLEXCAN0_RST_SHIFT_RSTn   = 131072 | 14U, /**< Flexcan0 reset control */
-    kFLEXCAN1_RST_SHIFT_RSTn   = 131072 | 15U, /**< Flexcan1 reset control */
-    kUSB_HS_RST_SHIFT_RSTn     = 131072 | 16U, /**< USB HS reset control */
-    kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */
-    kPOWERQUAD_RST_SHIFT_RSTn  = 131072 | 19U, /**< PowerQuad reset control */
-    kPLU_RST_SHIFT_RSTn        = 131072 | 20U, /**< PLU reset control */
-    kCTIMER3_RST_SHIFT_RSTn    = 131072 | 21U, /**< CTimer 3 reset control */
-    kCTIMER4_RST_SHIFT_RSTn    = 131072 | 22U, /**< CTimer 4 reset control */
-    kPUF_RST_SHIFT_RSTn        = 131072 | 23U, /**< PUF reset control */
-    kPKC_RST_SHIFT_RSTn        = 131072 | 24U, /**< PKC reset control */
-    kSM3_RST_SHIFT_RSTn        = 131072 | 30U, /**< SM3 reset control */
-
-    kI3C0_RST_SHIFT_RSTn         = 196608 | 0U,  /**< I3C0 reset control */
-    kI3C1_RST_SHIFT_RSTn         = 196608 | 1U,  /**< I3C1 reset control */
-    kSINC_RST_SHIFT_RSTn         = 196608 | 2U,  /**< SINC reset control */
-    kCOOLFLUX_RST_SHIFT_RSTn     = 196608 | 3U,  /**< CoolFlux reset control */
-    kENC0_RST_SHIFT_RSTn         = 196608 | 4U,  /**< ENC0 reset control */
-    kENC1_RST_SHIFT_RSTn         = 196608 | 5U,  /**< ENC1 reset control */
-    kPWM0_RST_SHIFT_RSTn         = 196608 | 6U,  /**< PWM0 reset control */
-    kPWM1_RST_SHIFT_RSTn         = 196608 | 7U,  /**< PWM1 reset control */
-    kAOI0_RST_SHIFT_RSTn         = 196608 | 8U,  /**< AOI0 reset control */
-    kDAC1_RST_SHIFT_RSTn         = 196608 | 11U, /**< DAC1 reset control */
-    kDAC2_RST_SHIFT_RSTn         = 196608 | 12U, /**< DAC2 reset control */
-    kOPAMP0_RST_SHIFT_RSTn       = 196608 | 13U, /**< OPAMP0 reset control */
-    kOPAMP1_RST_SHIFT_RSTn       = 196608 | 14U, /**< OPAMP1 reset control */
-    kOPAMP2_RST_SHIFT_RSTn       = 196608 | 15U, /**< OPAMP2 reset control */
-    kCMP2_RST_SHIFT_RSTn         = 196608 | 18U, /**< CMP2 reset control */
-    kVREF_RST_SHIFT_RSTn         = 196608 | 19U, /**< VREF reset control */
-    kCOOLFLUX_APB_RST_SHIFT_RSTn = 196608 | 20U, /**< CoolFlux APB reset control */
-    kNEUTRON_RST_SHIFT_RSTn      = 196608 | 21U, /**< Neutron mini reset control */
-    kTSI_RST_SHIFT_RSTn          = 196608 | 22U, /**< TSI reset control */
-    kEWM_RST_SHIFT_RSTn          = 196608 | 23U, /**< EWM reset control */
-    kEIM_RST_SHIFT_RSTn          = 196608 | 24U, /**< EIM reset control */
-    kSEMA42_RST_SHIFT_RSTn       = 196608 | 27U, /**< Semaphore reset control */
-} SYSCON_RSTn_t;
-
-/** Array initializers with peripheral reset bits **/
-#define ADC_RSTS                                   \
-    {                                              \
-        kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \
-    } /* Reset bits for ADC peripheral */
-#define CRC_RSTS            \
-    {                       \
-        kCRC_RST_SHIFT_RSTn \
-    } /* Reset bits for CRC peripheral */
-#define CTIMER_RSTS                                                                                         \
-    {                                                                                                       \
-        kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
-            kCTIMER4_RST_SHIFT_RSTn                                                                         \
-    } /* Reset bits for CTIMER peripheral */
-#define DMA_RSTS_N                                 \
-    {                                              \
-        kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
-    } /* Reset bits for DMA peripheral */
-
-#define LP_FLEXCOMM_RSTS                                                                                            \
-    {                                                                                                               \
-        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn,    \
-            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \
-    } /* Reset bits for FLEXCOMM peripheral */
-#define GPIO_RSTS_N                                                                                 \
-    {                                                                                               \
-        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
-            kGPIO4_RST_SHIFT_RSTn                                                                   \
-    } /* Reset bits for GPIO peripheral */
-#define INPUTMUX_RSTS       \
-    {                       \
-        kMUX_RST_SHIFT_RSTn \
-    } /* Reset bits for INPUTMUX peripheral */
-#define FLASH_RSTS          \
-    {                       \
-        kFMC_RST_SHIFT_RSTn \
-    } /* Reset bits for Flash peripheral */
-#define MRT_RSTS            \
-    {                       \
-        kMRT_RST_SHIFT_RSTn \
-    } /* Reset bits for MRT peripheral */
-#define PINT_RSTS            \
-    {                        \
-        kPINT_RST_SHIFT_RSTn \
-    } /* Reset bits for PINT peripheral */
-#define TRNG_RSTS            \
-    {                        \
-        kTRNG_RST_SHIFT_RSTn \
-    } /* Reset bits for TRNG peripheral */
-#define SCT_RSTS            \
-    {                       \
-        kSCT_RST_SHIFT_RSTn \
-    } /* Reset bits for SCT peripheral */
-#define UTICK_RSTS            \
-    {                         \
-        kUTICK_RST_SHIFT_RSTn \
-    } /* Reset bits for UTICK peripheral */
-#define PLU_RSTS_N          \
-    {                       \
-        kPLU_RST_SHIFT_RSTn \
-    } /* Reset bits for PLU peripheral */
-#define OSTIMER_RSTS            \
-    {                           \
-        kOSTIMER_RST_SHIFT_RSTn \
-    } /* Reset bits for OSTIMER peripheral */
-#define POWERQUAD_RSTS            \
-    {                             \
-        kPOWERQUAD_RST_SHIFT_RSTn \
-    } /* Reset bits for Powerquad peripheral */
-#define I3C_RSTS                                   \
-    {                                              \
-        kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \
-    } /* Reset bits for I3C peripheral */
-typedef SYSCON_RSTn_t reset_ip_name_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Assert reset to peripheral.
- *
- * Asserts reset signal to specified peripheral module.
- *
- * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
-
-/*!
- * @brief Clear reset to peripheral.
- *
- * Clears reset signal to specified peripheral module, allows it to operate.
- *
- * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
-
-/*!
- * @brief Reset peripheral module.
- *
- * Reset peripheral module.
- *
- * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_PeripheralReset(reset_ip_name_t peripheral);
-
-/*!
- * @brief Release peripheral module.
- *
- * Release peripheral module.
- *
- * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
-{
-    RESET_ClearPeripheralReset(peripheral);
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @} */
-
-#endif /* _FSL_RESET_H_ */

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/frdm-mcxn947-xpresso-baremetal-builtin LinkServer Debug.launch

@@ -1,106 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
-    <stringAttribute key=".gdbinit" value=""/>
-    <booleanAttribute key="attach" value="false"/>
-    <booleanAttribute key="boot.config.enable" value="false"/>
-    <stringAttribute key="boot.configuration.control" value=""/>
-    <stringAttribute key="bootrom.stall" value="0x50000040"/>
-    <stringAttribute key="com.crt.ctrlcenter.OFSemuDetails" value="LinkServer"/>
-    <booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
-    <stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
-    <booleanAttribute key="com.crt.ctrlcenter.mainBreakIsHardware" value="true"/>
-    <booleanAttribute key="com.crt.ctrlcenter.saveState" value="true"/>
-    <stringAttribute key="com.crt.ctrlcenter.serialNumber" value="LinkServerNXP SemiconductorsMCU-LINK FRDM-MCXN947 (r0E7) CMSIS-DAP V3.128NNF4LOKTTTMAC"/>
-    <mapAttribute key="com.crt.ctrlcenter.symbolsGroupSettings"/>
-    <intAttribute key="com.crt.ctrlcenter.version" value="6"/>
-    <stringAttribute key="com.nxp.mcuxpresso.flash.base.address" value="0x0"/>
-    <booleanAttribute key="com.nxp.mcuxpresso.flash.clear.console" value="true"/>
-    <booleanAttribute key="com.nxp.mcuxpresso.flash.confirm" value="false"/>
-    <stringAttribute key="com.nxp.mcuxpresso.flash.erase.algorithm" value="Mass erase"/>
-    <stringAttribute key="com.nxp.mcuxpresso.flash.executable" value="axf"/>
-    <stringAttribute key="com.nxp.mcuxpresso.flash.program.action" value="Program"/>
-    <booleanAttribute key="com.nxp.mcuxpresso.flash.reset.target" value="true"/>
-    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.manufacturer" value="NXP Semiconductors"/>
-    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.name" value="MCU-LINK FRDM-MCXN947 (r0E7) CMSIS-DAP V3.128"/>
-    <stringAttribute key="com.nxp.mcuxpresso.ide.probe.type" value="LinkServer"/>
-    <stringAttribute key="debug.level" value="2"/>
-    <stringAttribute key="emu.speed" value=""/>
-    <stringAttribute key="flash.driver.reset" value=""/>
-    <stringAttribute key="gdbserver.host" value="localhost"/>
-    <stringAttribute key="gdbserver.port" value="10989"/>
-    <booleanAttribute key="gdbserver.start" value="true"/>
-    <booleanAttribute key="internal.attach.slave" value="false"/>
-    <booleanAttribute key="internal.cache" value="false"/>
-    <stringAttribute key="internal.connect.script" value=""/>
-    <stringAttribute key="internal.core.index" value=""/>
-    <booleanAttribute key="internal.has_swo" value="true"/>
-    <booleanAttribute key="internal.multi.swd" value="true"/>
-    <stringAttribute key="internal.prelaunch.command" value=""/>
-    <stringAttribute key="internal.reset.script" value=""/>
-    <stringAttribute key="internal.resethandling" value=""/>
-    <stringAttribute key="internal.semihost" value="On"/>
-    <stringAttribute key="internal.wirespeed" value=""/>
-    <stringAttribute key="internal.wiretype" value="SWD"/>
-    <stringAttribute key="isp.control" value="xxxx"/>
-    <stringAttribute key="launch.config.handler" value="com.crt.ctrlcenter.launch.CRTLaunchConfigHandler"/>
-    <booleanAttribute key="mem.access" value="false"/>
-    <stringAttribute key="misc.options" value=" --romstalldelay 600"/>
-    <stringAttribute key="ondisconnect" value="cont"/>
-    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="0"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set non-stop on&#10;set pagination off&#10;set mi-async&#10;set remotetimeout 60000&#10;##target_extended_remote##&#10;set mem inaccessible-by-default ${mem.access}&#10;mon ondisconnect ${ondisconnect}&#10;set arm force-mode thumb&#10;${load}"/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
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-    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="10989"/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value="${run}"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
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-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
-    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
-    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.EXTERNAL_CONSOLE" value="false"/>
-    <stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=""/>
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-    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
-    <stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
-    <stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
-    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
-    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
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-    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="frdm-mcxn947-xpresso-baremetal-builtin"/>
-    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.1734776104"/>
-    <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
-    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
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-    </listAttribute>
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-        <listEntry value="4"/>
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-    <mapAttribute key="org.eclipse.debug.core.preferred_launchers">
-        <mapEntry key="[debug]" value="com.nxp.mcuxpresso.core.debug.support.linkserver.launch.LinkServerGdbLaunch"/>
-    </mapAttribute>
-    <stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
-    <stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;sourceLookupDirector&gt;&#10;    &lt;sourceContainers duplicates=&quot;false&quot;&gt;&#10;        &lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#10;&amp;lt;default/&amp;gt;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#10;        &lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#10;&amp;lt;mapping backend_enabled=&amp;quot;true&amp;quot; name=&amp;quot;Found Mappings&amp;quot;&amp;gt;&amp;#10;    &amp;lt;mapEntry memento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#10;&amp;amp;lt;mapEntry backendPath=&amp;amp;quot;/root/Documents/MCUXpresso_11.8.1_1197/workspace/frdmmcxn947_enet_txrx_rxpoll/Debug/src/&amp;amp;quot; localPath=&amp;amp;quot;/home/scaprile/work/cesanta/mongoose/src/&amp;amp;quot;/&amp;amp;gt;&amp;amp;#10;&amp;quot;/&amp;gt;&amp;#10;&amp;lt;/mapping&amp;gt;&amp;#10;&quot; typeId=&quot;org.eclipse.cdt.debug.core.containerType.mapping&quot;/&gt;&#10;    &lt;/sourceContainers&gt;&#10;&lt;/sourceLookupDirector&gt;&#10;"/>
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-    <stringAttribute key="process_factory_id" value="com.nxp.mcuxpresso.core.debug.override.MCXProcessFactory"/>
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-    <booleanAttribute key="redlink.enable.rangestepping" value="true"/>
-    <stringAttribute key="run" value="cont"/>
-    <booleanAttribute key="vector.catch" value="false"/>
-</launchConfiguration>

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/hal.c

@@ -1,187 +0,0 @@
-// Copyright (c) 2024 Cesanta Software Limited
-// All rights reserved
-
-#include "hal.h"
-
-static volatile uint64_t s_ticks;  // Milliseconds since boot
-void SysTick_Handler(void) {       // SyStick IRQ handler, triggered every 1ms
-  s_ticks++;
-}
-
-#if 0
-bool mg_random(void *buf, size_t len) {  // Use on-board RNG
-  for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
-    uint32_t r = rng_read();
-    memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
-  }
-  return true;
-}
-#endif
-
-uint64_t mg_millis(void) {  // Let Mongoose use our uptime function
-  return s_ticks;           // Return number of milliseconds since boot
-}
-
-void hal_init(void) {
-  clock_init();                            // Set system clock to SYS_FREQUENCY
-  SystemCoreClock = SYS_FREQUENCY;         // Update SystemCoreClock global var
-  SysTick_Config(SystemCoreClock / 1000);  // Sys tick every 1ms
-  // rng_init();  // TRNG is part of ELS and there is no info on that
-
-  uart_init(UART_DEBUG, 115200);  // Initialise UART
-  gpio_output(LED1);              // Initialise LED1
-  gpio_write(LED1, 1);
-  gpio_output(LED2);  // Initialise LED2
-  gpio_write(LED2, 1);
-  gpio_output(LED3);  // Initialise LED3
-  gpio_write(LED3, 1);
-  ethernet_init();  // Initialise Ethernet pins
-}
-
-#if defined(__ARMCC_VERSION)
-// Keil specific - implement IO printf redirection
-int fputc(int c, FILE *stream) {
-  if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c);
-  return c;
-}
-#elif defined(__GNUC__)
-// ARM GCC specific. ARM GCC is shipped with Newlib C library.
-// Implement newlib syscalls:
-//      _sbrk() for malloc
-//      _write() for printf redirection
-//      the rest are just stubs
-#include <sys/stat.h>  // For _fstat()
-
-#if !defined(__MCUXPRESSO)
-uint32_t SystemCoreClock;
-// evaluate your use of Secure/non-Secure and modify accordingly
-void SystemInit(void) {  // Called automatically by startup code
-  SCB->CPACR |=
-#if 0
-      (3UL << 0 * 2) | (3UL << 1 * 2) |   // Enable PowerQuad (CPO/CP1)
-#endif
-      (3UL << 10 * 2) | (3UL << 11 * 2);  // Enable FPU
-  __DSB();
-  __ISB();
-  SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;  // enable LPCAC
-// Read TRM 36.1 and decide whether you really want to enable aGDET and dGDET
-#if 1
-  // Disable aGDET and dGDET
-  ITRC0->OUT_SEL[4][0] =
-      (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) |
-      (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
-  ITRC0->OUT_SEL[4][1] =
-      (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) |
-      (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
-  SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
-  SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
-  SPC0->GLITCH_DETECT_SC = 0x3C;
-  SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
-  ITRC0->OUT_SEL[4][0] =
-      (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) |
-      (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
-  ITRC0->OUT_SEL[4][1] =
-      (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) |
-      (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
-  GDET0->GDET_ENABLE1 = 0;
-  GDET1->GDET_ENABLE1 = 0;
-#endif
-}
-#endif
-
-int _fstat(int fd, struct stat *st) {
-  (void) fd, (void) st;
-  return -1;
-}
-
-#if !defined(__MCUXPRESSO)
-extern unsigned char _end[];  // End of data section, start of heap. See link.ld
-static unsigned char *s_current_heap_end = _end;
-
-size_t hal_ram_used(void) {
-  return (size_t) (s_current_heap_end - _end);
-}
-
-size_t hal_ram_free(void) {
-  unsigned char endofstack;
-  return (size_t) (&endofstack - s_current_heap_end);
-}
-
-void *_sbrk(int incr) {
-  unsigned char *prev_heap;
-  unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
-  prev_heap = s_current_heap_end;
-  // Check how much space we  got from the heap end to the stack end
-  if (s_current_heap_end + incr > heap_end) return (void *) -1;
-  s_current_heap_end += incr;
-  return prev_heap;
-}
-#endif
-
-int _open(const char *path) {
-  (void) path;
-  return -1;
-}
-
-int _close(int fd) {
-  (void) fd;
-  return -1;
-}
-
-int _isatty(int fd) {
-  (void) fd;
-  return 1;
-}
-
-int _lseek(int fd, int ptr, int dir) {
-  (void) fd, (void) ptr, (void) dir;
-  return 0;
-}
-
-void _exit(int status) {
-  (void) status;
-  for (;;) asm volatile("BKPT #0");
-}
-
-void _kill(int pid, int sig) {
-  (void) pid, (void) sig;
-}
-
-int _getpid(void) {
-  return -1;
-}
-
-int _write(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
-  return -1;
-}
-
-int _read(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  return -1;
-}
-
-int _link(const char *a, const char *b) {
-  (void) a, (void) b;
-  return -1;
-}
-
-int _unlink(const char *a) {
-  (void) a;
-  return -1;
-}
-
-int _stat(const char *path, struct stat *st) {
-  (void) path, (void) st;
-  return -1;
-}
-
-int mkdir(const char *path, mode_t mode) {
-  (void) path, (void) mode;
-  return -1;
-}
-
-void _init(void) {
-}
-#endif  // __GNUC__

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/hal.h

@@ -1,223 +0,0 @@
-// Copyright (c) 2023 Cesanta Software Limited
-// All rights reserved
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#define LED1 PIN(0, 10)
-#define LED2 PIN(0, 27)
-#define LED3 PIN(1, 2)
-
-#ifndef UART_DEBUG
-#define UART_DEBUG LPUART4
-#endif
-
-#include "MCXN947_cm33_core0.h"
-
-#define BIT(x) (1UL << (x))
-#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
-#define PIN(bank, num) ((bank << 8) | (num))
-#define PINNO(pin) (pin & 255)
-#define PINBANK(pin) (pin >> 8)
-
-void hal_init(void);
-size_t hal_ram_free(void);
-size_t hal_ram_used(void);
-
-static inline void spin(volatile uint32_t count) {
-  while (count--) (void) 0;
-}
-
-#define SYS_FREQUENCY 150000000UL
-
-enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
-enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
-enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH };
-enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
-static inline GPIO_Type *gpio_bank(uint16_t pin) {
-  static GPIO_Type *const g[] = GPIO_BASE_PTRS;
-  return g[PINBANK(pin)];
-}
-
-static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
-                             uint8_t speed, uint8_t pull, uint8_t af) {
-  static PORT_Type *const p[] = PORT_BASE_PTRS;
-  PORT_Type *port = p[PINBANK(pin)];
-  GPIO_Type *gpio = gpio_bank(pin);
-  uint32_t mask = (uint32_t) BIT(PINNO(pin));
-  bool dopull = pull > 0;
-  if (dopull) --pull;
-  if (gpio != GPIO5) {
-    SYSCON->AHBCLKCTRL0 |=
-        (1 << (SYSCON_AHBCLKCTRL0_GPIO0_SHIFT + PINBANK(pin))) |
-        (1 << (SYSCON_AHBCLKCTRL0_PORT0_SHIFT + PINBANK(pin)));
-  };
-  port->PCR[PINNO(pin)] = PORT_PCR_IBE(1) | PORT_PCR_MUX(af) | PORT_PCR_DSE(1) |
-                          PORT_PCR_ODE(type) |
-                          PORT_PCR_SRE(speed != GPIO_SPEED_HIGH) |
-                          PORT_PCR_PE(dopull) | PORT_PCR_PS(pull);
-  gpio->ICR[PINNO(pin)] = GPIO_ICR_ISF_MASK;
-  if (mode == GPIO_MODE_INPUT) {
-    gpio->PDDR &= ~mask;
-  } else {
-    gpio->PDDR |= mask;
-  }
-}
-
-static inline void gpio_input(uint16_t pin) {
-  gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
-            GPIO_PULL_NONE, 0);
-}
-static inline void gpio_output(uint16_t pin) {
-  gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
-            GPIO_PULL_NONE, 0);
-}
-
-static inline bool gpio_read(uint16_t pin) {
-  GPIO_Type *gpio = gpio_bank(pin);
-  return gpio->PDR[PINNO(pin)];
-}
-
-static inline void gpio_write(uint16_t pin, bool value) {
-  GPIO_Type *gpio = gpio_bank(pin);
-  if (value) {
-    gpio->PDR[PINNO(pin)] = 1;
-  } else {
-    gpio->PDR[PINNO(pin)] = 0;
-  }
-}
-
-static inline void gpio_toggle(uint16_t pin) {
-  GPIO_Type *gpio = gpio_bank(pin);
-  uint32_t mask = (uint32_t) BIT(PINNO(pin));
-  gpio->PTOR = mask;
-}
-
-// MCU-Link UART (P1_9/8; FC4_P1/0)
-// Arduino J1_2/4 UART (P4_3/2; FC2_P3/2)
-// 33.3.23 LP_FLEXCOMM clocking
-// 66.2.4 LP_FLEXCOMM init
-// 66.5 LPUART
-static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
-  static LP_FLEXCOMM_Type *const f[] = LP_FLEXCOMM_BASE_PTRS;
-  uint8_t af = 2, fc = 0;    // Alternate function, FlexComm instance
-  uint16_t pr = 0, pt = 0;   // pins
-  uint32_t freq = 12000000;  // fro_12_m
-  if (uart == LPUART2) fc = 2, pt = PIN(4, 3), pr = PIN(4, 2);
-  if (uart == LPUART4) fc = 4, pt = PIN(1, 9), pr = PIN(1, 8);
-
-  SYSCON->AHBCLKCTRL1 |= (1 << (SYSCON_AHBCLKCTRL1_FC0_SHIFT + fc));
-  SYSCON->PRESETCTRL1 |= (1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
-  SYSCON->PRESETCTRL1 &= ~(1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
-  SYSCON->FCCLKSEL[fc] = SYSCON_FCCLKSEL_SEL(2);  // clock from FRO_12M / 1
-  SYSCON->FLEXCOMMCLKDIV[fc] = SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(0);
-  LP_FLEXCOMM_Type *flexcomm = f[fc];
-  flexcomm->PSELID = LP_FLEXCOMM_PSELID_PERSEL(1);  // configure as UART
-  gpio_init(pt, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
-            GPIO_PULL_UP, af);
-  gpio_init(pr, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
-            GPIO_PULL_UP, af);
-
-  uart->GLOBAL |= LPUART_GLOBAL_RST_MASK;  // reset, CTRL = 0, defaults
-  uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
-  // use a weird oversample ratio of 26x to fit specs, standard 16x won't do
-  CLRSET(uart->BAUD,
-         LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
-         LPUART_BAUD_OSR(26 - 1) | LPUART_BAUD_SBR(freq / (26 * baud)));
-  CLRSET(uart->CTRL,
-         LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
-             LPUART_CTRL_IDLECFG_MASK,
-         LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
-             LPUART_BAUD_SBNS(0));  // no parity, idle 2 chars after 1 stop bit
-  uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
-}
-
-static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
-  uart->DATA = byte;
-  while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
-}
-static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
-  while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
-}
-
-static inline void rng_init(void) {
-}
-static inline uint32_t rng_read(void) {
-  return 42;
-}
-
-// - PHY and MAC clocked via a 50MHz oscillator, P1_4 (ENET0_TXCLK)
-// - 33.3.30 ENET clocking
-// - SMI clocked from AHB module clock (CSR)
-// - PHY RST connected to P5_8
-// - PHY RXD0,1,DV = 1 on RST enable autonegotiation, no hw pull-ups
-static inline void ethernet_init(void) {
-  // '0' in clk_rmii, set for RMII mode
-  SYSCON->ENETRMIICLKSEL = SYSCON_ENETRMIICLKSEL_SEL(0);
-  SYSCON->ENETRMIICLKDIV = SYSCON_ENETRMIICLKDIV_DIV(0);
-  SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_ENET_MASK;        // enable bus clk
-  SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK;    // reset MAC
-  SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK;  // then set RMII
-  SYSCON0->ENET_PHY_INTF_SEL |= SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK;
-  gpio_init(PIN(5, 8), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
-            GPIO_PULL_NONE, 0);  // set P5_8 as GPIO (PHY \RST)
-  gpio_write(PIN(5, 8), 0);      // reset PHY
-  gpio_init(PIN(1, 4), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 9);  // set P1_4 as ENET0_TXCLK
-  gpio_init(PIN(1, 5), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 9);  // set P1_5 as ENET0_TXEN
-  gpio_init(PIN(1, 6), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 9);  // set P1_6 as ENET0_TXD0
-  gpio_init(PIN(1, 7), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 9);  // set P1_7 as ENET0_TXD1
-  gpio_init(PIN(1, 13), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_UP, 9);  // set P1_13 as ENET0_RXDV
-  gpio_init(PIN(1, 14), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_UP, 9);  // set P1_14 as ENET0_RXD0
-  gpio_init(PIN(1, 15), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_UP, 9);  // set P1_15 as ENET0_RXD1
-  gpio_init(PIN(1, 20), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 9);  // set P1_20 as ENET0_MDC
-  gpio_init(PIN(1, 21), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 9);   // set P1_21 as ENET0_MDIO
-  spin(10000);                    // keep PHY RST low for a while
-  gpio_write(PIN(5, 8), 1);       // deassert RST
-  NVIC_EnableIRQ(ETHERNET_IRQn);  // Setup Ethernet IRQ handler
-}
-
-#include "fsl_clock.h"
-#include "fsl_spc.h"
-
-// 33.2 Figure 127 SCG main clock
-static inline void clock_init(void) {
-  SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_SCG_MASK;    // enable SCG clk
-  CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(2));  // clock main_clock
-  spc_active_mode_dcdc_option_t dcdc = {
-      .DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
-      .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength};
-  SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdc);  // Set DCDC to 1.2 V
-  spc_active_mode_core_ldo_option_t ldo = {
-      .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
-      .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength};
-  SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo);  // Set LDO_CORE to 1.2 V
-  CLRSET(FMU0->FCTRL, FMU_FCTRL_RWSC_MASK, FMU_FCTRL_RWSC(3));  // Set Flash WS
-  spc_sram_voltage_config_t sram = {.operateVoltage = kSPC_sramOperateAt1P2V,
-                                    .requestVoltageUpdate = true};
-  SPC_SetSRAMOperateVoltage(SPC0, &sram);  // Set SRAM timing for 1.2V
-  CLOCK_SetupFROHFClocking(48000000U);     // Enable FRO HF
-  const pll_setup_t pll0 = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) |
-                                       SCG_APLLCTRL_SELI(27U) |
-                                       SCG_APLLCTRL_SELP(13U),
-                            .pllndiv = SCG_APLLNDIV_NDIV(8U),
-                            .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-                            .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-                            .pllRate = 150000000U};
-  CLOCK_SetPLL0Freq(&pll0);                              // Setup PLL0 (APLL),
-  CLOCK_SetPll0MonitorMode(0);                           // disable monitor mode
-  CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(5));  // clock main_clock
-  SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0);           // /1
-}

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/main.c

@@ -1,62 +0,0 @@
-/*
- * Copyright 2016-2024 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file    MCXN947_Project.c
- * @brief   Application entry point.
- */
-#include <stdio.h>
-#include "board.h"
-#include "peripherals.h"
-#include "pin_mux.h"
-#include "clock_config.h"
-#include "MCXN947_cm33_core0.h"
-#include "fsl_debug_console.h"
-/* TODO: insert other include files here. */
-#include "hal.h"
-#include "mongoose.h"
-#include "net.h"
-
-/* TODO: insert other definitions and declarations here. */
-#define BLINK_PERIOD_MS 1000
-
-static void timer_fn(void *arg) {
-  gpio_toggle(LED1);  // Blink LED
-  (void) arg;         // Unused
-}
-
-/*
- * @brief   Application entry point.
- */
-int main(void) {
-
-    /* Init board hardware. */
-    BOARD_InitBootPins();
-    BOARD_InitBootClocks();
-    BOARD_InitBootPeripherals();
-#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL
-    /* Init FSL debug console. */
-    BOARD_InitDebugConsole();
-#endif
-
-    struct mg_mgr mgr;  // Mongoose event manager
-
-    hal_init();  // Cross-platform hardware init
-
-    mg_mgr_init(&mgr);        // Initialise it
-    mg_log_set(MG_LL_DEBUG);  // Set log level to debug
-    mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mgr);
-
-    MG_INFO(("Initialising application..."));
-    web_init(&mgr);
-
-    for (;;) {
-      mg_mgr_poll(&mgr, 0);
-    }
-
-    return 0;
-}

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/mongoose_config.h

@@ -1,25 +0,0 @@
-#pragma once
-
-// See https://mongoose.ws/documentation/#build-options
-#define MG_ARCH MG_ARCH_NEWLIB
-
-#define MG_ENABLE_TCPIP 1
-#define MG_ENABLE_DRIVER_MCXN 1
-#define MG_ENABLE_CUSTOM_MILLIS 1
-//#define MG_ENABLE_CUSTOM_RANDOM 1
-#define MG_ENABLE_PACKED_FS 1 
-
-// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
-// By default, those are set to zero, meaning that DHCP is used
-//
-// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
-// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
-// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
-
-// Set custom MAC address. By default, it is randomly generated
-// Using a build-time constant:
-// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0)
-//
-// Using custom function:
-// extern void my_function(unsigned char *mac);
-// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/net.c

@@ -1 +0,0 @@
-../../../../examples/device-dashboard/net.c

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/net.h

@@ -1 +0,0 @@
-../../../../examples/device-dashboard/net.h

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/source/packed_fs.c

@@ -1 +0,0 @@
-../../../../examples/device-dashboard/packed_fs.c

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/startup/boot_multicore_slave.c

@@ -1,48 +0,0 @@
-//*****************************************************************************
-// boot_multicore_slave.c
-//
-// Provides functions to allow booting of secondary core in multicore system
-//
-//*****************************************************************************
-//
-// Copyright 2016-2022 NXP
-// All rights reserved.
-//
-// SPDX-License-Identifier: BSD-3-Clause
-//*****************************************************************************
-
-#if defined(__MULTICORE_MASTER)
-
-#include <stdint.h>
-
-#define SYSCON_BASE ((uint32_t)0x50000000)
-
-#define CPBOOT  (((volatile uint32_t *)(SYSCON_BASE + 0x804)))
-#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))
-
-#define CPUCTRL_KEY     ((uint32_t)(0x0000C0C4 << 16))
-#define CORE1_CLK_ENA   (1 << 3)
-#define CORE1_RESET_ENA (1 << 5)
-
-extern uint8_t __core_m33slave_START__;
-
-void boot_multicore_slave(void)
-{
-    volatile uint32_t *u32REG, u32Val;
-
-    unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__;
-
-    // Set CPU1 boot address in SYSCON->CPBoot
-    *CPBOOT = (uint32_t)slavevectortable_ptr;
-
-    // Read SYSCON->CPUCTRL and set key value in bits 31:16
-    u32REG = (uint32_t *)CPUCTRL;
-    u32Val = *u32REG | CPUCTRL_KEY;
-
-    // Enable CPU1 clock and reset in SYSCON->CPUCTRL
-    *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA;
-
-    // Clear CPU1 reset in SYSCON->CPUCTRL
-    *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA);
-}
-#endif // defined (__MULTICORE_MASTER)

examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/startup/boot_multicore_slave.h

@@ -1,26 +0,0 @@
-//*****************************************************************************
-// boot_multicore_slave.h
-//
-// Header for functions used for booting of secondary core in multicore system
-//*****************************************************************************
-//
-// Copyright 2016-2022 NXP
-// All rights reserved.
-//
-// SPDX-License-Identifier: BSD-3-Clause
-//*****************************************************************************
-
-#ifndef BOOT_MULTICORE_SLAVE_H_
-#define BOOT_MULTICORE_SLAVE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void boot_multicore_slave(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* BOOT_MULTICORE_SLAVE_H_ */

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/.cproject

@@ -1,735 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.crt.advproject.config.exe.debug.1992514917">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1992514917" moduleId="org.eclipse.cdt.core.settings" name="Debug">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.1992514917" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; # arm-none-eabi-objcopy -v -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
-					<folderInfo id="com.crt.advproject.config.exe.debug.1992514917." name="/" resourcePath="">
-						<toolChain id="com.crt.advproject.toolchain.exe.debug.806652998" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
-							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1969731363" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
-							<builder buildPath="${workspace_loc:/frdm-mcxn947-xpresso-freertos-builtin}/Debug" id="com.crt.advproject.builder.exe.debug.700225415" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
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-									<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
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-								<option id="com.crt.advproject.link.gcc.lto.optmization.level.823722371" name="Link-time optimization level" superClass="com.crt.advproject.link.gcc.lto.optmization.level"/>
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-								<option id="com.crt.advproject.link.crpenable.576300410" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.crpenable"/>
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-								<option id="com.crt.advproject.link.ecrp.202532127" name="Enhanced CRP" superClass="com.crt.advproject.link.ecrp"/>
-								<option id="com.crt.advproject.link.gcc.hdrlib.1358111247" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.nohost" valueType="enumerated"/>
-								<option id="com.crt.advproject.link.gcc.nanofloat.1098707676" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat"/>
-								<option id="com.crt.advproject.link.gcc.nanofloat.scanf.689148154" name="Enable scanf float " superClass="com.crt.advproject.link.gcc.nanofloat.scanf"/>
-								<option id="com.crt.advproject.link.toram.564447782" name="Link application to RAM" superClass="com.crt.advproject.link.toram"/>
-								<option id="com.crt.advproject.link.stackOffset.1508296833" name="Stack offset" superClass="com.crt.advproject.link.stackOffset"/>
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-								<option id="com.crt.advproject.link.gcc.multicore.empty.1355922678" name="No Multicore options for this project" superClass="com.crt.advproject.link.gcc.multicore.empty"/>
-								<option id="com.crt.advproject.link.config.682740228" name="Obsolete (Config)" superClass="com.crt.advproject.link.config"/>
-								<option id="com.crt.advproject.link.store.196987339" name="Obsolete (Store)" superClass="com.crt.advproject.link.store"/>
-								<option id="com.crt.advproject.link.securestate.977867921" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate"/>
-								<option id="com.crt.advproject.link.sgstubs.placement.536370498" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement"/>
-								<option id="com.crt.advproject.link.sgstubenable.261175817" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable"/>
-								<option id="com.crt.advproject.link.nonsecureobject.1065261932" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject"/>
-								<option id="com.crt.advproject.link.inimplib.321692015" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
-								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.159241052" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
-									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-								</inputType>
-							</tool>
-							<tool id="com.crt.advproject.tool.debug.release.990517564" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.release">
-								<option id="com.crt.advproject.miscellaneous.end_of_heap.1264230676" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
-								<option id="com.crt.advproject.miscellaneous.pvHeapStart.1814555656" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart"/>
-								<option id="com.crt.advproject.miscellaneous.pvHeapLimit.129716228" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit"/>
-								<option id="com.crt.advproject.debugger.security.nonsecureimageenable.60247837" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
-								<option id="com.crt.advproject.debugger.security.nonsecureimage.1109530766" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage"/>
-							</tool>
-						</toolChain>
-					</folderInfo>
-					<sourceEntries>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
-					</sourceEntries>
-				</configuration>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="frdm-mcxn947-xpresso-freertos-builtin.null.722564828" name="frdm-mcxn947-xpresso-freertos-builtin" projectType="com.crt.advproject.projecttype.exe"/>
-	</storageModule>
-	<storageModule moduleId="scannerConfiguration">
-		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1992514917;com.crt.advproject.config.exe.debug.1992514917.;com.crt.advproject.gas.exe.debug.189461350;com.crt.advproject.assembler.input.780499763">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1380682132;com.crt.advproject.config.exe.release.1380682132.;com.crt.advproject.gcc.exe.release.422861583;com.crt.advproject.compiler.input.28986509">
-			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1992514917;com.crt.advproject.config.exe.debug.1992514917.;com.crt.advproject.gcc.exe.debug.550426352;com.crt.advproject.compiler.input.851308779">
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-		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1380682132;com.crt.advproject.config.exe.release.1380682132.;com.crt.advproject.gas.exe.release.520171597;com.crt.advproject.assembler.input.1949242393">
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-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
-		<sdkName>SDK_2.x_FRDM-MCXN947</sdkName>
-		<sdkVersion>2.14.0</sdkVersion>
-		<sdkComponents>middleware.freertos-kernel.MCXN947;platform.drivers.reset.MCXN947;platform.drivers.clock.MCXN947;platform.drivers.lpflexcomm_lpuart.MCXN947;platform.drivers.port.MCXN947;platform.drivers.gpio.MCXN947;platform.drivers.mcx_spc.MCXN947;platform.drivers.lpflexcomm.MCXN947;platform.drivers.common.MCXN947;platform.devices.MCXN947_system.MCXN947;CMSIS_Include_core_cm.MCXN947;platform.devices.MCXN947_CMSIS.MCXN947;utility.debug_console.MCXN947;component.lpuart_adapter.MCXN947;component.serial_manager_uart.MCXN947;component.serial_manager.MCXN947;platform.utilities.assert.MCXN947;component.lists.MCXN947;project_template.frdmmcxn947.MCXN947;middleware.freertos-kernel.template.MCXN947;platform.devices.MCXN947_startup.MCXN947;middleware.freertos-kernel.extension.MCXN947;middleware.freertos-kernel.cm33_non_trustzone.MCXN947;</sdkComponents>
-		<boardId>frdmmcxn947</boardId>
-		<package>MCXN947VDF</package>
-		<core>cm33</core>
-		<coreId>cm33_core0_MCXN947</coreId>
-	</storageModule>
-	<storageModule moduleId="com.crt.config">
-		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;
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-&lt;memory can_program="true" id="Flash" is_ro="true" size="2048" type="Flash"/&gt;
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-&lt;/chip&gt;
-&lt;processor&gt;
-&lt;name gcc_name="cortex-m33"&gt;Cortex-M33&lt;/name&gt;
-&lt;family&gt;Cortex-M&lt;/family&gt;
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-&lt;name gcc_name="cortex-m33-nodsp"&gt;Cortex-M33 (No DSP)&lt;/name&gt;
-&lt;family&gt;Cortex-M&lt;/family&gt;
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-	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
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examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/board.c

@@ -1,245 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include "fsl_common.h"
-#include "fsl_debug_console.h"
-#include "board.h"
-#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
-#include "fsl_lpi2c.h"
-#endif /* SDK_I2C_BASED_COMPONENT_USED */
-#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
-#include "fsl_lpflexcomm.h"
-#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
-#include "fsl_spc.h"
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-/* Initialize debug console. */
-void BOARD_InitDebugConsole(void)
-{
-    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
-    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
-
-    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
-
-    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
-
-#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
-    LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART);
-#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
-
-    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
-}
-
-void BOARD_InitDebugConsole_Core1(void)
-{
-    /* attach 12 MHz clock to FLEXCOMM1 (debug console) */
-    //    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
-
-    RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
-
-    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
-
-    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
-                    uartClkSrcFreq);
-}
-
-#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
-void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
-{
-    lpi2c_master_config_t lpi2cConfig = {0};
-
-    /*
-     * lpi2cConfig.debugEnable = false;
-     * lpi2cConfig.ignoreAck = false;
-     * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
-     * lpi2cConfig.baudRate_Hz = 100000U;
-     * lpi2cConfig.busIdleTimeout_ns = 0;
-     * lpi2cConfig.pinLowTimeout_ns = 0;
-     * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
-     * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
-     */
-    LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
-    LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
-}
-
-status_t BOARD_LPI2C_Send(LPI2C_Type *base,
-                          uint8_t deviceAddress,
-                          uint32_t subAddress,
-                          uint8_t subAddressSize,
-                          uint8_t *txBuff,
-                          uint8_t txBuffSize)
-{
-    lpi2c_master_transfer_t xfer;
-
-    xfer.flags          = kLPI2C_TransferDefaultFlag;
-    xfer.slaveAddress   = deviceAddress;
-    xfer.direction      = kLPI2C_Write;
-    xfer.subaddress     = subAddress;
-    xfer.subaddressSize = subAddressSize;
-    xfer.data           = txBuff;
-    xfer.dataSize       = txBuffSize;
-
-    return LPI2C_MasterTransferBlocking(base, &xfer);
-}
-
-status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
-                             uint8_t deviceAddress,
-                             uint32_t subAddress,
-                             uint8_t subAddressSize,
-                             uint8_t *rxBuff,
-                             uint8_t rxBuffSize)
-{
-    lpi2c_master_transfer_t xfer;
-
-    xfer.flags          = kLPI2C_TransferDefaultFlag;
-    xfer.slaveAddress   = deviceAddress;
-    xfer.direction      = kLPI2C_Read;
-    xfer.subaddress     = subAddress;
-    xfer.subaddressSize = subAddressSize;
-    xfer.data           = rxBuff;
-    xfer.dataSize       = rxBuffSize;
-
-    return LPI2C_MasterTransferBlocking(base, &xfer);
-}
-
-status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
-                              uint8_t deviceAddress,
-                              uint32_t subAddress,
-                              uint8_t subAddressSize,
-                              uint8_t *txBuff,
-                              uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
-}
-
-status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
-                                 uint8_t deviceAddress,
-                                 uint32_t subAddress,
-                                 uint8_t subAddressSize,
-                                 uint8_t *rxBuff,
-                                 uint8_t rxBuffSize)
-{
-    status_t status;
-    lpi2c_master_transfer_t xfer;
-
-    xfer.flags          = kLPI2C_TransferDefaultFlag;
-    xfer.slaveAddress   = deviceAddress;
-    xfer.direction      = kLPI2C_Write;
-    xfer.subaddress     = subAddress;
-    xfer.subaddressSize = subAddressSize;
-    xfer.data           = NULL;
-    xfer.dataSize       = 0;
-
-    status = LPI2C_MasterTransferBlocking(base, &xfer);
-
-    if (kStatus_Success == status)
-    {
-        xfer.subaddressSize = 0;
-        xfer.direction      = kLPI2C_Read;
-        xfer.data           = rxBuff;
-        xfer.dataSize       = rxBuffSize;
-
-        status = LPI2C_MasterTransferBlocking(base, &xfer);
-    }
-
-    return status;
-}
-
-void BOARD_Accel_I2C_Init(void)
-{
-    BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
-}
-
-status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
-{
-    uint8_t data = (uint8_t)txBuff;
-
-    return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
-}
-
-status_t BOARD_Accel_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
-}
-
-void BOARD_Codec_I2C_Init(void)
-{
-    BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
-}
-
-status_t BOARD_Codec_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
-                            txBuffSize);
-}
-
-status_t BOARD_Codec_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
-}
-
-void BOARD_Camera_I2C_Init(void)
-{
-    LP_FLEXCOMM_Init(BOARD_CAMERA_I2C_INSTANCE, LP_FLEXCOMM_PERIPH_LPI2C);
-    BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
-}
-
-status_t BOARD_Camera_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
-                            txBuffSize);
-}
-
-status_t BOARD_Camera_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
-                               rxBuffSize);
-}
-
-status_t BOARD_Camera_I2C_SendSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
-{
-    return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
-                                txBuffSize);
-}
-
-status_t BOARD_Camera_I2C_ReceiveSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
-{
-    return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
-                                   rxBuffSize);
-}
-
-#endif /* SDK_I2C_BASED_COMPONENT_USED */
-
-/* Update Active mode voltage for OverDrive mode. */
-void BOARD_PowerMode_OD(void)
-{
-    spc_active_mode_dcdc_option_t opt = {
-        .DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
-        .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
-    };
-    SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
-
-    spc_sram_voltage_config_t cfg = {
-        .operateVoltage       = kSPC_sramOperateAt1P2V,
-        .requestVoltageUpdate = true,
-    };
-    SPC_SetSRAMOperateVoltage(SPC0, &cfg);
-}

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/board.h

@@ -1,261 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include "clock_config.h"
-#include "fsl_gpio.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief The board name */
-#define BOARD_NAME "FRDM-MCXN947"
-
-/*! @brief The UART to use for debug messages. */
-#define BOARD_DEBUG_UART_TYPE       kSerialPort_Uart
-#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) LPUART4
-#define BOARD_DEBUG_UART_INSTANCE   4U
-#define BOARD_DEBUG_UART_CLK_FREQ   12000000U
-#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4
-#define BOARD_DEBUG_UART_RST        kFC4_RST_SHIFT_RSTn
-#define BOARD_DEBUG_UART_CLKSRC     kCLOCK_FlexComm4
-#define BOARD_UART_IRQ_HANDLER      LP_FLEXCOMM4_IRQHandler
-#define BOARD_UART_IRQ              LP_FLEXCOMM4_IRQn
-
-#define BOARD_DEBUG_UART_TYPE_CORE1       kSerialPort_Uart
-#define BOARD_DEBUG_UART_BASEADDR_CORE1   (uint32_t) USART1
-#define BOARD_DEBUG_UART_INSTANCE_CORE1   1U
-#define BOARD_DEBUG_UART_CLK_FREQ_CORE1   12000000U
-#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
-#define BOARD_DEBUG_UART_RST_CORE1        kFC1_RST_SHIFT_RSTn
-#define BOARD_DEBUG_UART_CLKSRC_CORE1     kCLOCK_Flexcomm1
-#define BOARD_UART_IRQ_HANDLER_CORE1      FLEXCOMM1_IRQHandler
-#define BOARD_UART_IRQ_CORE1              FLEXCOMM1_IRQn
-
-#ifndef BOARD_DEBUG_UART_BAUDRATE
-#define BOARD_DEBUG_UART_BAUDRATE 115200U
-#endif /* BOARD_DEBUG_UART_BAUDRATE */
-
-#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
-#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
-#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
-
-/*! @brief The UART to use for Bluetooth M.2 interface. */
-#define BOARD_BT_UART_INSTANCE   2
-#define BOARD_BT_UART_BAUDRATE   3000000
-#define BOARD_BT_UART_CLK_FREQ   12000000U
-#define BOARD_BT_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM2
-
-/*! @brief The ENET PHY address. */
-#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */
-
-/*! @brief Memory ranges not usable by the ENET DMA. */
-#ifndef BOARD_ENET_NON_DMA_MEMORY_ARRAY
-#define BOARD_ENET_NON_DMA_MEMORY_ARRAY                                                     \
-    {                                                                                       \
-        {0x00000000U, 0x0007FFFFU}, {0x10000000U, 0x17FFFFFFU}, {0x80000000U, 0xDFFFFFFFU}, \
-            {0x00000000U, 0x00000000U},                                                     \
-    }
-#endif /* BOARD_ENET_NON_DMA_MEMORY_ARRAY */
-
-#define BOARD_ACCEL_I2C_BASEADDR   LPI2C2
-#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
-
-#define BOARD_CODEC_I2C_BASEADDR   LPI2C2
-#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
-#define BOARD_CODEC_I2C_INSTANCE   2
-
-/*! @brief Indexes of the TSI channels for on-board electrodes */
-#ifndef BOARD_TSI_ELECTRODE_1
-#define BOARD_TSI_ELECTRODE_1 3U
-#endif
-
-/*! @brief Indexes of the TSI mutual channels for FRDM-TOUCH board */
-#define BOARD_TSI_MUTUAL_TX_ELECTRODE_1 0U
-#define BOARD_TSI_MUTUAL_RX_ELECTRODE_1 14U
-
-#ifndef BOARD_LED_RED_GPIO
-#define BOARD_LED_RED_GPIO GPIO0
-#endif
-#ifndef BOARD_LED_RED_GPIO_PIN
-#define BOARD_LED_RED_GPIO_PIN 10U
-#endif
-
-#ifndef BOARD_LED_BLUE_GPIO
-#define BOARD_LED_BLUE_GPIO GPIO1
-#endif
-#ifndef BOARD_LED_BLUE_GPIO_PIN
-#define BOARD_LED_BLUE_GPIO_PIN 2U
-#endif
-
-#ifndef BOARD_LED_GREEN_GPIO
-#define BOARD_LED_GREEN_GPIO GPIO0
-#endif
-#ifndef BOARD_LED_GREEN_GPIO_PIN
-#define BOARD_LED_GREEN_GPIO_PIN 27U
-#endif
-
-#ifndef BOARD_SW2_GPIO
-#define BOARD_SW2_GPIO GPIO0
-#endif
-#ifndef BOARD_SW2_GPIO_PIN
-#define BOARD_SW2_GPIO_PIN 23U
-#endif
-#define BOARD_SW2_NAME        "SW2"
-#define BOARD_SW2_IRQ         GPIO00_IRQn
-#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler
-
-#ifndef BOARD_SW3_GPIO
-#define BOARD_SW3_GPIO GPIO0
-#endif
-#ifndef BOARD_SW3_GPIO_PIN
-#define BOARD_SW3_GPIO_PIN 6U
-#endif
-#define BOARD_SW3_NAME        "SW3"
-#define BOARD_SW3_IRQ         GPIO00_IRQn
-#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler
-
-/* USB PHY condfiguration */
-#define BOARD_USB_PHY_D_CAL     (0x04U)
-#define BOARD_USB_PHY_TXCAL45DP (0x07U)
-#define BOARD_USB_PHY_TXCAL45DM (0x07U)
-
-#define BOARD_HAS_NO_CTIMER_OUTPUT_PIN_CONNECTED_TO_LED (1)
-
-/* Board led color mapping */
-#define LOGIC_LED_ON  0U
-#define LOGIC_LED_OFF 1U
-
-#define LED_RED_INIT(output)                                           \
-    GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
-    BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN)                         /*!< Enable target LED_RED */
-#define LED_RED_ON()     GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN)  /*!< Turn on target LED_RED */
-#define LED_RED_OFF()    GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN)    /*!< Turn off target LED_RED */
-#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
-
-#define LED_BLUE_INIT(output)                                            \
-    GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
-    BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN)                       /*!< Enable target LED_BLUE */
-#define LED_BLUE_ON()     GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN)  /*!< Turn on target LED_BLUE */
-#define LED_BLUE_OFF()    GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN)    /*!< Turn off target LED_BLUE */
-#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
-
-#define LED_GREEN_INIT(output)                                             \
-    GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
-    BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
-#define LED_GREEN_ON()     GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN)  /*!< Turn on target LED_GREEN */
-#define LED_GREEN_OFF()    GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN)    /*!< Turn off target LED_GREEN */
-#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
-
-/* Display. */
-#define BOARD_LCD_DC_GPIO      GPIO0
-#define BOARD_LCD_DC_GPIO_PORT 0U
-#define BOARD_LCD_DC_GPIO_PIN  10U
-
-/* Camera */
-#define BOARD_CAMERA_I2C_BASEADDR         LPI2C7
-#define BOARD_CAMERA_I2C_INSTANCE         7
-#define BOARD_CAMERA_I2C_CLOCK_FREQ       CLOCK_GetLPFlexCommClkFreq(BOARD_CAMERA_I2C_INSTANCE)
-
-/* Serial MWM WIFI */
-#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
-#define BOARD_SERIAL_MWM_PORT          USART2
-#define BOARD_SERIAL_MWM_PORT_IRQn     FLEXCOMM2_IRQn
-#define BOARD_SERIAL_MWM_RST_WRITE(output)
-
-/*! @brief The EMVSIM SMARTCARD PHY configuration. */
-#define BOARD_SMARTCARD_MODULE                (EMVSIM0)      /*!< SMARTCARD communicational module instance */
-#define BOARD_SMARTCARD_MODULE_IRQ            (EMVSIM0_IRQn) /*!< SMARTCARD communicational module IRQ handler */
-#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetEmvsimClkFreq(0U))
-#define BOARD_SMARTCARD_CLOCK_VALUE           (4000000U) /*!< SMARTCARD clock frequency */
-
-/* ERPC LPSPI configuration */
-#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1)
-#define ERPC_BOARD_LPSPI_BASEADDR             LPSPI3
-#define ERPC_BOARD_LPSPI_BAUDRATE             500000U
-#define ERPC_BOARD_LPSPI_CLKSRC               kCLOCK_Flexcomm3
-#define ERPC_BOARD_LPSPI_CLK_FREQ             12000000 // CLOCK_GetFlexCommClkFreq(1)
-#define ERPC_BOARD_LPSPI_INT_GPIO             GPIO0
-#define ERPC_BOARD_LPSPI_INT_PIN              16U
-#define ERPC_BOARD_LPSPI_INT_PIN_IRQ          PIN_INT0_IRQn
-#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER  PIN_INT0_IRQHandler
-
-/* ERPC LPI2C configuration */
-#define ERPC_BOARD_LPI2C_BASEADDR            LPI2C0_BASE
-#define ERPC_BOARD_LPI2C_BAUDRATE            100000U
-#define ERPC_BOARD_LPI2C_CLKSRC              kCLOCK_Flexcomm0
-#define ERPC_BOARD_LPI2C_CLK_FREQ            12000000 // CLOCK_GetFlexCommClkFreq(2)
-#define ERPC_BOARD_LPI2C_INT_GPIO            GPIO1
-#define ERPC_BOARD_LPI2C_INT_PIN             0U
-#define ERPC_BOARD_LPI2C_INT_PIN_IRQ         PIN_INT1_IRQn
-#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-void BOARD_InitDebugConsole(void);
-void BOARD_InitDebugConsole_Core1(void);
-#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
-void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
-status_t BOARD_LPI2C_Send(LPI2C_Type *base,
-                          uint8_t deviceAddress,
-                          uint32_t subAddress,
-                          uint8_t subaddressSize,
-                          uint8_t *txBuff,
-                          uint8_t txBuffSize);
-status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
-                             uint8_t deviceAddress,
-                             uint32_t subAddress,
-                             uint8_t subaddressSize,
-                             uint8_t *rxBuff,
-                             uint8_t rxBuffSize);
-status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
-                              uint8_t deviceAddress,
-                              uint32_t subAddress,
-                              uint8_t subaddressSize,
-                              uint8_t *txBuff,
-                              uint8_t txBuffSize);
-status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
-                                 uint8_t deviceAddress,
-                                 uint32_t subAddress,
-                                 uint8_t subaddressSize,
-                                 uint8_t *rxBuff,
-                                 uint8_t rxBuffSize);
-void BOARD_Accel_I2C_Init(void);
-status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
-status_t BOARD_Accel_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-void BOARD_Codec_I2C_Init(void);
-status_t BOARD_Codec_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
-status_t BOARD_Codec_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-void BOARD_Camera_I2C_Init(void);
-status_t BOARD_Camera_I2C_Send(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
-status_t BOARD_Camera_I2C_Receive(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-
-status_t BOARD_Camera_I2C_SendSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
-status_t BOARD_Camera_I2C_ReceiveSCCB(
-    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
-#endif /* SDK_I2C_BASED_COMPONENT_USED */
-
-void BOARD_PowerMode_OD(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-#endif /* _BOARD_H_ */

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/clock_config.c

@@ -1,354 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v11.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.13.10
-board: FRDM-MCXN947
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_clock.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(12000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: RunPowerMode, value: OD}
-- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(48000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 36 MHz}
-- {id: System_clock.outFreq, value: 144 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: RunPowerMode, value: OD}
-- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
-- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(144000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(150000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    CLOCK_EnableClock(kCLOCK_Scg);                     /*!< Enable SCG clock */
-
-    /* FRO OSC setup - begin, enable the FRO for safety switching */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);              /*!< Switch to FRO 12M first to ensure we can change the clock setting */
-
-    CLOCK_SetFLASHAccessCyclesForFreq(100000000U, kOD_Mode);           /*!< Set the additional number of flash wait-states */
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
-

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/clock_config.h

@@ -1,177 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
-

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/peripherals.c

@@ -1,23 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Peripherals v1.0
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-
-/*******************************************************************************
- * Included files
- ******************************************************************************/
-#include "peripherals.h"
-
-/*******************************************************************************
- * BOARD_InitBootPeripherals function
- ******************************************************************************/
-void BOARD_InitBootPeripherals(void)
-{
-}

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/peripherals.h

@@ -1,23 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _PERIPHERALS_H_
-#define _PERIPHERALS_H_
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /*_cplusplus. */
-/*******************************************************************************
- * BOARD_InitBootPeripherals function
- ******************************************************************************/
-void BOARD_InitBootPeripherals(void);
-
-#if defined(__cplusplus)
-}
-#endif /*_cplusplus. */
-
-#endif /* _PERIPHERALS_H_ */

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/pin_mux.c

@@ -1,705 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v14.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.14.19
-board: FRDM-MCXN947
-expansion_headers:
-- id: micro_bus
-  name: mikroBUS(TM)
-  connectors:
-  - id: C1
-    name: J6
-    pins:
-    - {id: 1, name: AN, pin_num: T2, pin_signal: ADC1_A0}
-    - {id: 2, name: RST, pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1}
-    - {id: 3, name: CS, pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1}
-    - {id: 4, name: SCK, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
-    - {id: 5, name: MISO, pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1}
-    - {id: 6, name: MOSI, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
-  - id: C2
-    name: J5
-    pins:
-    - {id: 1, name: PWM, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
-    - {id: 2, name: INT, pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15}
-    - {id: 3, name: RX, pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16}
-    - {id: 4, name: TX, pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17}
-    - {id: 5, name: SCL, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
-    - {id: 6, name: SDA, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
-- id: frdm_arduino
-  name: LPCXpresso V3 (Arduino compatible)
-  connectors:
-  - id: C1
-    name: J3
-    pins:
-    - {id: 1, pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK}
-    - {id: 2, pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3}
-    - {id: 3, pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22}
-    - {id: 5, pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0}
-    - {id: 6, pin_num: F3, pin_signal: RESET_B}
-    - {id: 7, pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0}
-    - {id: 9, pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1}
-    - {id: 11, pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1}
-    - {id: 13, pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS}
-    - {id: 15, pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK}
-  - id: C2
-    name: J2
-    pins:
-    - {id: 1, pin_num: T3, pin_signal: ADC1_B0}
-    - {id: 2, pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20}
-    - {id: 3, pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10}
-    - {id: 4, pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10}
-    - {id: 5, pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11}
-    - {id: 6, pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19}
-    - {id: 7, pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12}
-    - {id: 8, pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16}
-    - {id: 9, pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1}
-    - {id: 10, pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18}
-    - {id: 11, pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10}
-    - {id: 12, pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17}
-    - {id: 13, pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11}
-    - {id: 15, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
-    - {id: 17, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
-    - {id: 18, pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3}
-    - {id: 20, pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1}
-  - id: C3
-    name: J1
-    pins:
-    - {id: 1, pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK}
-    - {id: 2, pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N}
-    - {id: 3, pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5}
-    - {id: 4, pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N}
-    - {id: 5, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
-    - {id: 6, pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21}
-    - {id: 7, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
-    - {id: 8, pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23}
-    - {id: 9, pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK}
-    - {id: 10, pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22}
-    - {id: 11, pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS}
-    - {id: 12, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
-    - {id: 13, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
-    - {id: 14, pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0}
-    - {id: 15, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
-    - {id: 16, pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23}
-  - id: C4
-    name: J4
-    pins:
-    - {id: 1, pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5}
-    - {id: 2, pin_num: P3, pin_signal: ADC0_A0}
-    - {id: 3, pin_num: U6, pin_signal: OPAMP0_INN}
-    - {id: 4, pin_num: R3, pin_signal: ADC0_B0}
-    - {id: 5, pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6}
-    - {id: 6, pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14}
-    - {id: 7, pin_num: U8, pin_signal: OPAMP1_INN}
-    - {id: 8, pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2}
-    - {id: 9, pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6}
-    - {id: 10, pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15}
-    - {id: 11, pin_num: U10, pin_signal: OPAMP2_INN}
-    - {id: 12, pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2}
-- {id: frdm_arduino, name: LPCXpressoV2/V3 Expansion Header}
-- {id: micro_bus, name: mikroBUS Click Header}
-external_user_signals: {}
-pin_labels:
-- {pin_num: A1, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8, label: 'P1_8/J9[32]',
-  identifier: DEBUG_UART_RX}
-- {pin_num: B1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9, label: 'P1_9/J9[30]', identifier: DEBUG_UART_TX}
-- {pin_num: D1, pin_signal: PIO1_13/TRIG_IN3/FC4_P5/FC3_P1/CT2_MAT3/SCT0_OUT5/FLEXIO0_D21/PLU_OUT3/ENET0_RXDV/CAN1_TXD/TSI0_CH22/ADC1_A13, label: 'P1_13/J9[27]'}
-- {pin_num: F1, pin_signal: PIO1_30/TRIG_OUT3/CT_INP16/SCT0_OUT8/SAI0_MCLK/XTAL48M, label: 'P1_30/XTAL/Y1[1]'}
-- {pin_num: H1, pin_signal: PIO2_1/TRACE_CLK/SDHC0_D4/SCT0_IN1/PWM1_B3/FLEXIO0_D9/FLEXSPI0_B_DQS/SINC0_MCLK_OUT0/SAI0_RX_FS, label: 'P2_1/TP27/J12[9]'}
-- {pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1, label: 'P2_5/TP25/J12[3]/J3[9]/SJ6[3]'}
-- {pin_num: M1, pin_signal: PIO2_9/TRACE_DATA1/SDHC0_D6/SCT0_IN3/PWM1_X1/FLEXIO0_D17/FLEXSPI0_B_DATA5/SINC0_MBIT3/SAI1_RXD0, label: 'P2_9/J8[14]'}
-- {pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3, label: 'P4_0/J8[4]/SJ14[1]'}
-- {pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N, label: 'P4_2/J1[4]'}
-- {pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N, label: 'P4_3/J1[2]'}
-- {pin_num: A2, pin_signal: PIO1_7/WUU0_IN9/TRIG_OUT2/FC5_P3/CT_INP7/SCT0_IN1/FLEXIO0_D15/PLU_CLK/ENET0_TXD1/SAI1_RX_FS/CAN1_RXD/TSI0_CH7/ADC0_A23, label: 'P1_7/J9[9]'}
-- {pin_num: B2, pin_signal: PIO1_6/TRIG_IN2/FC3_P6/FC5_P2/CT_INP6/SCT0_IN0/FLEXIO0_D14/ENET0_TXD0/SAI1_RX_BCLK/CAN1_TXD/TSI0_CH6/ADC0_A22, label: 'P1_6/J9[10]'}
-- {pin_num: D2, pin_signal: PIO1_12/WUU0_IN12/TRACE_CLK/FC4_P4/FC3_P0/CT2_MAT2/SCT0_OUT4/FLEXIO0_D20/PLU_OUT2/ENET0_RXER/CAN1_RXD/TSI0_CH21/ADC1_A12, label: 'P1_12/J2[11]/J9[28]'}
-- {pin_num: F2, pin_signal: PIO1_31/TRIG_IN4/CT_INP17/SCT0_OUT9/EXTAL48M, label: 'P1_31/EXTAL/Y1[3]'}
-- {pin_num: G2, pin_signal: VSS0, label: GND}
-- {pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK, label: 'P2_0/J3[1]/SJ8[3]'}
-- {pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK, label: 'P2_6/TP24/J12[2]/J3[15]/SJ1[3]'}
-- {pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS, label: 'P2_7/TP23/J12[1]/J3[13]/SJ3[3]'}
-- {pin_num: M2, pin_signal: PIO2_8/TRACE_DATA0/SDHC0_D7/SCT0_IN2/PWM1_X0/FLEXIO0_D16/FLEXSPI0_B_DATA4/SINC0_MCLK3/SAI1_TXD0, label: 'P2_8/J8[13]'}
-- {pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1, label: 'P4_1/J8[3]/SJ15[1]'}
-- {pin_num: T2, pin_signal: ADC1_A0, label: 'ANA_4/ADC1_A0/J6[1]'}
-- {pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3, label: 'ANA_6/ADC0_A3/J3[2]'}
-- {pin_num: B3, pin_signal: PIO1_5/FREQME_CLK_IN1/FC3_P5/FC5_P1/CT1_MAT3/SCT0_OUT1/FLEXIO0_D13/ENET0_TXEN/SAI0_RXD1/TSI0_CH5/ADC0_A21/CMP0_IN3, label: 'P1_5/J9[7]'}
-- {pin_num: C3, pin_signal: PIO1_10/TRACE_DATA2/FC4_P2/FC5_P6/CT2_MAT0/SCT0_IN2/FLEXIO0_D18/PLU_IN0/ENET0_TXER/CAN0_TXD/TSI0_CH19/ADC1_A10, label: 'P1_10/SJ20[3]/SJ16[2]'}
-- {pin_num: D3, pin_signal: PIO1_11/WUU0_IN11/TRACE_DATA3/FC4_P3/CT2_MAT1/SCT0_IN3/FLEXIO0_D19/PLU_IN1/ENET0_RX_CLK/I3C1_PUR/CAN0_RXD/TSI0_CH20/ADC1_A11, label: 'P1_11/SJ26[2]'}
-- {pin_num: F3, pin_signal: RESET_B, label: 'RESET_B/J23[10]/D16[1]/SW1[3]/SW1[4]/J3[6]', identifier: SW1}
-- {pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0, label: 'P2_2/TP5/J12[8]/J3[7]/SJ7[3]'}
-- {pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0, label: 'P2_3/TP4/J12[7]/J3[5]/SJ4[3]'}
-- {pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1, label: 'P2_4/TP26/J12[5]/J3[11]/SJ5[3]'}
-- {pin_num: M3, pin_signal: PIO2_10/TRACE_DATA2/SCT0_IN4/PWM1_X2/FLEXIO0_D18/FLEXSPI0_B_DATA6/SINC0_MCLK4/SAI1_RXD1, label: 'P2_10/J8[15]'}
-- {pin_num: P3, pin_signal: ADC0_A0, label: 'ADC0_A0/ARD_A0/J4[2]'}
-- {pin_num: R3, pin_signal: ADC0_B0, label: 'ADC0_B0/ARD_A1/J4[4]'}
-- {pin_num: T3, pin_signal: ADC1_B0, label: 'ADC1_B0/MC_BEMF_A/J2[1]'}
-- {pin_num: A4, pin_signal: PIO1_4/WUU0_IN8/FREQME_CLK_IN0/FC3_P4/FC5_P0/CT1_MAT2/SCT0_OUT0/FLEXIO0_D12/ENET0_TX_CLK/SAI0_TXD1/TSI0_CH4/ADC0_A20/CMP0_IN2, label: 'P1_4/SJ27[2]'}
-- {pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1, label: 'P1_3/J6[2]'}
-- {pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0, label: 'P1_2/SJ4[1]',
-  identifier: LED_BLUE}
-- {pin_num: D4, pin_signal: PIO1_14/FC4_P6/FC3_P2/CT_INP10/SCT0_IN4/FLEXIO0_D22/PLU_IN2/ENET0_RXD0/TSI0_CH23/ADC1_A14, label: 'P1_14/J9[2]'}
-- {pin_num: E4, pin_signal: PIO1_15/WUU0_IN13/FC3_P3/CT_INP11/SCT0_IN5/FLEXIO0_D23/PLU_IN3/ENET0_RXD1/I3C1_PUR/TSI0_CH24/ADC1_A15, label: 'P1_15/J9[1]'}
-- {pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17, label: 'P1_17/SJ15[3]/J5[4]/J9[3]'}
-- {pin_num: G4, pin_signal: PIO1_18/FREQME_CLK_IN0/FC5_P2/FC3_P6/CT3_MAT0/SCT0_IN6/FLEXIO0_D26/PLU_IN4/ENET0_COL/CAN0_TXD/ADC1_A18, label: 'P1_18/J9[6]'}
-- {pin_num: J4, pin_signal: VSS1, label: GND}
-- {pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22, label: 'P1_22/J9[24]/J3[3]/SJ9[3]'}
-- {pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23, label: 'P1_23/J9[23]/SJ1[1]'}
-- {pin_num: N4, pin_signal: PIO2_11/TRACE_DATA3/SCT0_IN5/PWM1_X3/FLEXIO0_D19/FLEXSPI0_B_DATA7/SINC0_MBIT4/SAI1_TXD1, label: 'P2_11/J8[16]'}
-- {pin_num: P4, pin_signal: VDD_P40, label: VDD_P4}
-- {pin_num: R4, pin_signal: VDD_ANA, label: 'VDD_ANA/J2[16]'}
-- {pin_num: T4, pin_signal: PIO4_7/CT_INP19, label: 'P4_7/J8[7]'}
-- {pin_num: U4, pin_signal: VREFO/ADC0_A7/ADC1_A7, label: VREFO/TP1}
-- {pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0, label: 'P1_1/J5[5]/J2[15]'}
-- {pin_num: E5, pin_signal: VSS3, label: GND}
-- {pin_num: G5, pin_signal: PIO1_19/WUU0_IN15/FREQME_CLK_IN1/FC5_P3/CT3_MAT1/SCT0_IN7/FLEXIO0_D27/PLU_IN5/ENET0_CRS/CAN0_RXD/ADC1_A19, label: 'P1_19/J9[5]'}
-- {pin_num: H5, pin_signal: VSS2, label: GND}
-- {pin_num: K5, pin_signal: PIO1_20/TRIG_IN2/FC5_P4/FC4_P0/CT3_MAT2/SCT0_OUT8/FLEXIO0_D28/PLU_OUT6/ENET0_MDC/CAN1_TXD/ADC1_A20/CMP1_IN3, label: P1_20}
-- {pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3, label: 'P1_21/SJ3[1]/J1[7]'}
-- {pin_num: N5, pin_signal: VDD_P41, label: VDD_P4}
-- {pin_num: R5, pin_signal: VREFH, label: VREFH}
-- {pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17, label: 'P0_25/J2[12]'}
-- {pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16, label: 'P0_24/SJ7[1]'}
-- {pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0, label: 'P1_0/J5[6]/J2[17]'}
-- {pin_num: N13, pin_signal: VSS4, label: GND}
-- {pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16, label: 'P1_16/SJ14[3]/J5[3]/J9[4]'}
-- {pin_num: H6, pin_signal: VDD1, label: VDD_P0/1}
-- {pin_num: K6, pin_signal: VDD_LDO_CORE, label: VDD_LDO_CORE_IN}
-- {pin_num: M6, pin_signal: PIO4_4/FC2_P4/CT_INP14/PLU_IN4/SINC0_MCLK4, label: 'P4_4/J9[26]'}
-- {pin_num: P6, pin_signal: VSS_P41, label: GND}
-- {pin_num: R6, pin_signal: VREFL, label: AGND}
-- {pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5, label: 'P4_12/SJ25[1]/J8[17]'}
-- {pin_num: U6, pin_signal: OPAMP0_INN, label: 'OPAMP0_INN/RSHUNT_CURA_N/SJ24[1]'}
-- {pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, label: 'P0_23/SJ9[1]/SW2[3]/SW2[4]', identifier: SW2}
-- {pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23, label: 'P0_31/J1[16]'}
-- {pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22, label: 'P0_30/SJ2[1]'}
-- {pin_num: G7, pin_signal: VDD0, label: VDD_P0/1}
-- {pin_num: L7, pin_signal: VDD_P20, label: VDD_P2}
-- {pin_num: N7, pin_signal: PIO4_6/TRIG_OUT4/FC2_P6/CT_INP18/PLU_CLK, label: 'P4_6/J8[5]'}
-- {pin_num: P7, pin_signal: VSS_P42, label: GND}
-- {pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5, label: 'P4_13/SJ10[1]/SJ2[3]/J8[18]'}
-- {pin_num: A8, pin_signal: PIO0_21/FC0_P5/FC1_P1/CT_INP1/FLEXIO0_D5/I3C0_SCL/TSI0_CH16/ADC0_A13, label: 'P0_21/SJ25[3]'}
-- {pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2, label: 'P0_22/J4[8]/SJ18[3]'}
-- {pin_num: C8, pin_signal: PIO0_20/WUU0_IN4/FC0_P4/FC1_P0/CT_INP0/FLEXIO0_D4/I3C0_SDA/TSI0_CH15/ADC0_A12, label: 'P0_20/SJ24[3]/J7[2]'}
-- {pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20, label: 'P0_28/J2[2]'}
-- {pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21, label: 'P0_29/J1[6]'}
-- {pin_num: H8, pin_signal: VDD2, label: VDD_P0/1}
-- {pin_num: H13, pin_signal: VSS10, label: GND}
-- {pin_num: K8, pin_signal: VDD_P21, label: VDD_P2}
-- {pin_num: M8, pin_signal: PIO4_5/FC2_P5/CT_INP15/PLU_IN5/SINC0_MBIT4, label: 'P4_5/SJ11[3]/J8[6]'}
-- {pin_num: N8, pin_signal: PIO4_14/CT4_MAT2/FLEXIO0_D22/PLU_OUT2, label: 'P4_14/J8[19]'}
-- {pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6, label: 'P4_16/SJ23[1]/J8[21]'}
-- {pin_num: T8, pin_signal: PIO4_15/WUU0_IN21/TRIG_OUT4/USB1_VBUS_DIG/CT4_MAT3/FLEXIO0_D23/PLU_OUT3/SINC0_MCLK_OUT0/CAN1_RXD/OPAMP0_OUT/ADC0_A1/CMP0_IN4P, label: 'P4_15/J8[20]'}
-- {pin_num: U8, pin_signal: OPAMP1_INN, label: 'OPAMP1_INN/RSHUNT_CURB_N/SJ22[1]'}
-- {pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11, label: 'P0_19/J2[13]/J7[1]'}
-- {pin_num: D6, pin_signal: VSS5, label: GND}
-- {pin_num: E13, pin_signal: VSS8, label: GND}
-- {pin_num: J14, pin_signal: VSS13, label: GND}
-- {pin_num: P9, pin_signal: VSS_P40, label: GND}
-- {pin_num: R9, pin_signal: PIO4_17/TRIG_IN9/FC2_P3/USB1_OTG_OC/CT3_MAT1/FLEXIO0_D25/PLU_OUT5/SINC0_MBIT1/OPAMP1_INP1/ADC0_B6, label: 'P4_17/J8[22]'}
-- {pin_num: A10, pin_signal: PIO0_17/FC0_P1/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1/PDM0_DATA0/I3C0_SCL/TSI0_CH12/ADC0_A9, label: 'P0_17/J7[7]'}
-- {pin_num: B10, pin_signal: PIO0_16/WUU0_IN2/FC0_P0/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0/PDM0_CLK/I3C0_SDA/TSI0_CH11/ADC0_A8, label: 'P0_16/J7[3]'}
-- {pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10, label: 'P0_18/SJ23[3]/J7[5]'}
-- {pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, label: 'P0_27/SJ6[1]', identifier: LED_GREEN}
-- {pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18, label: 'P0_26/J2[10]'}
-- {pin_num: H10, pin_signal: VDD_P31, label: VDD_P3}
-- {pin_num: J8, pin_signal: VSS11, label: GND}
-- {pin_num: K10, pin_signal: VDD_CORE/VOUT_CORE, label: 'VDD_CORE/L2[2]'}
-- {pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10, label: 'P5_2/SJ19[1]'}
-- {pin_num: N10, pin_signal: PIO4_18/CT3_MAT2/FLEXIO0_D26/PLU_OUT6, label: 'P4_18/J8[23]'}
-- {pin_num: R10, pin_signal: PIO4_19/TRIG_OUT5/CT3_MAT3/FLEXIO0_D27/PLU_OUT7/SINC0_MCLK_OUT1/OPAMP1_OUT/ADC0_B1/CMP1_IN4P, label: 'P4_19/J8[24]'}
-- {pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6, label: 'P4_20/SJ21[1]/J8[25]'}
-- {pin_num: U10, pin_signal: OPAMP2_INN, label: 'OPAMP2_INN/RSHUNT_CURC_N/SJ20[1]'}
-- {pin_num: B11, pin_signal: PIO0_11/CT0_MAT1/FLEXIO0_D3/HSCMP2_OUT/ADC0_B11, label: 'P0_11/J9[18]'}
-- {pin_num: D11, pin_signal: PIO0_12/FC1_P4/FC0_P0/CT0_MAT2/FLEXIO0_D4/ADC0_B12, label: 'P0_12/J8[9]'}
-- {pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14, label: 'P0_14/J4[6]/SJ19[3]'}
-- {pin_num: G11, pin_signal: VDD_P30, label: VDD_P3}
-- {pin_num: L11, pin_signal: VDD_CORE, label: 'VDD_CORE/L2[2]'}
-- {pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11, label: 'P5_3/SJ18[1]'}
-- {pin_num: P11, pin_signal: USB1_ID, label: 'HS_USB_ID/Q1[2]'}
-- {pin_num: T11, pin_signal: PIO4_21/TRIG_IN9/FC2_P5/CT2_MAT1/FLEXIO0_D29/SINC0_MBIT2/OPAMP2_INP1/ADC1_B6, label: 'P4_21/J8[26]'}
-- {pin_num: A12, pin_signal: PIO0_9/FC0_P5/CT_INP1/FLEXIO0_D1/ADC0_B9, label: 'P0_9/J8[10]'}
-- {pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, label: 'P0_10/SJ5[1]', identifier: LED_RED}
-- {pin_num: C12, pin_signal: PIO0_8/FC0_P4/CT_INP0/FLEXIO0_D0/ADC0_B8, label: 'P0_8/J8[11]'}
-- {pin_num: D9, pin_signal: VSS6, label: GND}
-- {pin_num: F12, pin_signal: PIO0_13/FC1_P5/FC0_P1/CT0_MAT3/FLEXIO0_D5/ADC0_B13, label: 'P0_13/J8[12]'}
-- {pin_num: H12, pin_signal: VDD_P42, label: VDD_P3}
-- {pin_num: K12, pin_signal: PIO5_5/TRIG_IN10/LPTMR0_ALT2/TAMPER3/ADC1_B13, label: 'P5_5/SJ17[3]'}
-- {pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12, label: 'P5_4/J2[7]'}
-- {pin_num: P14, pin_signal: VDD3, label: GND}
-- {pin_num: R12, pin_signal: VDD_USB, label: VDD_USB}
-- {pin_num: T12, pin_signal: PIO4_22/CT2_MAT2/FLEXIO0_D30, label: 'P4_22/J8[27]'}
-- {pin_num: U12, pin_signal: PIO4_23/TRIG_OUT5/FC2_P6/CT2_MAT3/FLEXIO0_D31/SINC0_MCLK_OUT2/OPAMP2_OUT/ADC0_A2/ADC0_B2/ADC1_B3/CMP2_IN4P, label: 'P4_23/J8[28]'}
-- {pin_num: C13, pin_signal: PIO0_7/WUU0_IN1/FC0_P3/CT_INP3/CMP2_IN1, label: 'P0_7/J8[8]'}
-- {pin_num: D12, pin_signal: VSS7, label: GND}
-- {pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15, label: 'P0_15/SJ8[1]'}
-- {pin_num: H9, pin_signal: VSS9, label: GND}
-- {pin_num: K13, pin_signal: PIO5_6/TRIG_OUT6/LPTMR1_ALT2/TAMPER4/ADC1_B14, label: 'P5_6/SJ13[1]'}
-- {pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15, label: 'P5_7/J5[2]'}
-- {pin_num: R13, pin_signal: USB1_DP, label: 'MCX_USB1_DP/L13[3]'}
-- {pin_num: A14, pin_signal: PIO0_5/EWM0_OUT_b/FC0_P1/FC1_P5/CT0_MAT3/UTICK_CAP3/PDM0_DATA0/TSI0_CH9, label: 'P0_5/SJ13[3]/J9[15]/SJ21[3]'}
-- {pin_num: B14, pin_signal: PIO0_4/WUU0_IN0/EWM0_IN/FC0_P0/FC1_P4/CT0_MAT2/UTICK_CAP2/HSCMP1_OUT/PDM0_CLK/TSI0_CH8, label: 'P0_4/SJ12[3]/J9[17]/SJ22[3]'}
-- {pin_num: C14, pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, label: 'P0_6/J23[7]/SW3[3]/SW3[4]', identifier: SW3}
-- {pin_num: D14, pin_signal: PIO3_7/FC6_P6/FC7_P1/CT4_MAT3/PWM0_B1/FLEXIO0_D15/FLEXSPI0_A_SCLK/SIM0_VCCEN/SAI0_MCLK, label: 'P3_7/TP18/U8[6]/U7[B2]'}
-- {pin_num: E14, pin_signal: PIO3_8/WUU0_IN23/FC6_P4/FC7_P0/CT_INP4/PWM0_A2/FLEXIO0_D16/FLEXSPI0_A_DATA0/SIM0_PD/SAI0_TX_BCLK, label: 'P3_8/TP16/U8[5]/U7[D3]'}
-- {pin_num: F14, pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, label: 'P3_4/J9[12]'}
-- {pin_num: G14, pin_signal: PIO3_5/FC7_P3/CT_INP19/PWM0_X3/FLEXIO0_D13/SIM1_IO, label: 'P3_5/J9[11]'}
-- {pin_num: J10, pin_signal: VSS12, label: GND}
-- {pin_num: L14, pin_signal: PIO5_8/TRIG_OUT7/TAMPER6/ADC1_B16, label: 'P5_8/U9[19]/J9[31]'}
-- {pin_num: M14, pin_signal: PIO5_9/TAMPER7/ADC1_B17, label: 'P5_9/J9[29]'}
-- {pin_num: N14, pin_signal: VDD_SYS, label: VDD_SYS}
-- {pin_num: T16, pin_signal: VDD4, label: GND}
-- {pin_num: R14, pin_signal: USB1_DM, label: 'MCX_USB1_DM/L13[2]'}
-- {pin_num: T14, pin_signal: USB0_DM/WUU0_IN28, label: TP2}
-- {pin_num: U14, pin_signal: USB1_VBUS, label: MCX_USB1_VBUS}
-- {pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1, label: 'P0_3/J23[8]/D16[3]/SJ17[1]'}
-- {pin_num: C15, pin_signal: PIO3_1/TRIG_IN1/FC6_P0/FC7_P6/CT_INP17/PWM0_B0/FLEXIO0_D9/FLEXSPI0_A_SS1_b/FREQME_CLK_OUT0, label: P3_1/TP31}
-- {pin_num: D15, pin_signal: PIO3_2/FC7_P0/CT4_MAT0/PWM0_X0/FLEXIO0_D10/SIM1_PD, label: 'P3_2/J9[20]/J7[8]'}
-- {pin_num: F15, pin_signal: PIO3_9/FC6_P5/FC7_P2/CT_INP5/PWM0_B2/FLEXIO0_D17/FLEXSPI0_A_DATA1/SIM0_RST/SAI0_TX_FS, label: 'P3_9/TP15/U8[2]/U7[D2]'}
-- {pin_num: H15, pin_signal: PIO3_15/FC8_P1/CT_INP7/PWM1_B1/FLEXIO0_D23/FLEXSPI0_A_DATA7/SAI0_RX_FS, label: 'P3_15/TP9/U7[E1]'}
-- {pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK, label: 'P3_16/SJ11[1]'}
-- {pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS, label: 'P3_17/J1[11]/SJ10[3]'}
-- {pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1, label: 'P3_23/J6[3]'}
-- {pin_num: P15, pin_signal: VDD_LDO_SYS/VOUT_SYS, label: VDD_LDO_SYS_IN}
-- {pin_num: R15, pin_signal: VDD_DCDC, label: VDD_DCDC}
-- {pin_num: T15, pin_signal: USB0_DP/WUU0_IN29, label: TP3}
-- {pin_num: A16, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, label: 'P0_1/SWCLK/J23[4]/D16[5]/J22[2]', identifier: DEBUG_SWD_SWDCLK}
-- {pin_num: B16, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, label: 'P0_2/SWO/J23[6]/D16[4]', identifier: DEBUG_SWD_SWO}
-- {pin_num: D16, pin_signal: PIO3_3/FC7_P1/CT4_MAT1/PWM0_X1/FLEXIO0_D11/SIM1_RST, label: 'P3_3/J9[19]/SJ12[1]'}
-- {pin_num: F16, pin_signal: PIO3_11/WUU0_IN24/FC6_P3/FC7_P5/CT1_MAT1/PWM0_B3/FLEXIO0_D19/FLEXSPI0_A_DATA3/SIM0_IO/SAI0_RXD0, label: 'P3_11/TP14/U8[7]/U7[D4]'}
-- {pin_num: G16, pin_signal: PIO3_12/FC7_P4/FC6_P4/CT1_MAT2/PWM1_A0/FLEXIO0_D20/FLEXSPI0_A_DATA4/SAI0_RXD1, label: 'P3_12/TP17/U7[D5]'}
-- {pin_num: H16, pin_signal: PIO3_13/FC7_P5/FC6_P5/CT1_MAT3/PWM1_B0/FLEXIO0_D21/FLEXSPI0_A_DATA5/SAI0_TXD1, label: 'P3_13/TP11/U7[E3]'}
-- {pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK, label: 'P3_18/J1[9]'}
-- {pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0, label: 'P3_21/J6[4]/J1[15]'}
-- {pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1, label: 'P3_22/J6[5]'}
-- {pin_num: P16, pin_signal: VSS_DCDC, label: GND}
-- {pin_num: U16, pin_signal: PIO5_0/TRIG_IN10/LPTMR0_ALT2/EXTAL32K/ADC1_B8, label: 'P5_0/EXTAL32K/Y2[2]'}
-- {pin_num: A17, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, label: 'P0_0/SWDIO/J23[2]/D16[6]', identifier: DEBUG_SWD_SWDIO}
-- {pin_num: B17, pin_signal: PIO3_0/WUU0_IN22/TRIG_IN0/FC7_P3/CT_INP16/PWM0_A0/FLEXIO0_D8/FLEXSPI0_A_SS0_b, label: 'P3_0/TP12/U8[1]/U7[C2]/U7[A3]'}
-- {pin_num: D17, pin_signal: PIO3_6/CLKOUT/FC6_P1/CT4_MAT2/PWM0_A1/FLEXIO0_D14/FLEXSPI0_A_DQS/SIM1_VCCEN/SAI1_MCLK/FREQME_CLK_OUT1, label: 'P3_6/TP8/U7[C3]'}
-- {pin_num: F17, pin_signal: PIO3_10/FC6_P2/FC7_P4/CT1_MAT0/PWM0_A3/FLEXIO0_D18/FLEXSPI0_A_DATA2/SIM0_CLK/SAI0_TXD0, label: 'P3_10/TP13/U8[3]/U7[C4]'}
-- {pin_num: H17, pin_signal: PIO3_14/WUU0_IN25/FC8_P0/CT_INP6/PWM1_A1/FLEXIO0_D22/FLEXSPI0_A_DATA6/SAI0_RX_BCLK, label: 'P3_14/TP10/U7[E2]'}
-- {pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS, label: 'P3_19/J5[1]/J1[13]'}
-- {pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0, label: 'P3_20/J6[6]/J1[5]'}
-- {pin_num: P17, pin_signal: DCDC_LX, label: DCDC_LX}
-- {pin_num: T17, pin_signal: VDD_BAT, label: 'VDD_BAT/J27[2]'}
-- {pin_num: U17, pin_signal: PIO5_1/TRIG_OUT6/LPTMR1_ALT2/XTAL32K/ADC1_B9, label: 'P5_1/XTAL32K/Y2[1]'}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "fsl_gpio.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitDEBUG_UARTPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitDEBUG_UARTPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitDEBUG_UARTPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitDEBUG_UARTPins(void)
-{
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-    const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
-                                             kPORT_PullDisable,
-                                             /* Low internal pull resistor value is selected. */
-                                             kPORT_LowPullResistor,
-                                             /* Fast slew rate is configured */
-                                             kPORT_FastSlewRate,
-                                             /* Passive input filter is disabled */
-                                             kPORT_PassiveFilterDisable,
-                                             /* Open drain output is disabled */
-                                             kPORT_OpenDrainDisable,
-                                             /* Low drive strength is configured */
-                                             kPORT_LowDriveStrength,
-                                             /* Pin is configured as FC4_P0 */
-                                             kPORT_MuxAlt2,
-                                             /* Digital input enabled */
-                                             kPORT_InputBufferEnable,
-                                             /* Digital input is not inverted */
-                                             kPORT_InputNormal,
-                                             /* Pin Control Register fields [15:0] are not locked */
-                                             kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
-
-    const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
-                                             kPORT_PullDisable,
-                                             /* Low internal pull resistor value is selected. */
-                                             kPORT_LowPullResistor,
-                                             /* Fast slew rate is configured */
-                                             kPORT_FastSlewRate,
-                                             /* Passive input filter is disabled */
-                                             kPORT_PassiveFilterDisable,
-                                             /* Open drain output is disabled */
-                                             kPORT_OpenDrainDisable,
-                                             /* Low drive strength is configured */
-                                             kPORT_LowDriveStrength,
-                                             /* Pin is configured as FC4_P1 */
-                                             kPORT_MuxAlt2,
-                                             /* Digital input enabled */
-                                             kPORT_InputBufferEnable,
-                                             /* Digital input is not inverted */
-                                             kPORT_InputNormal,
-                                             /* Pin Control Register fields [15:0] are not locked */
-                                             kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitSWD_DEBUGPins:
-- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A16, peripheral: SWD, signal: SWCLK, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down,
-    pull_enable: enable, input_buffer: enable, invert_input: normal}
-  - {pin_num: A17, peripheral: SWD, signal: SWDIO, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high, pull_select: up,
-    pull_enable: enable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B16, peripheral: SWD, signal: SWO, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, drive_strength: high,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitSWD_DEBUGPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitSWD_DEBUGPins(void)
-{
-    /* Enables the clock for PORT0 controller: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */
-                                               kPORT_PullUp,
-                                               /* Low internal pull resistor value is selected. */
-                                               kPORT_LowPullResistor,
-                                               /* Fast slew rate is configured */
-                                               kPORT_FastSlewRate,
-                                               /* Passive input filter is disabled */
-                                               kPORT_PassiveFilterDisable,
-                                               /* Open drain output is disabled */
-                                               kPORT_OpenDrainDisable,
-                                               /* High drive strength is configured */
-                                               kPORT_HighDriveStrength,
-                                               /* Pin is configured as SWDIO */
-                                               kPORT_MuxAlt1,
-                                               /* Digital input enabled */
-                                               kPORT_InputBufferEnable,
-                                               /* Digital input is not inverted */
-                                               kPORT_InputNormal,
-                                               /* Pin Control Register fields [15:0] are not locked */
-                                               kPORT_UnlockRegister};
-    /* PORT0_0 (pin A17) is configured as SWDIO */
-    PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO);
-
-    const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */
-                                                kPORT_PullDown,
-                                                /* Low internal pull resistor value is selected. */
-                                                kPORT_LowPullResistor,
-                                                /* Fast slew rate is configured */
-                                                kPORT_FastSlewRate,
-                                                /* Passive input filter is disabled */
-                                                kPORT_PassiveFilterDisable,
-                                                /* Open drain output is disabled */
-                                                kPORT_OpenDrainDisable,
-                                                /* Low drive strength is configured */
-                                                kPORT_LowDriveStrength,
-                                                /* Pin is configured as SWCLK */
-                                                kPORT_MuxAlt1,
-                                                /* Digital input enabled */
-                                                kPORT_InputBufferEnable,
-                                                /* Digital input is not inverted */
-                                                kPORT_InputNormal,
-                                                /* Pin Control Register fields [15:0] are not locked */
-                                                kPORT_UnlockRegister};
-    /* PORT0_1 (pin A16) is configured as SWCLK */
-    PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK);
-
-    const port_pin_config_t DEBUG_SWD_SWO = {/* Internal pull-up/down resistor is disabled */
-                                             kPORT_PullDisable,
-                                             /* Low internal pull resistor value is selected. */
-                                             kPORT_LowPullResistor,
-                                             /* Fast slew rate is configured */
-                                             kPORT_FastSlewRate,
-                                             /* Passive input filter is disabled */
-                                             kPORT_PassiveFilterDisable,
-                                             /* Open drain output is disabled */
-                                             kPORT_OpenDrainDisable,
-                                             /* High drive strength is configured */
-                                             kPORT_HighDriveStrength,
-                                             /* Pin is configured as SWO */
-                                             kPORT_MuxAlt1,
-                                             /* Digital input enabled */
-                                             kPORT_InputBufferEnable,
-                                             /* Digital input is not inverted */
-                                             kPORT_InputNormal,
-                                             /* Pin Control Register fields [15:0] are not locked */
-                                             kPORT_UnlockRegister};
-    /* PORT0_2 (pin B16) is configured as SWO */
-    PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, &DEBUG_SWD_SWO);
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitLEDsPins:
-- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: C4, peripheral: GPIO1, signal: 'GPIO, 2', pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0,
-    direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B12, peripheral: GPIO0, signal: 'GPIO, 10', pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, direction: OUTPUT, slew_rate: fast, open_drain: disable,
-    drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: E10, peripheral: GPIO0, signal: 'GPIO, 27', pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitLEDsPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitLEDsPins(void)
-{
-    /* Enables the clock for GPIO0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Gpio0);
-    /* Enables the clock for GPIO1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Gpio1);
-    /* Enables the clock for PORT0 controller: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-    gpio_pin_config_t LED_RED_config = {
-        .pinDirection = kGPIO_DigitalOutput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_10 (pin B12)  */
-    GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
-
-    gpio_pin_config_t LED_GREEN_config = {
-        .pinDirection = kGPIO_DigitalOutput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_27 (pin E10)  */
-    GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
-
-    gpio_pin_config_t LED_BLUE_config = {
-        .pinDirection = kGPIO_DigitalOutput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO1_2 (pin C4)  */
-    GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
-
-    const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
-                                       kPORT_PullDisable,
-                                       /* Low internal pull resistor value is selected. */
-                                       kPORT_LowPullResistor,
-                                       /* Fast slew rate is configured */
-                                       kPORT_FastSlewRate,
-                                       /* Passive input filter is disabled */
-                                       kPORT_PassiveFilterDisable,
-                                       /* Open drain output is disabled */
-                                       kPORT_OpenDrainDisable,
-                                       /* Low drive strength is configured */
-                                       kPORT_LowDriveStrength,
-                                       /* Pin is configured as PIO0_10 */
-                                       kPORT_MuxAlt0,
-                                       /* Digital input enabled */
-                                       kPORT_InputBufferEnable,
-                                       /* Digital input is not inverted */
-                                       kPORT_InputNormal,
-                                       /* Pin Control Register fields [15:0] are not locked */
-                                       kPORT_UnlockRegister};
-    /* PORT0_10 (pin B12) is configured as PIO0_10 */
-    PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED);
-
-    const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
-                                         kPORT_PullDisable,
-                                         /* Low internal pull resistor value is selected. */
-                                         kPORT_LowPullResistor,
-                                         /* Fast slew rate is configured */
-                                         kPORT_FastSlewRate,
-                                         /* Passive input filter is disabled */
-                                         kPORT_PassiveFilterDisable,
-                                         /* Open drain output is disabled */
-                                         kPORT_OpenDrainDisable,
-                                         /* Low drive strength is configured */
-                                         kPORT_LowDriveStrength,
-                                         /* Pin is configured as PIO0_27 */
-                                         kPORT_MuxAlt0,
-                                         /* Digital input enabled */
-                                         kPORT_InputBufferEnable,
-                                         /* Digital input is not inverted */
-                                         kPORT_InputNormal,
-                                         /* Pin Control Register fields [15:0] are not locked */
-                                         kPORT_UnlockRegister};
-    /* PORT0_27 (pin E10) is configured as PIO0_27 */
-    PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN);
-
-    const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
-                                        kPORT_PullDisable,
-                                        /* Low internal pull resistor value is selected. */
-                                        kPORT_LowPullResistor,
-                                        /* Fast slew rate is configured */
-                                        kPORT_FastSlewRate,
-                                        /* Passive input filter is disabled */
-                                        kPORT_PassiveFilterDisable,
-                                        /* Open drain output is disabled */
-                                        kPORT_OpenDrainDisable,
-                                        /* Low drive strength is configured */
-                                        kPORT_LowDriveStrength,
-                                        /* Pin is configured as PIO1_2 */
-                                        kPORT_MuxAlt0,
-                                        /* Digital input enabled */
-                                        kPORT_InputBufferEnable,
-                                        /* Digital input is not inverted */
-                                        kPORT_InputNormal,
-                                        /* Pin Control Register fields [15:0] are not locked */
-                                        kPORT_UnlockRegister};
-    /* PORT1_2 (pin C4) is configured as PIO1_2 */
-    PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE);
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitBUTTONsPins:
-- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: C14, peripheral: GPIO0, signal: 'GPIO, 6', pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, direction: INPUT,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBUTTONsPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBUTTONsPins(void)
-{
-    /* Enables the clock for GPIO0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Gpio0);
-    /* Enables the clock for PORT0 controller: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    gpio_pin_config_t SW3_config = {
-        .pinDirection = kGPIO_DigitalInput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_6 (pin C14)  */
-    GPIO_PinInit(BOARD_INITBUTTONSPINS_SW3_GPIO, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3_config);
-
-    gpio_pin_config_t SW2_config = {
-        .pinDirection = kGPIO_DigitalInput,
-        .outputLogic = 0U
-    };
-    /* Initialize GPIO functionality on pin PIO0_23 (pin B7)  */
-    GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config);
-
-    const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
-                                   kPORT_PullDisable,
-                                   /* Low internal pull resistor value is selected. */
-                                   kPORT_LowPullResistor,
-                                   /* Fast slew rate is configured */
-                                   kPORT_FastSlewRate,
-                                   /* Passive input filter is disabled */
-                                   kPORT_PassiveFilterDisable,
-                                   /* Open drain output is disabled */
-                                   kPORT_OpenDrainDisable,
-                                   /* Low drive strength is configured */
-                                   kPORT_LowDriveStrength,
-                                   /* Pin is configured as PIO0_23 */
-                                   kPORT_MuxAlt0,
-                                   /* Digital input enabled */
-                                   kPORT_InputBufferEnable,
-                                   /* Digital input is not inverted */
-                                   kPORT_InputNormal,
-                                   /* Pin Control Register fields [15:0] are not locked */
-                                   kPORT_UnlockRegister};
-    /* PORT0_23 (pin B7) is configured as PIO0_23 */
-    PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2);
-
-    const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
-                                   kPORT_PullUp,
-                                   /* Low internal pull resistor value is selected. */
-                                   kPORT_LowPullResistor,
-                                   /* Fast slew rate is configured */
-                                   kPORT_FastSlewRate,
-                                   /* Passive input filter is disabled */
-                                   kPORT_PassiveFilterDisable,
-                                   /* Open drain output is disabled */
-                                   kPORT_OpenDrainDisable,
-                                   /* Low drive strength is configured */
-                                   kPORT_LowDriveStrength,
-                                   /* Pin is configured as PIO0_6 */
-                                   kPORT_MuxAlt0,
-                                   /* Digital input enabled */
-                                   kPORT_InputBufferEnable,
-                                   /* Digital input is not inverted */
-                                   kPORT_InputNormal,
-                                   /* Pin Control Register fields [15:0] are not locked */
-                                   kPORT_UnlockRegister};
-    /* PORT0_6 (pin C14) is configured as PIO0_6 */
-    PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/board/pin_mux.h

@@ -1,184 +0,0 @@
-/*
- * Copyright 2022-2023 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*! @name PORT1_8 (coord A1), P1_8/J9[32]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT1               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 8U                   /*!<@brief PORT pin number */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 8U)      /*!<@brief PORT pin mask */
-                                                                        /* @} */
-
-/*! @name PORT1_9 (coord B1), P1_9/J9[30]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT1               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 9U                   /*!<@brief PORT pin number */
-#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 9U)      /*!<@brief PORT pin mask */
-                                                                        /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitDEBUG_UARTPins(void);
-
-/*! @name PORT0_1 (coord A16), P0_1/SWCLK/J23[4]/D16[5]/J22[2]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U                   /*!<@brief PORT pin number */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U)      /*!<@brief PORT pin mask */
-                                                                          /* @} */
-
-/*! @name PORT0_0 (coord A17), P0_0/SWDIO/J23[2]/D16[6]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U                   /*!<@brief PORT pin number */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U)      /*!<@brief PORT pin mask */
-                                                                         /* @} */
-
-/*! @name PORT0_2 (coord B16), P0_2/SWO/J23[6]/D16[4]
-  @{ */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 2U                   /*!<@brief PORT pin number */
-#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 2U)      /*!<@brief PORT pin mask */
-                                                                       /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitSWD_DEBUGPins(void);
-
-/*! @name PORT1_2 (coord C4), P1_2/SJ4[1]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO1               /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 2U              /*!<@brief GPIO pin number */
-#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT1               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_BLUE_PIN 2U                   /*!<@brief PORT pin number */
-#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 2U)      /*!<@brief PORT pin mask */
-                                                             /* @} */
-
-/*! @name PORT0_10 (coord B12), P0_10/SJ5[1]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO0                /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 10U              /*!<@brief GPIO pin number */
-#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 10U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITLEDSPINS_LED_RED_PORT PORT0                /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_RED_PIN 10U                   /*!<@brief PORT pin number */
-#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 10U)      /*!<@brief PORT pin mask */
-                                                             /* @} */
-
-/*! @name PORT0_27 (coord E10), P0_27/SJ6[1]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO0                /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 27U              /*!<@brief GPIO pin number */
-#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 27U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT0                /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITLEDSPINS_LED_GREEN_PIN 27U                   /*!<@brief PORT pin number */
-#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 27U)      /*!<@brief PORT pin mask */
-                                                               /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitLEDsPins(void);
-
-/*! @name PORT0_6 (coord C14), P0_6/J23[7]/SW3[3]/SW3[4]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO0               /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 6U              /*!<@brief GPIO pin number */
-#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITBUTTONSPINS_SW3_PORT PORT0               /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW3_PIN 6U                   /*!<@brief PORT pin number */
-#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 6U)      /*!<@brief PORT pin mask */
-                                                           /* @} */
-
-/*! @name PORT0_23 (coord B7), P0_23/SJ9[1]/SW2[3]/SW2[4]
-  @{ */
-
-/* Symbols to be used with GPIO driver */
-#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIO0                /*!<@brief GPIO peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN 23U              /*!<@brief GPIO pin number */
-#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN_MASK (1U << 23U) /*!<@brief GPIO pin mask */
-
-/* Symbols to be used with PORT driver */
-#define BOARD_INITBUTTONSPINS_SW2_PORT PORT0                /*!<@brief PORT peripheral base pointer */
-#define BOARD_INITBUTTONSPINS_SW2_PIN 23U                   /*!<@brief PORT pin number */
-#define BOARD_INITBUTTONSPINS_SW2_PIN_MASK (1U << 23U)      /*!<@brief PORT pin mask */
-                                                            /* @} */
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitBUTTONsPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/device/system_MCXN947_cm33_core0.c

@@ -1,130 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          MCXN947VDF_cm33_core0
-**                          MCXN947VNL_cm33_core0
-**
-**     Compilers:           GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**                          Keil ARM C/C++ Compiler
-**                          MCUXpresso Compiler
-**
-**     Reference manual:    MCXNx4x Reference Manual
-**     Version:             rev. 2.0, 2023-02-01
-**     Build:               b231219
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
-**     SPDX-License-Identifier: BSD-3-Clause
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-**     Revisions:
-**     - rev. 1.0 (2022-10-01)
-**         Initial version
-**     - rev. 2.0 (2023-02-01)
-**         Initial version based on Rev. 2 Draft B
-**
-** ###################################################################
-*/
-
-/*!
- * @file MCXN947_cm33_core0
- * @version 2.0
- * @date 2023-02-01
- * @brief Device specific configuration file for MCXN947_cm33_core0
- *        (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "fsl_device_registers.h"
-
-
-
-
-
-
-/* ----------------------------------------------------------------------------
-   -- Core clock
-   ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
-   -- SystemInit()
-   ---------------------------------------------------------------------------- */
-
-__attribute__ ((weak)) void SystemInit (void) {
-#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
-  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
-  #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
-
-
-  SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
-#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-  SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
-
-  SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */
-
-  SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */
-
-#if defined(__MCUXPRESSO)
-    extern void(*const g_pfnVectors[]) (void);
-    SCB->VTOR = (uint32_t) &g_pfnVectors;
-#else
-    extern void *__Vectors;
-    SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-    /* enable the flash cache LPCAC */
-    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
-
-    /* Disable aGDET trigger the CHIP_RESET */
-    ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
-    ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
-    /* Disable aGDET interrupt and reset */
-    SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
-    SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
-    SPC0->GLITCH_DETECT_SC = 0x3C;
-    SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
-
-    /* Disable dGDET trigger the CHIP_RESET */
-    ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
-    ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
-    GDET0->GDET_ENABLE1 = 0;
-    GDET1->GDET_ENABLE1 = 0;
-
-  SystemInitHook();
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemCoreClockUpdate()
-   ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-
-
-
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemInitHook()
-   ---------------------------------------------------------------------------- */
-
-__attribute__ ((weak)) void SystemInitHook (void) {
-  /* Void implementation of the weak function. */
-}

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/drivers/fsl_gpio.c

@@ -1,440 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019, 2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_gpio.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.gpio"
-#endif
-
-#if defined(GPIO_RSTS)
-#define GPIO_RESETS_ARRAY GPIO_RSTS
-#endif
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
-static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
-#endif
-
-#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
-
-#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Array to map FGPIO instance number to clock name. */
-static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
-
-#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
-
-#if defined(GPIO_RESETS_ARRAY)
-/* Reset array */
-static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
-#endif
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * @brief Gets the GPIO instance according to the GPIO base
- *
- * @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
- * @retval GPIO instance
- */
-static uint32_t GPIO_GetInstance(GPIO_Type *base);
-#endif
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
-static uint32_t GPIO_GetInstance(GPIO_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
-    {
-        if (s_gpioBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_gpioBases));
-
-    return instance;
-}
-#endif
-/*!
- * brief Initializes a GPIO pin used by the board.
- *
- * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
- * Then, call the GPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration.
- * code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * endcode
- *
- * param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param pin    GPIO port pin number
- * param config GPIO pin configuration pointer
- */
-void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
-{
-    assert(NULL != config);
-
-#if defined(GPIO_RESETS_ARRAY)
-    RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
-#endif
-
-    if (config->pinDirection == kGPIO_DigitalInput)
-    {
-        base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
-    }
-    else
-    {
-        GPIO_PinWrite(base, pin, config->outputLogic);
-        base->PDDR |= GPIO_FIT_REG((1UL << pin));
-    }
-}
-
-#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
-void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
-{
-    info->feature = (uint16_t)base->VERID;
-    info->minor   = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT);
-    info->major   = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * brief Reads the GPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
-{
-    uint8_t instance;
-    PORT_Type *portBase;
-    instance = (uint8_t)GPIO_GetInstance(base);
-    portBase = s_portBases[instance];
-    return portBase->ISFR;
-}
-#else
-/*!
- * brief Read the GPIO interrupt status flags.
- *
- * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * return The current GPIO's interrupt status flag.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)
-{
-    return base->ISFR[0];
-}
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
- * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- *
- * return The current GPIO's interrupt status flag based on the selected interrupt channel.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)
-{
-    assert(channel < 2U);
-    return base->ISFR[channel];
-}
-#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
-/*!
- * brief Read individual pin's interrupt status flag.
- *
- * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
- * param pin GPIO specific pin number.
- * return The current selected pin's interrupt status flag.
- */
-uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
-{
-    return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT);
-}
-#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
-
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * brief Clears multiple GPIO pin interrupt status flags.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param mask GPIO pin number macro
- */
-void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
-{
-    uint8_t instance;
-    PORT_Type *portBase;
-    instance       = (uint8_t)GPIO_GetInstance(base);
-    portBase       = s_portBases[instance];
-    portBase->ISFR = mask;
-}
-#else
-/*!
- * brief Clears GPIO pin interrupt status flags.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param mask GPIO pin number macro
- */
-void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)
-{
-    base->ISFR[0] = GPIO_FIT_REG(mask);
-}
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param mask GPIO pin number macro
- * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- */
-void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)
-{
-    assert(channel < 2U);
-    base->ISFR[channel] = GPIO_FIT_REG(mask);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
-/*!
- * brief Clear GPIO individual pin's interrupt status flag.
- *
- * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
- * param pin GPIO specific pin number.
- */
-void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)
-{
-    base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U));
-}
-#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
-
-#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
- * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
- * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
- * endian data convention.
- *
- * param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * param attribute GPIO checker attribute
- */
-void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
-{
-#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
-    base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT);
-#else
-    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
-                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
-#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */
-}
-#endif
-
-#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
-#endif
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * @brief Gets the FGPIO instance according to the GPIO base
- *
- * @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
- * @retval FGPIO instance
- */
-static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
-#endif
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
-    {
-        if (s_fgpioBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_fgpioBases));
-
-    return instance;
-}
-#endif
-#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
-/*!
- * brief Initializes the FGPIO peripheral.
- *
- * This function ungates the FGPIO clock.
- *
- * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- */
-void FGPIO_PortInit(FGPIO_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Ungate FGPIO periphral clock */
-    CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
-
-/*!
- * brief Initializes a FGPIO pin used by the board.
- *
- * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
- * Then, call the FGPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration:
- * code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * endcode
- *
- * param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * param pin    FGPIO port pin number
- * param config FGPIO pin configuration pointer
- */
-void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
-{
-    assert(NULL != config);
-
-    if (config->pinDirection == kGPIO_DigitalInput)
-    {
-        base->PDDR &= ~(1UL << pin);
-    }
-    else
-    {
-        FGPIO_PinWrite(base, pin, config->outputLogic);
-        base->PDDR |= (1UL << pin);
-    }
-}
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * brief Reads the FGPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level-sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base)
-{
-    uint8_t instance;
-    instance = (uint8_t)FGPIO_GetInstance(base);
-    PORT_Type *portBase;
-    portBase = s_portBases[instance];
-    return portBase->ISFR;
-}
-
-/*!
- * brief Clears the multiple FGPIO pin interrupt status flag.
- *
- * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * param mask FGPIO pin number macro
- */
-void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask)
-{
-    uint8_t instance;
-    instance = (uint8_t)FGPIO_GetInstance(base);
-    PORT_Type *portBase;
-    portBase       = s_portBases[instance];
-    portBase->ISFR = mask;
-}
-#endif
-#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
- * words. Each 32-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
- * bytes in the GACR follow a standard little endian
- * data convention.
- *
- * param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * param attribute FGPIO checker attribute
- */
-void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
-{
-    base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) |
-                 ((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT);
-}
-#endif
-
-#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/drivers/fsl_gpio.h

@@ -1,799 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FSL_GPIO_H_
-#define FSL_GPIO_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup gpio
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief GPIO driver version. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
-/*@}*/
-
-#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
-#define GPIO_FIT_REG(value) \
-    ((uint8_t)(value)) /*!< For some platforms with 8-bit register width, cast the type to uint8_t */
-#else
-#define GPIO_FIT_REG(value) ((uint32_t)(value))
-#endif /*FSL_FEATURE_GPIO_REGISTERS_WIDTH*/
-
-/*! @brief GPIO direction definition */
-typedef enum _gpio_pin_direction
-{
-    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
-    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
-} gpio_pin_direction_t;
-
-#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
-/*! @brief GPIO checker attribute */
-typedef enum _gpio_checker_attribute
-{
-    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
-        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
-        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
-        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
-        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
-        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
-        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
-    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
-        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
-    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
-        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
-    kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
-} gpio_checker_attribute_t;
-#endif
-
-/*!
- * @brief The GPIO pin configuration structure.
- *
- * Each pin can only be configured as either an output pin or an input pin at a time.
- * If configured as an input pin, leave the outputConfig unused.
- * Note that in some use cases, the corresponding port property should be configured in advance
- *        with the PORT_SetPinConfig().
- */
-typedef struct _gpio_pin_config
-{
-    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
-    /* Output configurations; ignore if configured as an input pin */
-    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
-} gpio_pin_config_t;
-
-#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \
-     !(defined(FSL_FEATURE_SOC_PORT_COUNT))
-/*! @brief Configures the interrupt generation condition. */
-typedef enum _gpio_interrupt_config
-{
-    kGPIO_InterruptStatusFlagDisabled   = 0x0U,  /*!< Interrupt status flag is disabled. */
-    kGPIO_DMARisingEdge                 = 0x1U,  /*!< ISF flag and DMA request on rising edge. */
-    kGPIO_DMAFallingEdge                = 0x2U,  /*!< ISF flag and DMA request on falling edge. */
-    kGPIO_DMAEitherEdge                 = 0x3U,  /*!< ISF flag and DMA request on either edge. */
-    kGPIO_FlagRisingEdge                = 0x05U, /*!< Flag sets on rising edge. */
-    kGPIO_FlagFallingEdge               = 0x06U, /*!< Flag sets on falling edge. */
-    kGPIO_FlagEitherEdge                = 0x07U, /*!< Flag sets on either edge. */
-    kGPIO_InterruptLogicZero            = 0x8U,  /*!< Interrupt when logic zero. */
-    kGPIO_InterruptRisingEdge           = 0x9U,  /*!< Interrupt on rising edge. */
-    kGPIO_InterruptFallingEdge          = 0xAU,  /*!< Interrupt on falling edge. */
-    kGPIO_InterruptEitherEdge           = 0xBU,  /*!< Interrupt on either edge. */
-    kGPIO_InterruptLogicOne             = 0xCU,  /*!< Interrupt when logic one. */
-    kGPIO_ActiveHighTriggerOutputEnable = 0xDU,  /*!< Enable active high-trigger output. */
-    kGPIO_ActiveLowTriggerOutputEnable  = 0xEU,  /*!< Enable active low-trigger output. */
-} gpio_interrupt_config_t;
-#endif
-
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*! @brief Configures the selection of interrupt/DMA request/trigger output. */
-typedef enum _gpio_interrupt_selection
-{
-    kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
-    kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
-} gpio_interrupt_selection_t;
-#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
-
-#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
-/*! @brief GPIO version information. */
-typedef struct _gpio_version_info
-{
-    uint16_t feature; /*!< Feature Specification Number. */
-    uint8_t minor;    /*!< Minor Version Number. */
-    uint8_t major;    /*!< Major Version Number. */
-} gpio_version_info_t;
-#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
-
-#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
-/*! @brief GPIO pin and interrupt control. */
-typedef enum
-{
-    kGPIO_PinControlNonSecure          = 0x01U, /*!< Pin Control Non-Secure. */
-    kGPIO_InterruptControlNonSecure    = 0x02U, /*!< Interrupt Control Non-Secure. */
-    kGPIO_PinControlNonPrivilege       = 0x04U, /*!< Pin Control Non-Privilege. */
-    kGPIO_InterruptControlNonPrivilege = 0x08U, /*!< Interrupt Control Non-Privilege. */
-} gpio_pin_interrupt_control_t;
-#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
-
-/*! @} */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @addtogroup gpio_driver
- * @{
- */
-
-/*! @name GPIO Configuration */
-/*@{*/
-
-/*!
- * @brief Initializes a GPIO pin used by the board.
- *
- * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
- * Then, call the GPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration.
- * @code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * @endcode
- *
- * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin    GPIO port pin number
- * @param config GPIO pin configuration pointer
- */
-void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
-
-#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
-/*!
- * @brief Get GPIO version information.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param info GPIO version information
- */
-void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info);
-#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
-
-#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
-/*!
- * @brief lock or unlock secure privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask pin or interrupt macro
- */
-static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)
-{
-    base->LOCK |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Enable Pin Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNS |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Pin Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNS &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Enable Pin Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNP |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Pin Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->PCNP &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Enable Interrupt Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNS |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Interrupt Control Non-Secure.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNS &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Enable Interrupt Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNP |= GPIO_FIT_REG(mask);
-}
-
-/*!
- * @brief Disable Interrupt Control Non-Privilege.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
-{
-    base->ICNP &= GPIO_FIT_REG(~mask);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
-
-#if defined(FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL
-/*!
- * @brief Enable port input.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)
-{
-    base->PIDR &= GPIO_FIT_REG(~mask);
-}
-
-/*!
- * @brief Disable port input.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
-{
-    base->PIDR |= GPIO_FIT_REG(mask);
-}
-#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
-
-/*@}*/
-
-/*! @name GPIO Output Operations */
-/*@{*/
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
- *
- * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin number
- * @param output  GPIO pin output logic level.
- *        - 0: corresponding pin output low-logic level.
- *        - 1: corresponding pin output high-logic level.
- */
-static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    if (output == 0U)
-    {
-        base->PCOR = GPIO_FIT_REG(1UL << pin);
-    }
-    else
-    {
-        base->PSOR = GPIO_FIT_REG(1UL << pin);
-    }
-#else
-    if (output == 0U)
-    {
-        base->PDOR |= GPIO_FIT_REG(1UL << pin);
-    }
-    else
-    {
-        base->PDOR &= ~GPIO_FIT_REG(1UL << pin);
-    }
-#endif
-}
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 1.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    base->PSOR = GPIO_FIT_REG(mask);
-#else
-    base->PDOR |= GPIO_FIT_REG(mask);
-#endif
-}
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 0.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    base->PCOR = GPIO_FIT_REG(mask);
-#else
-    base->PDOR &= ~GPIO_FIT_REG(mask);
-#endif
-}
-
-/*!
- * @brief Reverses the current output logic of the multiple GPIO pins.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
-{
-#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
-    base->PTOR = GPIO_FIT_REG(mask);
-#else
-    base->PDOR ^= GPIO_FIT_REG(mask);
-#endif
-}
-
-/*@}*/
-
-/*! @name GPIO Input Operations */
-/*@{*/
-
-/*!
- * @brief Reads the current input value of the GPIO port.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin number
- * @retval GPIO port input value
- *        - 0: corresponding pin input low-logic level.
- *        - 1: corresponding pin input high-logic level.
- */
-static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
-{
-    return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
-}
-
-/*@}*/
-
-/*! @name GPIO Interrupt */
-/*@{*/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-/*!
- * @brief Reads the GPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base);
-
-/*!
- * @brief Clears multiple GPIO pin interrupt status flags.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask);
-#else
-/*!
- * @brief Configures the gpio pin interrupt/DMA request.
- *
- * @param base    GPIO peripheral base pointer.
- * @param pin     GPIO pin number.
- * @param config  GPIO pin interrupt configuration.
- *        - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
- *        - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- *        - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- *        - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- *        - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- *        - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- *        - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- *        - #kGPIO_InterruptLogicZero  : Interrupt when logic zero.
- *        - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- *        - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- *        - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
- *        - #kGPIO_InterruptLogicOne   : Interrupt when logic one.
- *        - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- *        - #kGPIO_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
- */
-static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)
-{
-    assert(base);
-
-    base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config));
-}
-
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * @brief Configures the gpio pin interrupt/DMA request/trigger output channel selection.
- *
- * @param base    GPIO peripheral base pointer.
- * @param pin     GPIO pin number.
- * @param selection  GPIO pin interrupt output selection.
- *        - #kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
- *        - #kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.
- */
-static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)
-{
-    assert(base);
-
-    base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQS_MASK) | GPIO_ICR_IRQS(selection));
-}
-#endif
-/*!
- * @brief Read the GPIO interrupt status flags.
- *
- * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * @return The current GPIO's interrupt status flag.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base);
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * @brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
- *
- * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
- * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- * @return The current GPIO's interrupt status flag based on the selected interrupt channel.
- *         '1' means the related pin's flag is set, '0' means the related pin's flag not set.
- *          For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
- */
-uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel);
-#endif
-/*!
- * @brief Read individual pin's interrupt status flag.
- *
- * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
- * @param pin GPIO specific pin number.
- * @return The current selected pin's interrupt status flag.
- */
-uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin);
-
-/*!
- * @brief Clears GPIO pin interrupt status flags.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- */
-void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask);
-#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
-/*!
- * @brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pin number macro
- * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
- */
-void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel);
-#endif
-/*!
- * @brief Clear GPIO individual pin's interrupt status flag.
- *
- * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
- * @param pin GPIO specific pin number.
- */
-void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin);
-
-/*!
- * @brief Reads the GPIO DMA request flags.
- *        The corresponding flag will be cleared automatically at the completion of the requested
- *        DMA transfer
- */
-static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base)
-{
-    assert(base);
-    return (base->ISFR[1]);
-}
-
-/*!
- * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins.
- *
- * @param base   GPIO peripheral base pointer.
- * @param mask   GPIO pin number macro.
- * @param config  GPIO pin interrupt configuration.
- *        - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
- *        - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- *        - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- *        - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- *        - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- *        - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- *        - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- *        - #kGPIO_InterruptLogicZero  : Interrupt when logic zero.
- *        - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- *        - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- *        - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
- *        - #kGPIO_InterruptLogicOne   : Interrupt when logic one.
- *        - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- *        - #kGPIO_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
- */
-static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)
-{
-    assert(base);
-
-    if (0UL != (mask & 0xffffUL))
-    {
-        base->GICLR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
-    }
-    mask = mask >> 16U;
-    if (mask != 0UL)
-    {
-        base->GICHR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
-    }
-}
-#endif
-
-#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
- * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
- * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
- * endian data convention.
- *
- * @param base      GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
- * @param attribute GPIO checker attribute
- */
-void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
-#endif
-
-/*@}*/
-/*! @} */
-
-/*!
- * @addtogroup fgpio_driver
- * @{
- */
-
-/*
- * Introduces the FGPIO feature.
- *
- * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
- * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
- * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
- */
-
-#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
-
-/*! @name FGPIO Configuration */
-/*@{*/
-
-#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
-/*!
- * @brief Initializes the FGPIO peripheral.
- *
- * This function ungates the FGPIO clock.
- *
- * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- */
-void FGPIO_PortInit(FGPIO_Type *base);
-#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
-
-/*!
- * @brief Initializes a FGPIO pin used by the board.
- *
- * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
- * Then, call the FGPIO_PinInit() function.
- *
- * This is an example to define an input pin or an output pin configuration:
- * @code
- * Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * @endcode
- *
- * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param pin    FGPIO port pin number
- * @param config FGPIO pin configuration pointer
- */
-void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
-
-/*@}*/
-
-/*! @name FGPIO Output Operations */
-/*@{*/
-
-/*!
- * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
- *
- * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param pin     FGPIO pin number
- * @param output  FGPIOpin output logic level.
- *        - 0: corresponding pin output low-logic level.
- *        - 1: corresponding pin output high-logic level.
- */
-static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output)
-{
-    if (output == 0U)
-    {
-        base->PCOR = 1UL << pin;
-    }
-    else
-    {
-        base->PSOR = 1UL << pin;
-    }
-}
-
-/*!
- * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask)
-{
-    base->PSOR = mask;
-}
-
-/*!
- * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask)
-{
-    base->PCOR = mask;
-}
-
-/*!
- * @brief Reverses the current output logic of the multiple FGPIO pins.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
-{
-    base->PTOR = mask;
-}
-/*@}*/
-
-/*! @name FGPIO Input Operations */
-/*@{*/
-
-/*!
- * @brief Reads the current input value of the FGPIO port.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param pin  FGPIO pin number
- * @retval FGPIO port input value
- *        - 0: corresponding pin input low-logic level.
- *        - 1: corresponding pin input high-logic level.
- */
-static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
-{
-    return (((base->PDIR) >> pin) & 0x01U);
-}
-/*@}*/
-
-/*! @name FGPIO Interrupt */
-/*@{*/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
-    defined(FSL_FEATURE_SOC_PORT_COUNT)
-
-/*!
- * @brief Reads the FGPIO port interrupt status flag.
- *
- * If a pin is configured to generate the DMA request, the corresponding flag
- * is cleared automatically at the completion of the requested DMA transfer.
- * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level-sensitive interrupt that remains asserted, the flag
- * is set again immediately.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
- */
-uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base);
-
-/*!
- * @brief Clears the multiple FGPIO pin interrupt status flag.
- *
- * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param mask FGPIO pin number macro
- */
-void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
-#endif
-#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
-/*!
- * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
- * words. Each 32-bit data port includes a GACR register, which defines the byte-level
- * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
- * bytes in the GACR follow a standard little endian
- * data convention.
- *
- * @param base      FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
- * @param attribute FGPIO checker attribute
- */
-void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
-#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
-
-/*@}*/
-
-#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-
-#endif /* FSL_GPIO_H_*/

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/drivers/fsl_lpflexcomm.c

@@ -1,380 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_common.h"
-#include "fsl_lpflexcomm.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm"
-#endif
-
-/*!
- * @brief Used for conversion between `void*` and `uint32_t`.
- */
-typedef union pvoid_to_u32
-{
-    void *pvoid;
-    uint32_t u32;
-} pvoid_to_u32_t;
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*! @brief check whether lpflexcomm supports peripheral type */
-static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph);
-
-/*! @brief Changes LP_FLEXCOMM mode. */
-static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock);
-
-/*! @brief Common LPFLEXCOMM IRQhandle. */
-static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance);
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Array to map LP_FLEXCOMM instance number to base address. */
-static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS;
-
-/*! @brief Array to map LP_FLEXCOMM instance PTRS. */
-static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS;
-
-/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
-static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
-
-/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
-static void *s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
-
-/*! @brief Array to map LP_FLEXCOMM instance number to IRQ number. */
-IRQn_Type const kFlexcommIrqs[] = LP_FLEXCOMM_IRQS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief IDs of clock for each LP_FLEXCOMM module */
-static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
-/*! @brief Pointers to LP_FLEXCOMM resets for each instance. */
-static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS;
-#endif
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* check whether lpflexcomm supports peripheral type */
-static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph)
-{
-    if (periph == LP_FLEXCOMM_PERIPH_NONE)
-    {
-        return true;
-    }
-    else if (periph <= LP_FLEXCOMM_PERIPH_LPI2C)
-    {
-        return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
-    }
-    else if (periph == LP_FLEXCOMM_PERIPH_LPI2CAndLPUART)
-    {
-        return true;
-    }
-    else
-    {
-        return false;
-    }
-}
-
-/*! @brief Returns for LP_FLEXCOMM base address. */
-uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance)
-{
-    if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs))
-    {
-        return s_lpflexcommBaseAddrs[instance];
-    }
-    return 0U;
-}
-
-/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
-uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance)
-{
-    LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
-    return base->ISTAT;
-}
-
-/* Get the index corresponding to the LP_FLEXCOMM */
-/*! brief Returns instance number for LP_FLEXCOMM module with given base address. */
-uint32_t LP_FLEXCOMM_GetInstance(void *base)
-{
-    uint32_t i;
-    pvoid_to_u32_t BaseAddr;
-    BaseAddr.pvoid = base;
-
-    for (i = 0U; i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs); i++)
-    {
-        if (BaseAddr.u32 == s_lpflexcommBaseAddrs[i])
-        {
-            break;
-        }
-    }
-
-    assert(i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
-    return i;
-}
-
-/* Changes LP_FLEXCOMM mode */
-static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock)
-{
-    assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART);
-    LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
-
-    /* Check whether peripheral type is present */
-    if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph))
-    {
-        return kStatus_OutOfRange;
-    }
-
-    /* Flexcomm is locked to different peripheral type than expected  */
-    if (((base->PSELID & LP_FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
-        ((base->PSELID & LP_FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
-    {
-        return kStatus_Fail;
-    }
-
-    /* Check if we are asked to lock */
-    if (lock != 0)
-    {
-        base->PSELID = (uint32_t)periph | LP_FLEXCOMM_PSELID_LOCK_MASK;
-    }
-    else
-    {
-        base->PSELID = (uint32_t)periph;
-    }
-
-    return kStatus_Success;
-}
-
-/*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
-status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
-{
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the peripheral clock */
-    CLOCK_EnableClock(s_lpflexcommClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
-    /* Reset the LP_FLEXCOMM module before configuring it.*/
-    RESET_ClearPeripheralReset(s_lpflexcommResets[instance]);
-#endif
-    /* Set the LP_FLEXCOMM to given peripheral */
-    return LP_FLEXCOMM_SetPeriph(instance, periph, 0);
-}
-
-/*! brief Deinitializes LP_FLEXCOMM. */
-void LP_FLEXCOMM_Deinit(uint32_t instance)
-{
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the peripheral clock */
-    CLOCK_DisableClock(s_lpflexcommClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-    RESET_SetPeripheralReset(s_lpflexcommResets[instance]);
-}
-
-/*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
- * LP_FLEXCOMM mode */
-void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
-                               lpflexcomm_irq_handler_t handler,
-                               void *lpflexcommHandle,
-                               LP_FLEXCOMM_PERIPH_T periph)
-{
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
-    /* Clear handler first to avoid execution of the handler with wrong handle */
-    s_lpflexcommIrqHandler[periph][instance] = NULL;
-    s_lpflexcommHandle[periph][instance]     = lpflexcommHandle;
-    s_lpflexcommIrqHandler[periph][instance] = handler;
-}
-
-static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance)
-{
-    uint32_t interruptStat;
-
-    interruptStat = LP_FLEXCOMM_GetInterruptStatus(instance);
-    if ((interruptStat &
-         ((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag | (uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U)
-    {
-        if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance] != NULL)
-        {
-            s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance](
-                instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C][instance]);
-        }
-    }
-    if ((interruptStat & ((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag | (uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U)
-    {
-        if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance] != NULL)
-        {
-            s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance](
-                instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPUART][instance]);
-        }
-    }
-    if (((interruptStat & (uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U)
-    {
-        if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance] != NULL)
-        {
-            s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance](
-                instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPSPI][instance]);
-        }
-    }
-    SDK_ISR_EXIT_BARRIER;
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-#if defined(LP_FLEXCOMM0)
-void LP_FLEXCOMM0_DriverIRQHandler(void);
-void LP_FLEXCOMM0_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(0U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM1)
-void LP_FLEXCOMM1_DriverIRQHandler(void);
-void LP_FLEXCOMM1_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(1U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM2)
-void LP_FLEXCOMM2_DriverIRQHandler(void);
-void LP_FLEXCOMM2_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(2U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM3)
-void LP_FLEXCOMM3_DriverIRQHandler(void);
-void LP_FLEXCOMM3_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(3U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM4)
-void LP_FLEXCOMM4_DriverIRQHandler(void);
-void LP_FLEXCOMM4_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(4U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM5)
-void LP_FLEXCOMM5_DriverIRQHandler(void);
-void LP_FLEXCOMM5_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(5U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM6)
-void LP_FLEXCOMM6_DriverIRQHandler(void);
-void LP_FLEXCOMM6_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(6U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM7)
-void LP_FLEXCOMM7_DriverIRQHandler(void);
-void LP_FLEXCOMM7_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(7U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM8)
-void LP_FLEXCOMM8_DriverIRQHandler(void);
-void LP_FLEXCOMM8_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(8U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM9)
-void LP_FLEXCOMM9_DriverIRQHandler(void);
-void LP_FLEXCOMM9_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(9U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM10)
-void LP_FLEXCOMM10_DriverIRQHandler(void);
-void LP_FLEXCOMM10_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(10U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM11)
-void LP_FLEXCOMM11_DriverIRQHandler(void);
-void LP_FLEXCOMM11_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(11U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM12)
-void LP_FLEXCOMM12_DriverIRQHandler(void);
-void LP_FLEXCOMM12_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(12U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM13)
-void LP_FLEXCOMM13_DriverIRQHandler(void);
-void LP_FLEXCOMM13_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(13U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM17)
-void LP_FLEXCOMM17_DriverIRQHandler(void);
-void LP_FLEXCOMM17_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(17U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM18)
-void LP_FLEXCOMM18_DriverIRQHandler(void);
-void LP_FLEXCOMM18_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(18U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM19)
-void LP_FLEXCOMM19_DriverIRQHandler(void);
-void LP_FLEXCOMM19_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(19U);
-}
-#endif
-
-#if defined(LP_FLEXCOMM20)
-void LP_FLEXCOMM20_DriverIRQHandler(void);
-void LP_FLEXCOMM20_DriverIRQHandler(void)
-{
-    LP_FLEXCOMM_CommonIRQHandler(20U);
-}
-#endif

examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/drivers/fsl_lpflexcomm.h

@@ -1,88 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef FSL_LP_FLEXCOMM_H_
-#define FSL_LP_FLEXCOMM_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpflexcomm_driver
- * @{
- */
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief FlexCOMM driver version. */
-#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
-/*@}*/
-
-/*! @brief LP_FLEXCOMM peripheral modes. */
-typedef enum
-{
-    LP_FLEXCOMM_PERIPH_NONE,               /*!< No peripheral */
-    LP_FLEXCOMM_PERIPH_LPUART,             /*!< LPUART peripheral */
-    LP_FLEXCOMM_PERIPH_LPSPI,              /*!< LPSPI Peripheral */
-    LP_FLEXCOMM_PERIPH_LPI2C,              /*!< LPI2C Peripheral */
-    LP_FLEXCOMM_PERIPH_LPI2CAndLPUART = 7, /*!< LPI2C and LPUART Peripheral */
-} LP_FLEXCOMM_PERIPH_T;
-
-/*! @brief LP_FLEXCOMM interrupt source flags. */
-enum _lpflexcomm_interrupt_flag
-{
-    kLPFLEXCOMM_I2cSlaveInterruptFlag  = LP_FLEXCOMM_ISTAT_I2CS_MASK,   /* LPI2C slave interrupt. */
-    kLPFLEXCOMM_I2cMasterInterruptFlag = LP_FLEXCOMM_ISTAT_I2CM_MASK,   /* LPI2C master interrupt. */
-    kLPFLEXCOMM_SpiInterruptFlag       = LP_FLEXCOMM_ISTAT_SPI_MASK,    /* LPSPI interrupt. */
-    kLPFLEXCOMM_UartRxInterruptFlag    = LP_FLEXCOMM_ISTAT_UARTRX_MASK, /* LPUART RX interrupt. */
-    kLPFLEXCOMM_UartTxInterruptFlag    = LP_FLEXCOMM_ISTAT_UARTTX_MASK, /* LPUART TX interrupt. */
-
-    kLPFLEXCOMM_AllInterruptFlag = kLPFLEXCOMM_I2cSlaveInterruptFlag | kLPFLEXCOMM_I2cMasterInterruptFlag |
-                                   kLPFLEXCOMM_SpiInterruptFlag | kLPFLEXCOMM_UartRxInterruptFlag |
-                                   kLPFLEXCOMM_UartTxInterruptFlag,
-};
-
-/*! @brief Typedef for interrupt handler. */
-typedef void (*lpflexcomm_irq_handler_t)(uint32_t instance, void *handle);
-
-/*! @brief Array with IRQ number for each LP_FLEXCOMM module. */
-extern IRQn_Type const kFlexcommIrqs[];
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */
-uint32_t LP_FLEXCOMM_GetInstance(void *base);
-
-/*! @brief Returns for LP_FLEXCOMM base address. */
-uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance);
-
-/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
-uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance);
-
-/*! @brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
-status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph);
-
-/*! @brief Deinitializes LP_FLEXCOMM. */
-void LP_FLEXCOMM_Deinit(uint32_t instance);
-
-/*! @brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
- * LP_FLEXCOMM mode */
-void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
-                               lpflexcomm_irq_handler_t handler,
-                               void *lpflexcommHandle,
-                               LP_FLEXCOMM_PERIPH_T periph);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*@}*/
-
-#endif /* FSL_LP_FLEXCOMM_H_*/